Searched defs:SU (Results 26 - 37 of 37) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUSubtarget.cpp789 const SUnit *SU = SI.getSUnit(); local
797 const SUnit *SU = Preds.pop_back_val(); local
817 SUnit *SU = Worklist.pop_back_val(); local
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H A DGCNHazardRecognizer.cpp53 void GCNHazardRecognizer::EmitInstruction(SUnit *SU) { argument
132 GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument
H A DSIMachineScheduler.h171 SUnit *SU = nullptr; member in struct:llvm::SIScheduleBlock::SISchedCandidate
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H A DSIMachineScheduler.cpp197 void SIScheduleBlock::addUnit(SUnit *SU) { argument
299 SUnit *SU = TopReadySUs[0]; local
417 SUnit *SU = pickNode(); local
453 undoReleaseSucc(SUnit *SU, SDep *SuccEdge) argument
463 releaseSucc(SUnit *SU, SDep *SuccEdge) argument
483 releaseSuccessors(SUnit *SU, bool InOrOutBlock) argument
499 nodeScheduled(SUnit *SU) argument
646 isSUInBlock(SUnit *SU, unsigned ID) argument
656 SUnit *SU = &DAG->SUnits[i]; local
664 hasDataDependencyPred(const SUnit &SU, const SUnit &FromSU) argument
682 SUnit *SU = &DAG->SUnits[i]; local
698 const SUnit &SU = DAG->SUnits[SUNum]; local
811 SUnit *SU = &DAG->SUnits[SUNum]; local
853 SUnit *SU = &DAG->SUnits[SUNum]; local
899 SUnit *SU = &DAG->SUnits[i]; local
936 SUnit *SU = &DAG->SUnits[SUNum]; local
980 SUnit *SU = &DAG->SUnits[i]; local
1006 SUnit *SU = &DAG->SUnits[SUNum]; local
1032 SUnit *SU = &DAG->SUnits[SUNum]; local
1053 SUnit *SU = &DAG->SUnits[SUNum]; local
1075 SUnit *SU = &DAG->SUnits[SUNum]; local
1081 SUnit *SU = &DAG->SUnits[SUNum]; local
1114 SUnit *SU = &DAG->SUnits[SUNum]; local
1146 const SUnit &SU = DAG->SUnits[SUNum]; local
1221 SUnit *SU = &DAG->SUnits[i]; local
1235 SUnit *SU = &DAG->SUnits[i]; local
1827 SUnit *SU = &SUnits[ScheduledSUnits[i]]; local
1949 SUnit *SU = &SUnits[i]; local
2025 SUnit *SU = &SUnits[*I]; local
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/freebsd-13-stable/libexec/getty/
H A Dgettytab.h80 #define SU gettystrs[18].value macro
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachinePipeliner.h273 unsigned getInstrBaseReg(SUnit *SU) { argument
354 bool insert(SUnit *SU) { return Nodes.insert(SU); } argument
376 void setExceedPressure(SUnit *SU) { ExceedPressure = SU; } argument
378 bool isExceedSU(SUnit *SU) { retur argument
563 isScheduledAtStage(SUnit *SU, unsigned StageNum) argument
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H A DScheduleDAG.h384 bool addPredBarrier(SUnit *SU) { argument
483 inline void SDep::setSUnit(SUnit *SU) { Dep.setPointer(SU); } argument
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H A DMachineScheduler.h456 PressureDiff &getPressureDiff(const SUnit *SU) { argument
559 find(SUnit *SU) argument
561 push(SUnit *SU) argument
853 SUnit *SU; member in struct:llvm::GenericSchedulerBase::SchedCandidate
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp212 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { argument
218 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { argument
225 void AddPredQueued(SUnit *SU, const SDep &D) { argument
233 AddPred(SUnit *SU, const SDep &D) argument
241 RemovePred(SUnit *SU, const SDep &D) argument
247 isReady(SUnit *SU) argument
398 ReleasePred(SUnit *SU, const SDep *PredEdge) argument
554 ReleasePredecessors(SUnit *SU) argument
651 AdvancePastStalls(SUnit *SU) argument
693 EmitNode(SUnit *SU) argument
736 ScheduleNodeBottomUp(SUnit *SU) argument
835 UnscheduleNodeBottomUp(SUnit *SU) argument
938 SUnit *SU = *I; local
948 BacktrackBottomUp(SUnit *SU, SUnit *BtSU) argument
970 isOperandOf(const SUnit *SU, SDNode *N) argument
980 TryUnfoldSU(SUnit *SU) argument
1134 CopyAndMoveSuccessors(SUnit *SU) argument
1222 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument
1297 CheckForLiveRegDef(SUnit *SU, unsigned Reg, SUnit **LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs, const TargetRegisterInfo *TRI) argument
1319 CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, ArrayRef<SUnit*> LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs) argument
1346 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) argument
1437 SUnit *SU = Interferences[i-1]; local
1618 SUnit *SU = PickNodeToScheduleBottomUp(); local
1906 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); variable
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DScheduleDAGInstrs.cpp230 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { argument
290 addPhysRegDeps(SUnit *SU, unsigned OperIdx) argument
394 addVRegDefDeps(SUnit *SU, unsigned OperIdx) argument
514 addVRegUseDeps(SUnit *SU, unsigned OperIdx) argument
575 SUnit *SU = newSUnit(&MI); local
629 insert(SUnit *SU, ValueType V) argument
667 addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap) argument
674 addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap, ValueType V) argument
814 SUnit *SU = MISUnitMap[&MI]; local
1259 visitPreorder(const SUnit *SU) argument
1267 visitPostorderNode(const SUnit *SU) argument
1416 follow(const SUnit *SU) argument
1437 hasDataSucc(const SUnit *SU) argument
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H A DMachinePipeliner.cpp679 const SUnit *SU = Worklist.pop_back_val(); local
853 SUnit *SU = getSUnit(UseMI); local
873 SUnit *SU = getSUnit(DefMI); local
1190 SUnit *SU = &SUnits[i]; local
1202 SUnit *SU = I->first; local
1457 SUnit *SU = &SUnits[*I]; local
1481 SUnit *SU = &SUnits[*I]; local
1802 SUnit *SU = &SUnits[i]; local
1813 addConnectedNodes(SUnit *SU, NodeSet &NewSet, SetVector<SUnit *> &NodesAdded) argument
1835 SUnit *SU = Set1[i]; local
2053 SUnit *SU = *NI; local
2238 SUnit *SU = getSUnit(MI); local
2377 insert(SUnit *SU, int StartCycle, int EndCycle, int II) argument
2480 multipleIterations(SUnit *SU, SwingSchedulerDAG *DAG) argument
2491 computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int *MinEnd, int *MaxStart, int II, SwingSchedulerDAG *DAG) argument
2552 orderDependence(SwingSchedulerDAG *SSD, SUnit *SU, std::deque<SUnit *> &Insts) argument
2737 SUnit &SU = SSD->SUnits[i]; local
2785 SUnit *SU = NodeOrder[i]; local
2924 SUnit *SU = &SSD->SUnits[i]; local
2934 SUnit *SU = cycleInstrs[i]; local
2940 SUnit *SU = cycleInstrs[i]; local
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H A DMachineScheduler.cpp620 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { argument
648 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { argument
657 releasePred(SUnit *SU, SDep *PredEdge) argument
685 releasePredecessors(SUnit *SU) argument
775 SUnit *SU = SchedImpl->pickNode(IsTopNode); local
878 updateQueues(SUnit *SU, bool IsTopNode) argument
931 collectVRegUses(SUnit &SU) argument
1070 updateScheduledPressure(const SUnit *SU, const std::vector<unsigned> &NewMaxPressure) argument
1115 SUnit &SU = *V2SU.SU; local
1147 SUnit *SU = V2SU.SU; local
1223 SUnit *SU = SchedImpl->pickNode(IsTopNode); local
1344 SUnit *SU = V2SU.SU; local
1389 scheduleMI(SUnit *SU, bool IsTopNode) argument
1473 SUnit *SU; member in struct:__anon3520::BaseMemOpClusterMutation::MemOpInfo
1478 MemOpInfo(SUnit *SU, ArrayRef<const MachineOperand *> BaseOps, int64_t Offset, unsigned Width) argument
1976 getLatencyStallCycles(SUnit *SU) argument
2036 checkHazard(SUnit *SU) argument
2130 releaseNode(SUnit *SU, unsigned ReadyCycle, bool InPQueue, unsigned Idx) argument
2249 bumpNode(SUnit *SU) argument
2401 SUnit *SU = *(Pending.begin() + I); local
2420 removeReady(SUnit *SU) argument
2947 getWeakLeft(const SUnit *SU, bool isTop) argument
2958 biasPhysReg(const SUnit *SU, bool isTop) argument
2995 initCandidate(SchedCandidate &Cand, SUnit *SU, bool AtTop, const RegPressureTracker &RPTracker, RegPressureTracker &TempTracker) argument
3261 SUnit *SU; local
3300 reschedulePhysReg(SUnit *SU, bool isTop) argument
3331 schedNode(SUnit *SU, bool IsTopNode) argument
3467 SUnit *SU; local
3495 schedNode(SUnit *SU, bool IsTopNode) argument
3575 SUnit *SU = ReadyQ.back(); variable
3670 SUnit *SU; variable
3758 getNodeLabel(const SUnit *SU, const ScheduleDAG *G) argument
3770 getNodeDescription(const SUnit *SU, const ScheduleDAG *G) argument
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