Lines Matching defs:SU
103 dbgs() << "SU(" << su->NodeNum << ")";
228 /// MO is an operand of SU's instruction that defines a physical register. Adds
229 /// data dependencies from SU to any uses of the physical register.
230 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
231 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
239 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc();
247 SUnit *UseSU = I->SU;
248 if (UseSU == SU)
257 Dep = SDep(SU, SDep::Artificial);
261 SU->hasPhysRegDefs = true;
262 Dep = SDep(SU, SDep::Data, *Alias);
271 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
273 ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep);
278 if (SU->getInstr()->isBundle() || (RegUse && RegUse->isBundle()))
279 ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep);
290 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
291 MachineInstr *MI = SU->getInstr();
311 SUnit *DefSU = I->SU;
314 if (DefSU != SU &&
317 SDep Dep(SU, Kind, /*Reg=*/*Alias);
321 ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep);
328 SU->hasPhysRegUses = true;
332 Uses.insert(PhysRegSUOper(SU, OperIdx, Reg));
336 addPhysRegDataDeps(SU, OperIdx);
345 if (MO.isDead() && SU->isCall) {
356 if (!I->SU->isCall)
363 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
394 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
395 MachineInstr *MI = SU->getInstr();
443 SUnit *UseSU = I->SU;
445 SDep Dep(SU, SDep::Data, Reg);
448 ST.adjustSchedDependency(SU, OperIdx, UseSU, I->OperandIndex, Dep);
480 SUnit *DefSU = V2SU.SU;
486 if (DefSU == SU)
488 SDep Dep(SU, SDep::Output, Reg);
498 V2SU.SU = SU;
505 CurrentVRegDefs.insert(VReg2SUnit(Reg, LaneMask, SU));
514 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
515 const MachineInstr *MI = SU->getInstr();
522 CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));
531 if (V2SU.SU == SU)
534 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg));
575 SUnit *SU = newSUnit(&MI);
576 MISUnitMap[&MI] = SU;
578 SU->isCall = MI.isCall();
579 SU->isCommutable = MI.isCommutable();
581 // Assign the Latency field of SU using target-provided information.
582 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
593 const MCSchedClassDesc *SC = getSchedClass(SU);
599 SU->hasReservedResource = true;
602 SU->isUnbuffered = true;
627 /// Adds SU to the SUList of V. If Map grows huge, reduce its size by calling
629 void inline insert(SUnit *SU, ValueType V) {
630 MapVector::operator[](V).push_back(SU);
667 void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
670 addChainDependencies(SU, I.second,
674 void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
679 addChainDependencies(SU, Itr->second,
688 for (auto *SU : sus)
689 SU->addPredBarrier(BarrierChain);
753 // objects. The SU is then inserted in the SUList(s) mapped from the
760 // Certain memory accesses are known to not alias any SU in Stores
814 SUnit *SU = MISUnitMap[&MI];
815 assert(SU && "No SUnit mapped to this MI");
825 PDiffs->addInstruction(SU->NodeNum, RegOpers, MRI);
849 addPhysRegDeps(SU, j);
852 addVRegDefDeps(SU, j);
866 addPhysRegDeps(SU, j);
868 addVRegUseDeps(SU, j);
878 if (SU->NumSuccs == 0 && SU->Latency > 1 && (HasVRegDef || MI.mayLoad())) {
879 SDep Dep(SU, SDep::Artificial);
880 Dep.setLatency(SU->Latency - 1);
893 BarrierChain->addPredBarrier(SU);
894 BarrierChain = SU;
896 LLVM_DEBUG(dbgs() << "Global memory object and new barrier chain: SU("
913 BarrierChain->addPredBarrier(SU);
915 FPExceptions.insert(SU, UnknownValue);
931 BarrierChain->addPredBarrier(SU);
935 // SU depends on.
943 addChainDependencies(SU, Stores);
944 addChainDependencies(SU, NonAliasStores);
945 addChainDependencies(SU, Loads);
946 addChainDependencies(SU, NonAliasLoads);
949 Stores.insert(SU, UnknownValue);
958 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
959 addChainDependencies(SU, (ThisMayAlias ? Loads : NonAliasLoads), V);
968 (ThisMayAlias ? Stores : NonAliasStores).insert(SU, V);
972 addChainDependencies(SU, Loads, UnknownValue);
973 addChainDependencies(SU, Stores, UnknownValue);
975 } else { // SU is a load.
978 addChainDependencies(SU, Stores);
979 addChainDependencies(SU, NonAliasStores);
981 Loads.insert(SU, UnknownValue);
989 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
992 (ThisMayAlias ? Loads : NonAliasLoads).insert(SU, V);
995 addChainDependencies(SU, Stores, UnknownValue);
1051 // Insert all SU's NodeNums into a vector and sort it.
1055 for (auto *SU : I.second)
1056 NodeNums.push_back(SU->NodeNum);
1058 for (auto *SU : I.second)
1059 NodeNums.push_back(SU->NodeNum);
1062 // The N last elements in NodeNums will be removed, and the SU with
1075 LLVM_DEBUG(dbgs() << "Inserting new barrier chain: SU("
1079 LLVM_DEBUG(dbgs() << "Keeping old barrier chain: SU("
1160 void ScheduleDAGInstrs::dumpNode(const SUnit &SU) const {
1162 dumpNodeName(SU);
1164 SU.getInstr()->dump();
1172 for (const SUnit &SU : SUnits)
1173 dumpNodeAll(SU);
1179 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1182 if (SU == &EntrySU)
1184 else if (SU == &ExitSU)
1187 SU->getInstr()->print(oss, /*SkipOpers=*/true);
1252 bool isVisited(const SUnit *SU) const {
1253 return R.DFSNodeData[SU->NodeNum].SubtreeID
1259 void visitPreorder(const SUnit *SU) {
1260 R.DFSNodeData[SU->NodeNum].InstrCount =
1261 SU->getInstr()->isTransient() ? 0 : 1;
1267 void visitPostorderNode(const SUnit *SU) {
1270 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
1271 RootData RData(SU->NodeNum);
1272 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
1279 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
1280 for (const SDep &PredDep : SU->Preds) {
1285 joinPredSubtree(PredDep, SU, /*CheckLimit=*/false);
1292 RootSet[PredNum].ParentNodeID = SU->NodeNum;
1303 RootSet[SU->NodeNum] = RData;
1342 LLVM_DEBUG(dbgs() << " SU(" << Idx << ") in tree "
1416 void follow(const SUnit *SU) {
1417 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
1437 static bool hasDataSucc(const SUnit *SU) {
1438 for (const SDep &SuccDep : SU->Succs) {
1453 for (const SUnit &SU : SUnits) {
1454 if (Impl.isVisited(&SU) || hasDataSucc(&SU))
1458 Impl.visitPreorder(&SU);
1459 DFS.follow(&SU);