| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | RegisterBank.h | 92 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) { argument
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| H A D | RegisterBankInfo.h | 60 const RegisterBank *RegBank; member in struct:llvm::RegisterBankInfo::PartialMapping
65 PartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.h | 53 mutable std::unique_ptr<CodeGenRegBank> RegBank; member in class:llvm::CodeGenTarget
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| H A D | CodeGenTarget.cpp | 325 getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy, CodeGenRegBank &RegBank, const CodeGenSubRegIndex *SubIdx) const argument
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| H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); local
208 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, argument
706 emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, const std::string &ClName) argument
776 emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank, const std::string &ClName) argument
877 runMCDesc(raw_ostream &OS, CodeGenTarget &Target, CodeGenRegBank &RegBank) argument
1142 runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, CodeGenRegBank &RegBank) argument
1212 runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, CodeGenRegBank &RegBank) argument
1617 CodeGenRegBank &RegBank = Target.getRegBank(); local
1628 CodeGenRegBank &RegBank = Target.getRegBank(); local
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| H A D | CodeGenRegisters.cpp | 76 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) { argument
168 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) { argument
255 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) { argument
267 CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) { argument
465 computeSecondarySubRegs(CodeGenRegBank &RegBank) argument
546 computeSuperRegs(CodeGenRegBank &RegBank) argument
741 CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) argument
815 CodeGenRegisterClass(CodeGenRegBank &RegBank, StringRef Name, Key Props) argument
829 inheritProperties(CodeGenRegBank &RegBank) argument
944 computeSubClasses(CodeGenRegBank &RegBank) argument
995 getMatchingSubClassWithSubRegs( CodeGenRegBank &RegBank, const CodeGenSubRegIndex *SubIdx) const argument
1088 buildRegUnitSet(const CodeGenRegBank &RegBank, std::vector<unsigned> &RegUnits) const argument
1599 computeUberSets(std::vector<UberRegSet> &UberSets, std::vector<UberRegSet*> &RegSets, CodeGenRegBank &RegBank) argument
1660 computeUberWeights(std::vector<UberRegSet> &UberSets, CodeGenRegBank &RegBank) argument
1717 normalizeWeight(CodeGenRegister *Reg, std::vector<UberRegSet> &UberSets, std::vector<UberRegSet*> &RegSets, BitVector &NormalRegs, CodeGenRegister::RegUnitList &NormalUnits, CodeGenRegBank &RegBank) argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/ |
| H A D | MIParser.h | 42 const RegisterBank *RegBank; member in union:llvm::VRegInfo::__anon3155
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 543 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value); local
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| H A D | MIParser.cpp | 298 const auto &RegBank = RBI->getRegBank(I); local
1343 const RegisterBank *RegBank = nullptr; local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 63 setRegBank(Register Reg, const RegisterBank &RegBank) argument
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| H A D | MachineVerifier.cpp | 1725 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); local
125 const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg)); local
267 hashPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank *RegBank) argument
531 OS << *RegBank; local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); local
1089 unsigned RegBank local
357 selectLoadStoreOpCode(unsigned Opc, unsigned RegBank, unsigned Size) const argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 200 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); local
1369 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); local
1438 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1891 extendLow32IntoHigh32(MachineIRBuilder &B, Register Hi32Reg, Register Lo32Reg, unsigned ExtOpc, const RegisterBank &RegBank, bool IsBooleanSrc = false) argument
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