Lines Matching defs:RegBank
62 CodeGenRegBank &RegBank = Target.getRegBank();
63 RegBank.computeDerivedInfo();
91 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
93 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
95 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
208 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
210 unsigned NumRCs = RegBank.getRegClasses().size();
211 unsigned NumSets = RegBank.getNumRegPressureSets();
217 for (const auto &RC : RegBank.getRegClasses()) {
219 OS << " {" << RC.getWeight(RegBank) << ", ";
224 RC.buildRegUnitSet(RegBank, RegUnits);
225 OS << RegBank.getRegUnitSetWeight(RegUnits);
236 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
238 if (RegBank.getRegUnit(UnitIdx).Weight > 1)
244 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
248 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
250 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
274 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
290 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
302 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();
306 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
310 PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order);
342 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
346 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
348 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])
707 CodeGenRegBank &RegBank,
709 const auto &SubRegIndices = RegBank.getSubRegIndices();
777 CodeGenRegBank &RegBank,
780 const auto &SubRegIndices = RegBank.getSubRegIndices();
878 CodeGenRegBank &RegBank) {
884 const auto &Regs = RegBank.getRegisters();
886 auto &SubRegIndices = RegBank.getSubRegIndices();
918 Reg.addSubRegsPreOrder(SR, RegBank);
1031 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
1032 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
1042 const auto &RegisterClasses = RegBank.getRegClasses();
1126 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "
1143 CodeGenRegBank &RegBank) {
1162 if (!RegBank.getSubRegIndices().empty()) {
1190 const auto &RegisterClasses = RegBank.getRegClasses();
1213 CodeGenRegBank &RegBank){
1226 const auto &RegisterClasses = RegBank.getRegClasses();
1227 const auto &SubRegIndices = RegBank.getSubRegIndices();
1450 const auto &Regs = RegBank.getRegisters();
1466 emitComposeSubRegIndices(OS, RegBank, ClassName);
1467 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName);
1502 EmitRegUnitPressure(OS, RegBank, ClassName);
1525 printMask(OS, RegBank.CoveringLanes);
1531 << " " << RegBank.getNumNativeRegUnits() << ",\n"
1550 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1561 BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
1568 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
1569 Covered |= RegBank.computeCoveredRegisters(
1617 CodeGenRegBank &RegBank = Target.getRegBank();
1618 runEnums(OS, Target, RegBank);
1619 runMCDesc(OS, Target, RegBank);
1620 runTargetHeader(OS, Target, RegBank);
1621 runTargetDesc(OS, Target, RegBank);
1628 CodeGenRegBank &RegBank = Target.getRegBank();
1637 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) {
1656 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) {
1669 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) {
1675 for (const CodeGenRegister &R : RegBank.getRegisters()) {