1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This tablegen backend is responsible for emitting a description of a target 10// register file for a code generator. It uses instances of the Register, 11// RegisterAliases, and RegisterClass classes to gather this information. 12// 13//===----------------------------------------------------------------------===// 14 15#include "CodeGenRegisters.h" 16#include "CodeGenTarget.h" 17#include "SequenceToOffsetTable.h" 18#include "Types.h" 19#include "llvm/ADT/ArrayRef.h" 20#include "llvm/ADT/BitVector.h" 21#include "llvm/ADT/STLExtras.h" 22#include "llvm/ADT/SetVector.h" 23#include "llvm/ADT/SmallVector.h" 24#include "llvm/ADT/SparseBitVector.h" 25#include "llvm/ADT/Twine.h" 26#include "llvm/Support/Casting.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Format.h" 29#include "llvm/Support/MachineValueType.h" 30#include "llvm/Support/raw_ostream.h" 31#include "llvm/TableGen/Error.h" 32#include "llvm/TableGen/Record.h" 33#include "llvm/TableGen/SetTheory.h" 34#include "llvm/TableGen/TableGenBackend.h" 35#include <algorithm> 36#include <cassert> 37#include <cstddef> 38#include <cstdint> 39#include <deque> 40#include <iterator> 41#include <set> 42#include <string> 43#include <vector> 44 45using namespace llvm; 46 47cl::OptionCategory RegisterInfoCat("Options for -gen-register-info"); 48 49static cl::opt<bool> 50 RegisterInfoDebug("register-info-debug", cl::init(false), 51 cl::desc("Dump register information to help debugging"), 52 cl::cat(RegisterInfoCat)); 53 54namespace { 55 56class RegisterInfoEmitter { 57 CodeGenTarget Target; 58 RecordKeeper &Records; 59 60public: 61 RegisterInfoEmitter(RecordKeeper &R) : Target(R), Records(R) { 62 CodeGenRegBank &RegBank = Target.getRegBank(); 63 RegBank.computeDerivedInfo(); 64 } 65 66 // runEnums - Print out enum values for all of the registers. 67 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 68 69 // runMCDesc - Print out MC register descriptions. 70 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 71 72 // runTargetHeader - Emit a header fragment for the register info emitter. 73 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target, 74 CodeGenRegBank &Bank); 75 76 // runTargetDesc - Output the target register and register file descriptions. 77 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, 78 CodeGenRegBank &Bank); 79 80 // run - Output the register file description. 81 void run(raw_ostream &o); 82 83 void debugDump(raw_ostream &OS); 84 85private: 86 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs, 87 bool isCtor); 88 void EmitRegMappingTables(raw_ostream &o, 89 const std::deque<CodeGenRegister> &Regs, 90 bool isCtor); 91 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 92 const std::string &ClassName); 93 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, 94 const std::string &ClassName); 95 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank, 96 const std::string &ClassName); 97}; 98 99} // end anonymous namespace 100 101// runEnums - Print out enum values for all of the registers. 102void RegisterInfoEmitter::runEnums(raw_ostream &OS, 103 CodeGenTarget &Target, CodeGenRegBank &Bank) { 104 const auto &Registers = Bank.getRegisters(); 105 106 // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 107 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 108 109 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); 110 111 emitSourceFileHeader("Target Register Enum Values", OS); 112 113 OS << "\n#ifdef GET_REGINFO_ENUM\n"; 114 OS << "#undef GET_REGINFO_ENUM\n\n"; 115 116 OS << "namespace llvm {\n\n"; 117 118 OS << "class MCRegisterClass;\n" 119 << "extern const MCRegisterClass " << Target.getName() 120 << "MCRegisterClasses[];\n\n"; 121 122 if (!Namespace.empty()) 123 OS << "namespace " << Namespace << " {\n"; 124 OS << "enum {\n NoRegister,\n"; 125 126 for (const auto &Reg : Registers) 127 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; 128 assert(Registers.size() == Registers.back().EnumValue && 129 "Register enum value mismatch!"); 130 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 131 OS << "};\n"; 132 if (!Namespace.empty()) 133 OS << "} // end namespace " << Namespace << "\n"; 134 135 const auto &RegisterClasses = Bank.getRegClasses(); 136 if (!RegisterClasses.empty()) { 137 138 // RegisterClass enums are stored as uint16_t in the tables. 139 assert(RegisterClasses.size() <= 0xffff && 140 "Too many register classes to fit in tables"); 141 142 OS << "\n// Register classes\n\n"; 143 if (!Namespace.empty()) 144 OS << "namespace " << Namespace << " {\n"; 145 OS << "enum {\n"; 146 for (const auto &RC : RegisterClasses) 147 OS << " " << RC.getName() << "RegClassID" 148 << " = " << RC.EnumValue << ",\n"; 149 OS << "\n };\n"; 150 if (!Namespace.empty()) 151 OS << "} // end namespace " << Namespace << "\n\n"; 152 } 153 154 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices(); 155 // If the only definition is the default NoRegAltName, we don't need to 156 // emit anything. 157 if (RegAltNameIndices.size() > 1) { 158 OS << "\n// Register alternate name indices\n\n"; 159 if (!Namespace.empty()) 160 OS << "namespace " << Namespace << " {\n"; 161 OS << "enum {\n"; 162 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 163 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 164 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 165 OS << "};\n"; 166 if (!Namespace.empty()) 167 OS << "} // end namespace " << Namespace << "\n\n"; 168 } 169 170 auto &SubRegIndices = Bank.getSubRegIndices(); 171 if (!SubRegIndices.empty()) { 172 OS << "\n// Subregister indices\n\n"; 173 std::string Namespace = SubRegIndices.front().getNamespace(); 174 if (!Namespace.empty()) 175 OS << "namespace " << Namespace << " {\n"; 176 OS << "enum : uint16_t {\n NoSubRegister,\n"; 177 unsigned i = 0; 178 for (const auto &Idx : SubRegIndices) 179 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; 180 OS << " NUM_TARGET_SUBREGS\n};\n"; 181 if (!Namespace.empty()) 182 OS << "} // end namespace " << Namespace << "\n\n"; 183 } 184 185 OS << "// Register pressure sets enum.\n"; 186 if (!Namespace.empty()) 187 OS << "namespace " << Namespace << " {\n"; 188 OS << "enum RegisterPressureSets {\n"; 189 unsigned NumSets = Bank.getNumRegPressureSets(); 190 for (unsigned i = 0; i < NumSets; ++i ) { 191 const RegUnitSet &RegUnits = Bank.getRegSetAt(i); 192 OS << " " << RegUnits.Name << " = " << i << ",\n"; 193 } 194 OS << "};\n"; 195 if (!Namespace.empty()) 196 OS << "} // end namespace " << Namespace << '\n'; 197 OS << '\n'; 198 199 OS << "} // end namespace llvm\n\n"; 200 OS << "#endif // GET_REGINFO_ENUM\n\n"; 201} 202 203static void printInt(raw_ostream &OS, int Val) { 204 OS << Val; 205} 206 207void RegisterInfoEmitter:: 208EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 209 const std::string &ClassName) { 210 unsigned NumRCs = RegBank.getRegClasses().size(); 211 unsigned NumSets = RegBank.getNumRegPressureSets(); 212 213 OS << "/// Get the weight in units of pressure for this register class.\n" 214 << "const RegClassWeight &" << ClassName << "::\n" 215 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 216 << " static const RegClassWeight RCWeightTable[] = {\n"; 217 for (const auto &RC : RegBank.getRegClasses()) { 218 const CodeGenRegister::Vec &Regs = RC.getMembers(); 219 OS << " {" << RC.getWeight(RegBank) << ", "; 220 if (Regs.empty() || RC.Artificial) 221 OS << '0'; 222 else { 223 std::vector<unsigned> RegUnits; 224 RC.buildRegUnitSet(RegBank, RegUnits); 225 OS << RegBank.getRegUnitSetWeight(RegUnits); 226 } 227 OS << "}, \t// " << RC.getName() << "\n"; 228 } 229 OS << " };\n" 230 << " return RCWeightTable[RC->getID()];\n" 231 << "}\n\n"; 232 233 // Reasonable targets (not ARMv7) have unit weight for all units, so don't 234 // bother generating a table. 235 bool RegUnitsHaveUnitWeight = true; 236 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 237 UnitIdx < UnitEnd; ++UnitIdx) { 238 if (RegBank.getRegUnit(UnitIdx).Weight > 1) 239 RegUnitsHaveUnitWeight = false; 240 } 241 OS << "/// Get the weight in units of pressure for this register unit.\n" 242 << "unsigned " << ClassName << "::\n" 243 << "getRegUnitWeight(unsigned RegUnit) const {\n" 244 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 245 << " && \"invalid register unit\");\n"; 246 if (!RegUnitsHaveUnitWeight) { 247 OS << " static const uint8_t RUWeightTable[] = {\n "; 248 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 249 UnitIdx < UnitEnd; ++UnitIdx) { 250 const RegUnit &RU = RegBank.getRegUnit(UnitIdx); 251 assert(RU.Weight < 256 && "RegUnit too heavy"); 252 OS << RU.Weight << ", "; 253 } 254 OS << "};\n" 255 << " return RUWeightTable[RegUnit];\n"; 256 } 257 else { 258 OS << " // All register units have unit weight.\n" 259 << " return 1;\n"; 260 } 261 OS << "}\n\n"; 262 263 OS << "\n" 264 << "// Get the number of dimensions of register pressure.\n" 265 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n" 266 << " return " << NumSets << ";\n}\n\n"; 267 268 OS << "// Get the name of this register unit pressure set.\n" 269 << "const char *" << ClassName << "::\n" 270 << "getRegPressureSetName(unsigned Idx) const {\n" 271 << " static const char *const PressureNameTable[] = {\n"; 272 unsigned MaxRegUnitWeight = 0; 273 for (unsigned i = 0; i < NumSets; ++i ) { 274 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 275 MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight); 276 OS << " \"" << RegUnits.Name << "\",\n"; 277 } 278 OS << " };\n" 279 << " return PressureNameTable[Idx];\n" 280 << "}\n\n"; 281 282 OS << "// Get the register unit pressure limit for this dimension.\n" 283 << "// This limit must be adjusted dynamically for reserved registers.\n" 284 << "unsigned " << ClassName << "::\n" 285 << "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const " 286 "{\n" 287 << " static const " << getMinimalTypeForRange(MaxRegUnitWeight, 32) 288 << " PressureLimitTable[] = {\n"; 289 for (unsigned i = 0; i < NumSets; ++i ) { 290 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 291 OS << " " << RegUnits.Weight << ", \t// " << i << ": " 292 << RegUnits.Name << "\n"; 293 } 294 OS << " };\n" 295 << " return PressureLimitTable[Idx];\n" 296 << "}\n\n"; 297 298 SequenceToOffsetTable<std::vector<int>> PSetsSeqs; 299 300 // This table may be larger than NumRCs if some register units needed a list 301 // of unit sets that did not correspond to a register class. 302 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists(); 303 std::vector<std::vector<int>> PSets(NumRCUnitSets); 304 305 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) { 306 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); 307 PSets[i].reserve(PSetIDs.size()); 308 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(), 309 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { 310 PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order); 311 } 312 llvm::sort(PSets[i]); 313 PSetsSeqs.add(PSets[i]); 314 } 315 316 PSetsSeqs.layout(); 317 318 OS << "/// Table of pressure sets per register class or unit.\n" 319 << "static const int RCSetsTable[] = {\n"; 320 PSetsSeqs.emit(OS, printInt, "-1"); 321 OS << "};\n\n"; 322 323 OS << "/// Get the dimensions of register pressure impacted by this " 324 << "register class.\n" 325 << "/// Returns a -1 terminated array of pressure set IDs\n" 326 << "const int* " << ClassName << "::\n" 327 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; 328 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 329 << " RCSetStartTable[] = {\n "; 330 for (unsigned i = 0, e = NumRCs; i != e; ++i) { 331 OS << PSetsSeqs.get(PSets[i]) << ","; 332 } 333 OS << "};\n" 334 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n" 335 << "}\n\n"; 336 337 OS << "/// Get the dimensions of register pressure impacted by this " 338 << "register unit.\n" 339 << "/// Returns a -1 terminated array of pressure set IDs\n" 340 << "const int* " << ClassName << "::\n" 341 << "getRegUnitPressureSets(unsigned RegUnit) const {\n" 342 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 343 << " && \"invalid register unit\");\n"; 344 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 345 << " RUSetStartTable[] = {\n "; 346 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 347 UnitIdx < UnitEnd; ++UnitIdx) { 348 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) 349 << ","; 350 } 351 OS << "};\n" 352 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n" 353 << "}\n\n"; 354} 355 356using DwarfRegNumsMapPair = std::pair<Record*, std::vector<int64_t>>; 357using DwarfRegNumsVecTy = std::vector<DwarfRegNumsMapPair>; 358 359void finalizeDwarfRegNumsKeys(DwarfRegNumsVecTy &DwarfRegNums) { 360 // Sort and unique to get a map-like vector. We want the last assignment to 361 // match previous behaviour. 362 std::stable_sort(DwarfRegNums.begin(), DwarfRegNums.end(), 363 on_first<LessRecordRegister>()); 364 // Warn about duplicate assignments. 365 const Record *LastSeenReg = nullptr; 366 for (const auto &X : DwarfRegNums) { 367 const auto &Reg = X.first; 368 // The only way LessRecordRegister can return equal is if they're the same 369 // string. Use simple equality instead. 370 if (LastSeenReg && Reg->getName() == LastSeenReg->getName()) 371 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 372 getQualifiedName(Reg) + 373 "specified multiple times"); 374 LastSeenReg = Reg; 375 } 376 auto Last = std::unique( 377 DwarfRegNums.begin(), DwarfRegNums.end(), 378 [](const DwarfRegNumsMapPair &A, const DwarfRegNumsMapPair &B) { 379 return A.first->getName() == B.first->getName(); 380 }); 381 DwarfRegNums.erase(Last, DwarfRegNums.end()); 382} 383 384void RegisterInfoEmitter::EmitRegMappingTables( 385 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 386 // Collect all information about dwarf register numbers 387 DwarfRegNumsVecTy DwarfRegNums; 388 389 // First, just pull all provided information to the map 390 unsigned maxLength = 0; 391 for (auto &RE : Regs) { 392 Record *Reg = RE.TheDef; 393 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 394 maxLength = std::max((size_t)maxLength, RegNums.size()); 395 DwarfRegNums.emplace_back(Reg, std::move(RegNums)); 396 } 397 finalizeDwarfRegNumsKeys(DwarfRegNums); 398 399 if (!maxLength) 400 return; 401 402 // Now we know maximal length of number list. Append -1's, where needed 403 for (DwarfRegNumsVecTy::iterator I = DwarfRegNums.begin(), 404 E = DwarfRegNums.end(); 405 I != E; ++I) 406 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 407 I->second.push_back(-1); 408 409 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 410 411 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; 412 413 // Emit reverse information about the dwarf register numbers. 414 for (unsigned j = 0; j < 2; ++j) { 415 for (unsigned i = 0, e = maxLength; i != e; ++i) { 416 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 417 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 418 OS << i << "Dwarf2L[]"; 419 420 if (!isCtor) { 421 OS << " = {\n"; 422 423 // Store the mapping sorted by the LLVM reg num so lookup can be done 424 // with a binary search. 425 std::map<uint64_t, Record*> Dwarf2LMap; 426 for (DwarfRegNumsVecTy::iterator 427 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 428 int DwarfRegNo = I->second[i]; 429 if (DwarfRegNo < 0) 430 continue; 431 Dwarf2LMap[DwarfRegNo] = I->first; 432 } 433 434 for (std::map<uint64_t, Record*>::iterator 435 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I) 436 OS << " { " << I->first << "U, " << getQualifiedName(I->second) 437 << " },\n"; 438 439 OS << "};\n"; 440 } else { 441 OS << ";\n"; 442 } 443 444 // We have to store the size in a const global, it's used in multiple 445 // places. 446 OS << "extern const unsigned " << Namespace 447 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize"; 448 if (!isCtor) 449 OS << " = array_lengthof(" << Namespace 450 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 451 << "Dwarf2L);\n\n"; 452 else 453 OS << ";\n\n"; 454 } 455 } 456 457 for (auto &RE : Regs) { 458 Record *Reg = RE.TheDef; 459 const RecordVal *V = Reg->getValue("DwarfAlias"); 460 if (!V || !V->getValue()) 461 continue; 462 463 DefInit *DI = cast<DefInit>(V->getValue()); 464 Record *Alias = DI->getDef(); 465 const auto &AliasIter = 466 std::lower_bound(DwarfRegNums.begin(), DwarfRegNums.end(), Alias, 467 [](const DwarfRegNumsMapPair &A, const Record *B) { 468 return LessRecordRegister()(A.first, B); 469 }); 470 assert(AliasIter != DwarfRegNums.end() && AliasIter->first == Alias && 471 "Expected Alias to be present in map"); 472 const auto &RegIter = 473 std::lower_bound(DwarfRegNums.begin(), DwarfRegNums.end(), Reg, 474 [](const DwarfRegNumsMapPair &A, const Record *B) { 475 return LessRecordRegister()(A.first, B); 476 }); 477 assert(RegIter != DwarfRegNums.end() && RegIter->first == Reg && 478 "Expected Reg to be present in map"); 479 RegIter->second = AliasIter->second; 480 } 481 482 // Emit information about the dwarf register numbers. 483 for (unsigned j = 0; j < 2; ++j) { 484 for (unsigned i = 0, e = maxLength; i != e; ++i) { 485 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 486 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 487 OS << i << "L2Dwarf[]"; 488 if (!isCtor) { 489 OS << " = {\n"; 490 // Store the mapping sorted by the Dwarf reg num so lookup can be done 491 // with a binary search. 492 for (DwarfRegNumsVecTy::iterator 493 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 494 int RegNo = I->second[i]; 495 if (RegNo == -1) // -1 is the default value, don't emit a mapping. 496 continue; 497 498 OS << " { " << getQualifiedName(I->first) << ", " << RegNo 499 << "U },\n"; 500 } 501 OS << "};\n"; 502 } else { 503 OS << ";\n"; 504 } 505 506 // We have to store the size in a const global, it's used in multiple 507 // places. 508 OS << "extern const unsigned " << Namespace 509 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; 510 if (!isCtor) 511 OS << " = array_lengthof(" << Namespace 512 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n"; 513 else 514 OS << ";\n\n"; 515 } 516 } 517} 518 519void RegisterInfoEmitter::EmitRegMapping( 520 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 521 // Emit the initializer so the tables from EmitRegMappingTables get wired up 522 // to the MCRegisterInfo object. 523 unsigned maxLength = 0; 524 for (auto &RE : Regs) { 525 Record *Reg = RE.TheDef; 526 maxLength = std::max((size_t)maxLength, 527 Reg->getValueAsListOfInts("DwarfNumbers").size()); 528 } 529 530 if (!maxLength) 531 return; 532 533 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 534 535 // Emit reverse information about the dwarf register numbers. 536 for (unsigned j = 0; j < 2; ++j) { 537 OS << " switch ("; 538 if (j == 0) 539 OS << "DwarfFlavour"; 540 else 541 OS << "EHFlavour"; 542 OS << ") {\n" 543 << " default:\n" 544 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 545 546 for (unsigned i = 0, e = maxLength; i != e; ++i) { 547 OS << " case " << i << ":\n"; 548 OS << " "; 549 if (!isCtor) 550 OS << "RI->"; 551 std::string Tmp; 552 raw_string_ostream(Tmp) << Namespace 553 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 554 << "Dwarf2L"; 555 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; 556 if (j == 0) 557 OS << "false"; 558 else 559 OS << "true"; 560 OS << ");\n"; 561 OS << " break;\n"; 562 } 563 OS << " }\n"; 564 } 565 566 // Emit information about the dwarf register numbers. 567 for (unsigned j = 0; j < 2; ++j) { 568 OS << " switch ("; 569 if (j == 0) 570 OS << "DwarfFlavour"; 571 else 572 OS << "EHFlavour"; 573 OS << ") {\n" 574 << " default:\n" 575 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 576 577 for (unsigned i = 0, e = maxLength; i != e; ++i) { 578 OS << " case " << i << ":\n"; 579 OS << " "; 580 if (!isCtor) 581 OS << "RI->"; 582 std::string Tmp; 583 raw_string_ostream(Tmp) << Namespace 584 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 585 << "L2Dwarf"; 586 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; 587 if (j == 0) 588 OS << "false"; 589 else 590 OS << "true"; 591 OS << ");\n"; 592 OS << " break;\n"; 593 } 594 OS << " }\n"; 595 } 596} 597 598// Print a BitVector as a sequence of hex numbers using a little-endian mapping. 599// Width is the number of bits per hex number. 600static void printBitVectorAsHex(raw_ostream &OS, 601 const BitVector &Bits, 602 unsigned Width) { 603 assert(Width <= 32 && "Width too large"); 604 unsigned Digits = (Width + 3) / 4; 605 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 606 unsigned Value = 0; 607 for (unsigned j = 0; j != Width && i + j != e; ++j) 608 Value |= Bits.test(i + j) << j; 609 OS << format("0x%0*x, ", Digits, Value); 610 } 611} 612 613// Helper to emit a set of bits into a constant byte array. 614class BitVectorEmitter { 615 BitVector Values; 616public: 617 void add(unsigned v) { 618 if (v >= Values.size()) 619 Values.resize(((v/8)+1)*8); // Round up to the next byte. 620 Values[v] = true; 621 } 622 623 void print(raw_ostream &OS) { 624 printBitVectorAsHex(OS, Values, 8); 625 } 626}; 627 628static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 629 OS << getEnumName(VT); 630} 631 632static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { 633 OS << Idx->EnumValue; 634} 635 636// Differentially encoded register and regunit lists allow for better 637// compression on regular register banks. The sequence is computed from the 638// differential list as: 639// 640// out[0] = InitVal; 641// out[n+1] = out[n] + diff[n]; // n = 0, 1, ... 642// 643// The initial value depends on the specific list. The list is terminated by a 644// 0 differential which means we can't encode repeated elements. 645 646typedef SmallVector<uint16_t, 4> DiffVec; 647typedef SmallVector<LaneBitmask, 4> MaskVec; 648 649// Differentially encode a sequence of numbers into V. The starting value and 650// terminating 0 are not added to V, so it will have the same size as List. 651static 652DiffVec &diffEncode(DiffVec &V, unsigned InitVal, SparseBitVector<> List) { 653 assert(V.empty() && "Clear DiffVec before diffEncode."); 654 uint16_t Val = uint16_t(InitVal); 655 656 for (uint16_t Cur : List) { 657 V.push_back(Cur - Val); 658 Val = Cur; 659 } 660 return V; 661} 662 663template<typename Iter> 664static 665DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) { 666 assert(V.empty() && "Clear DiffVec before diffEncode."); 667 uint16_t Val = uint16_t(InitVal); 668 for (Iter I = Begin; I != End; ++I) { 669 uint16_t Cur = (*I)->EnumValue; 670 V.push_back(Cur - Val); 671 Val = Cur; 672 } 673 return V; 674} 675 676static void printDiff16(raw_ostream &OS, uint16_t Val) { 677 OS << Val; 678} 679 680static void printMask(raw_ostream &OS, LaneBitmask Val) { 681 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')'; 682} 683 684// Try to combine Idx's compose map into Vec if it is compatible. 685// Return false if it's not possible. 686static bool combine(const CodeGenSubRegIndex *Idx, 687 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) { 688 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); 689 for (const auto &I : Map) { 690 CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1]; 691 if (Entry && Entry != I.second) 692 return false; 693 } 694 695 // All entries are compatible. Make it so. 696 for (const auto &I : Map) { 697 auto *&Entry = Vec[I.first->EnumValue - 1]; 698 assert((!Entry || Entry == I.second) && 699 "Expected EnumValue to be unique"); 700 Entry = I.second; 701 } 702 return true; 703} 704 705void 706RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, 707 CodeGenRegBank &RegBank, 708 const std::string &ClName) { 709 const auto &SubRegIndices = RegBank.getSubRegIndices(); 710 OS << "unsigned " << ClName 711 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n"; 712 713 // Many sub-register indexes are composition-compatible, meaning that 714 // 715 // compose(IdxA, IdxB) == compose(IdxA', IdxB) 716 // 717 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. 718 // The illegal entries can be use as wildcards to compress the table further. 719 720 // Map each Sub-register index to a compatible table row. 721 SmallVector<unsigned, 4> RowMap; 722 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows; 723 724 auto SubRegIndicesSize = 725 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 726 for (const auto &Idx : SubRegIndices) { 727 unsigned Found = ~0u; 728 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 729 if (combine(&Idx, Rows[r])) { 730 Found = r; 731 break; 732 } 733 } 734 if (Found == ~0u) { 735 Found = Rows.size(); 736 Rows.resize(Found + 1); 737 Rows.back().resize(SubRegIndicesSize); 738 combine(&Idx, Rows.back()); 739 } 740 RowMap.push_back(Found); 741 } 742 743 // Output the row map if there is multiple rows. 744 if (Rows.size() > 1) { 745 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32) 746 << " RowMap[" << SubRegIndicesSize << "] = {\n "; 747 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 748 OS << RowMap[i] << ", "; 749 OS << "\n };\n"; 750 } 751 752 // Output the rows. 753 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) 754 << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n"; 755 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 756 OS << " { "; 757 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 758 if (Rows[r][i]) 759 OS << Rows[r][i]->getQualifiedName() << ", "; 760 else 761 OS << "0, "; 762 OS << "},\n"; 763 } 764 OS << " };\n\n"; 765 766 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n" 767 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n"; 768 if (Rows.size() > 1) 769 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; 770 else 771 OS << " return Rows[0][IdxB];\n"; 772 OS << "}\n\n"; 773} 774 775void 776RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, 777 CodeGenRegBank &RegBank, 778 const std::string &ClName) { 779 // See the comments in computeSubRegLaneMasks() for our goal here. 780 const auto &SubRegIndices = RegBank.getSubRegIndices(); 781 782 // Create a list of Mask+Rotate operations, with equivalent entries merged. 783 SmallVector<unsigned, 4> SubReg2SequenceIndexMap; 784 SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences; 785 for (const auto &Idx : SubRegIndices) { 786 const SmallVector<MaskRolPair, 1> &IdxSequence 787 = Idx.CompositionLaneMaskTransform; 788 789 unsigned Found = ~0u; 790 unsigned SIdx = 0; 791 unsigned NextSIdx; 792 for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) { 793 SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 794 NextSIdx = SIdx + Sequence.size() + 1; 795 if (Sequence == IdxSequence) { 796 Found = SIdx; 797 break; 798 } 799 } 800 if (Found == ~0u) { 801 Sequences.push_back(IdxSequence); 802 Found = SIdx; 803 } 804 SubReg2SequenceIndexMap.push_back(Found); 805 } 806 807 OS << " struct MaskRolOp {\n" 808 " LaneBitmask Mask;\n" 809 " uint8_t RotateLeft;\n" 810 " };\n" 811 " static const MaskRolOp LaneMaskComposeSequences[] = {\n"; 812 unsigned Idx = 0; 813 for (size_t s = 0, se = Sequences.size(); s != se; ++s) { 814 OS << " "; 815 const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 816 for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) { 817 const MaskRolPair &P = Sequence[p]; 818 printMask(OS << "{ ", P.Mask); 819 OS << format(", %2u }, ", P.RotateLeft); 820 } 821 OS << "{ LaneBitmask::getNone(), 0 }"; 822 if (s+1 != se) 823 OS << ", "; 824 OS << " // Sequence " << Idx << "\n"; 825 Idx += Sequence.size() + 1; 826 } 827 OS << " };\n" 828 " static const MaskRolOp *const CompositeSequences[] = {\n"; 829 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { 830 OS << " "; 831 unsigned Idx = SubReg2SequenceIndexMap[i]; 832 OS << format("&LaneMaskComposeSequences[%u]", Idx); 833 if (i+1 != e) 834 OS << ","; 835 OS << " // to " << SubRegIndices[i].getName() << "\n"; 836 } 837 OS << " };\n\n"; 838 839 OS << "LaneBitmask " << ClName 840 << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)" 841 " const {\n" 842 " --IdxA; assert(IdxA < " << SubRegIndices.size() 843 << " && \"Subregister index out of bounds\");\n" 844 " LaneBitmask Result;\n" 845 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n" 846 " LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();\n" 847 " if (unsigned S = Ops->RotateLeft)\n" 848 " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));\n" 849 " else\n" 850 " Result |= LaneBitmask(M);\n" 851 " }\n" 852 " return Result;\n" 853 "}\n\n"; 854 855 OS << "LaneBitmask " << ClName 856 << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, " 857 " LaneBitmask LaneMask) const {\n" 858 " LaneMask &= getSubRegIndexLaneMask(IdxA);\n" 859 " --IdxA; assert(IdxA < " << SubRegIndices.size() 860 << " && \"Subregister index out of bounds\");\n" 861 " LaneBitmask Result;\n" 862 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n" 863 " LaneBitmask::Type M = LaneMask.getAsInteger();\n" 864 " if (unsigned S = Ops->RotateLeft)\n" 865 " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));\n" 866 " else\n" 867 " Result |= LaneBitmask(M);\n" 868 " }\n" 869 " return Result;\n" 870 "}\n\n"; 871} 872 873// 874// runMCDesc - Print out MC register descriptions. 875// 876void 877RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 878 CodeGenRegBank &RegBank) { 879 emitSourceFileHeader("MC Register Information", OS); 880 881 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 882 OS << "#undef GET_REGINFO_MC_DESC\n\n"; 883 884 const auto &Regs = RegBank.getRegisters(); 885 886 auto &SubRegIndices = RegBank.getSubRegIndices(); 887 // The lists of sub-registers and super-registers go in the same array. That 888 // allows us to share suffixes. 889 typedef std::vector<const CodeGenRegister*> RegVec; 890 891 // Differentially encoded lists. 892 SequenceToOffsetTable<DiffVec> DiffSeqs; 893 SmallVector<DiffVec, 4> SubRegLists(Regs.size()); 894 SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); 895 SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); 896 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size()); 897 898 // List of lane masks accompanying register unit sequences. 899 SequenceToOffsetTable<MaskVec> LaneMaskSeqs; 900 SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size()); 901 902 // Keep track of sub-register names as well. These are not differentially 903 // encoded. 904 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec; 905 SequenceToOffsetTable<SubRegIdxVec, deref<std::less<>>> SubRegIdxSeqs; 906 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); 907 908 SequenceToOffsetTable<std::string> RegStrings; 909 910 // Precompute register lists for the SequenceToOffsetTable. 911 unsigned i = 0; 912 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) { 913 const auto &Reg = *I; 914 RegStrings.add(std::string(Reg.getName())); 915 916 // Compute the ordered sub-register list. 917 SetVector<const CodeGenRegister*> SR; 918 Reg.addSubRegsPreOrder(SR, RegBank); 919 diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end()); 920 DiffSeqs.add(SubRegLists[i]); 921 922 // Compute the corresponding sub-register indexes. 923 SubRegIdxVec &SRIs = SubRegIdxLists[i]; 924 for (const CodeGenRegister *S : SR) 925 SRIs.push_back(Reg.getSubRegIndex(S)); 926 SubRegIdxSeqs.add(SRIs); 927 928 // Super-registers are already computed. 929 const RegVec &SuperRegList = Reg.getSuperRegs(); 930 diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(), 931 SuperRegList.end()); 932 DiffSeqs.add(SuperRegLists[i]); 933 934 // Differentially encode the register unit list, seeded by register number. 935 // First compute a scale factor that allows more diff-lists to be reused: 936 // 937 // D0 -> (S0, S1) 938 // D1 -> (S2, S3) 939 // 940 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial 941 // value for the differential decoder is the register number multiplied by 942 // the scale. 943 // 944 // Check the neighboring registers for arithmetic progressions. 945 unsigned ScaleA = ~0u, ScaleB = ~0u; 946 SparseBitVector<> RUs = Reg.getNativeRegUnits(); 947 if (I != Regs.begin() && 948 std::prev(I)->getNativeRegUnits().count() == RUs.count()) 949 ScaleB = *RUs.begin() - *std::prev(I)->getNativeRegUnits().begin(); 950 if (std::next(I) != Regs.end() && 951 std::next(I)->getNativeRegUnits().count() == RUs.count()) 952 ScaleA = *std::next(I)->getNativeRegUnits().begin() - *RUs.begin(); 953 unsigned Scale = std::min(ScaleB, ScaleA); 954 // Default the scale to 0 if it can't be encoded in 4 bits. 955 if (Scale >= 16) 956 Scale = 0; 957 RegUnitInitScale[i] = Scale; 958 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); 959 960 const auto &RUMasks = Reg.getRegUnitLaneMasks(); 961 MaskVec &LaneMaskVec = RegUnitLaneMasks[i]; 962 assert(LaneMaskVec.empty()); 963 LaneMaskVec.insert(LaneMaskVec.begin(), RUMasks.begin(), RUMasks.end()); 964 // Terminator mask should not be used inside of the list. 965#ifndef NDEBUG 966 for (LaneBitmask M : LaneMaskVec) { 967 assert(!M.all() && "terminator mask should not be part of the list"); 968 } 969#endif 970 LaneMaskSeqs.add(LaneMaskVec); 971 } 972 973 // Compute the final layout of the sequence table. 974 DiffSeqs.layout(); 975 LaneMaskSeqs.layout(); 976 SubRegIdxSeqs.layout(); 977 978 OS << "namespace llvm {\n\n"; 979 980 const std::string &TargetName = std::string(Target.getName()); 981 982 // Emit the shared table of differential lists. 983 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; 984 DiffSeqs.emit(OS, printDiff16); 985 OS << "};\n\n"; 986 987 // Emit the shared table of regunit lane mask sequences. 988 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; 989 LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); 990 OS << "};\n\n"; 991 992 // Emit the table of sub-register indexes. 993 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 994 SubRegIdxSeqs.emit(OS, printSubRegIndex); 995 OS << "};\n\n"; 996 997 // Emit the table of sub-register index sizes. 998 OS << "extern const MCRegisterInfo::SubRegCoveredBits " 999 << TargetName << "SubRegIdxRanges[] = {\n"; 1000 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; 1001 for (const auto &Idx : SubRegIndices) { 1002 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// " 1003 << Idx.getName() << "\n"; 1004 } 1005 OS << "};\n\n"; 1006 1007 // Emit the string table. 1008 RegStrings.layout(); 1009 RegStrings.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName + 1010 "RegStrings[]"); 1011 1012 OS << "extern const MCRegisterDesc " << TargetName 1013 << "RegDesc[] = { // Descriptors\n"; 1014 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; 1015 1016 // Emit the register descriptors now. 1017 i = 0; 1018 for (const auto &Reg : Regs) { 1019 OS << " { " << RegStrings.get(std::string(Reg.getName())) << ", " 1020 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) 1021 << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 1022 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " 1023 << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << " },\n"; 1024 ++i; 1025 } 1026 OS << "};\n\n"; // End of register descriptors... 1027 1028 // Emit the table of register unit roots. Each regunit has one or two root 1029 // registers. 1030 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; 1031 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { 1032 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots(); 1033 assert(!Roots.empty() && "All regunits must have a root register."); 1034 assert(Roots.size() <= 2 && "More than two roots not supported yet."); 1035 OS << " { " << getQualifiedName(Roots.front()->TheDef); 1036 for (unsigned r = 1; r != Roots.size(); ++r) 1037 OS << ", " << getQualifiedName(Roots[r]->TheDef); 1038 OS << " },\n"; 1039 } 1040 OS << "};\n\n"; 1041 1042 const auto &RegisterClasses = RegBank.getRegClasses(); 1043 1044 // Loop over all of the register classes... emitting each one. 1045 OS << "namespace { // Register classes...\n"; 1046 1047 SequenceToOffsetTable<std::string> RegClassStrings; 1048 1049 // Emit the register enum value arrays for each RegisterClass 1050 for (const auto &RC : RegisterClasses) { 1051 ArrayRef<Record*> Order = RC.getOrder(); 1052 1053 // Give the register class a legal C name if it's anonymous. 1054 const std::string &Name = RC.getName(); 1055 1056 RegClassStrings.add(Name); 1057 1058 // Emit the register list now. 1059 OS << " // " << Name << " Register Class...\n" 1060 << " const MCPhysReg " << Name 1061 << "[] = {\n "; 1062 for (Record *Reg : Order) { 1063 OS << getQualifiedName(Reg) << ", "; 1064 } 1065 OS << "\n };\n\n"; 1066 1067 OS << " // " << Name << " Bit set.\n" 1068 << " const uint8_t " << Name 1069 << "Bits[] = {\n "; 1070 BitVectorEmitter BVE; 1071 for (Record *Reg : Order) { 1072 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); 1073 } 1074 BVE.print(OS); 1075 OS << "\n };\n\n"; 1076 1077 } 1078 OS << "} // end anonymous namespace\n\n"; 1079 1080 RegClassStrings.layout(); 1081 RegClassStrings.emitStringLiteralDef( 1082 OS, Twine("extern const char ") + TargetName + "RegClassStrings[]"); 1083 1084 OS << "extern const MCRegisterClass " << TargetName 1085 << "MCRegisterClasses[] = {\n"; 1086 1087 for (const auto &RC : RegisterClasses) { 1088 assert(isInt<8>(RC.CopyCost) && "Copy cost too large."); 1089 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " 1090 << RegClassStrings.get(RC.getName()) << ", " 1091 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " 1092 << RC.getQualifiedName() + "RegClassID" << ", " 1093 << RC.CopyCost << ", " 1094 << ( RC.Allocatable ? "true" : "false" ) << " },\n"; 1095 } 1096 1097 OS << "};\n\n"; 1098 1099 EmitRegMappingTables(OS, Regs, false); 1100 1101 // Emit Reg encoding table 1102 OS << "extern const uint16_t " << TargetName; 1103 OS << "RegEncodingTable[] = {\n"; 1104 // Add entry for NoRegister 1105 OS << " 0,\n"; 1106 for (const auto &RE : Regs) { 1107 Record *Reg = RE.TheDef; 1108 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); 1109 uint64_t Value = 0; 1110 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { 1111 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b))) 1112 Value |= (uint64_t)B->getValue() << b; 1113 } 1114 OS << " " << Value << ",\n"; 1115 } 1116 OS << "};\n"; // End of HW encoding table 1117 1118 // MCRegisterInfo initialization routine. 1119 OS << "static inline void Init" << TargetName 1120 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 1121 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) " 1122 "{\n" 1123 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 1124 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, " 1125 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, " 1126 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, " 1127 << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, " 1128 << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, " 1129 << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n" 1130 << TargetName << "SubRegIdxRanges, " << TargetName 1131 << "RegEncodingTable);\n\n"; 1132 1133 EmitRegMapping(OS, Regs, false); 1134 1135 OS << "}\n\n"; 1136 1137 OS << "} // end namespace llvm\n\n"; 1138 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 1139} 1140 1141void 1142RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 1143 CodeGenRegBank &RegBank) { 1144 emitSourceFileHeader("Register Information Header Fragment", OS); 1145 1146 OS << "\n#ifdef GET_REGINFO_HEADER\n"; 1147 OS << "#undef GET_REGINFO_HEADER\n\n"; 1148 1149 const std::string &TargetName = std::string(Target.getName()); 1150 std::string ClassName = TargetName + "GenRegisterInfo"; 1151 1152 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; 1153 1154 OS << "namespace llvm {\n\n"; 1155 1156 OS << "class " << TargetName << "FrameLowering;\n\n"; 1157 1158 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 1159 << " explicit " << ClassName 1160 << "(unsigned RA, unsigned D = 0, unsigned E = 0,\n" 1161 << " unsigned PC = 0, unsigned HwMode = 0);\n"; 1162 if (!RegBank.getSubRegIndices().empty()) { 1163 OS << " unsigned composeSubRegIndicesImpl" 1164 << "(unsigned, unsigned) const override;\n" 1165 << " LaneBitmask composeSubRegIndexLaneMaskImpl" 1166 << "(unsigned, LaneBitmask) const override;\n" 1167 << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl" 1168 << "(unsigned, LaneBitmask) const override;\n" 1169 << " const TargetRegisterClass *getSubClassWithSubReg" 1170 << "(const TargetRegisterClass*, unsigned) const override;\n"; 1171 } 1172 OS << " const RegClassWeight &getRegClassWeight(" 1173 << "const TargetRegisterClass *RC) const override;\n" 1174 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n" 1175 << " unsigned getNumRegPressureSets() const override;\n" 1176 << " const char *getRegPressureSetName(unsigned Idx) const override;\n" 1177 << " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned " 1178 "Idx) const override;\n" 1179 << " const int *getRegClassPressureSets(" 1180 << "const TargetRegisterClass *RC) const override;\n" 1181 << " const int *getRegUnitPressureSets(" 1182 << "unsigned RegUnit) const override;\n" 1183 << " ArrayRef<const char *> getRegMaskNames() const override;\n" 1184 << " ArrayRef<const uint32_t *> getRegMasks() const override;\n" 1185 << " /// Devirtualized TargetFrameLowering.\n" 1186 << " static const " << TargetName << "FrameLowering *getFrameLowering(\n" 1187 << " const MachineFunction &MF);\n" 1188 << "};\n\n"; 1189 1190 const auto &RegisterClasses = RegBank.getRegClasses(); 1191 1192 if (!RegisterClasses.empty()) { 1193 OS << "namespace " << RegisterClasses.front().Namespace 1194 << " { // Register classes\n"; 1195 1196 for (const auto &RC : RegisterClasses) { 1197 const std::string &Name = RC.getName(); 1198 1199 // Output the extern for the instance. 1200 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; 1201 } 1202 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; 1203 } 1204 OS << "} // end namespace llvm\n\n"; 1205 OS << "#endif // GET_REGINFO_HEADER\n\n"; 1206} 1207 1208// 1209// runTargetDesc - Output the target register and register file descriptions. 1210// 1211void 1212RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 1213 CodeGenRegBank &RegBank){ 1214 emitSourceFileHeader("Target Register and Register Classes Information", OS); 1215 1216 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 1217 OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; 1218 1219 OS << "namespace llvm {\n\n"; 1220 1221 // Get access to MCRegisterClass data. 1222 OS << "extern const MCRegisterClass " << Target.getName() 1223 << "MCRegisterClasses[];\n"; 1224 1225 // Start out by emitting each of the register classes. 1226 const auto &RegisterClasses = RegBank.getRegClasses(); 1227 const auto &SubRegIndices = RegBank.getSubRegIndices(); 1228 1229 // Collect all registers belonging to any allocatable class. 1230 std::set<Record*> AllocatableRegs; 1231 1232 // Collect allocatable registers. 1233 for (const auto &RC : RegisterClasses) { 1234 ArrayRef<Record*> Order = RC.getOrder(); 1235 1236 if (RC.Allocatable) 1237 AllocatableRegs.insert(Order.begin(), Order.end()); 1238 } 1239 1240 const CodeGenHwModes &CGH = Target.getHwModes(); 1241 unsigned NumModes = CGH.getNumModeIds(); 1242 1243 // Build a shared array of value types. 1244 SequenceToOffsetTable<std::vector<MVT::SimpleValueType>> VTSeqs; 1245 for (unsigned M = 0; M < NumModes; ++M) { 1246 for (const auto &RC : RegisterClasses) { 1247 std::vector<MVT::SimpleValueType> S; 1248 for (const ValueTypeByHwMode &VVT : RC.VTs) 1249 S.push_back(VVT.get(M).SimpleTy); 1250 VTSeqs.add(S); 1251 } 1252 } 1253 VTSeqs.layout(); 1254 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1255 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); 1256 OS << "};\n"; 1257 1258 // Emit SubRegIndex names, skipping 0. 1259 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; 1260 1261 for (const auto &Idx : SubRegIndices) { 1262 OS << Idx.getName(); 1263 OS << "\", \""; 1264 } 1265 OS << "\" };\n\n"; 1266 1267 // Emit SubRegIndex lane masks, including 0. 1268 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " 1269 "LaneBitmask::getAll(),\n"; 1270 for (const auto &Idx : SubRegIndices) { 1271 printMask(OS << " ", Idx.LaneMask); 1272 OS << ", // " << Idx.getName() << '\n'; 1273 } 1274 OS << " };\n\n"; 1275 1276 OS << "\n"; 1277 1278 // Now that all of the structs have been emitted, emit the instances. 1279 if (!RegisterClasses.empty()) { 1280 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" 1281 << " = {\n"; 1282 for (unsigned M = 0; M < NumModes; ++M) { 1283 unsigned EV = 0; 1284 OS << " // Mode = " << M << " ("; 1285 if (M == 0) 1286 OS << "Default"; 1287 else 1288 OS << CGH.getMode(M).Name; 1289 OS << ")\n"; 1290 for (const auto &RC : RegisterClasses) { 1291 assert(RC.EnumValue == EV++ && "Unexpected order of register classes"); 1292 (void)EV; 1293 const RegSizeInfo &RI = RC.RSI.get(M); 1294 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " 1295 << RI.SpillAlignment; 1296 std::vector<MVT::SimpleValueType> VTs; 1297 for (const ValueTypeByHwMode &VVT : RC.VTs) 1298 VTs.push_back(VVT.get(M).SimpleTy); 1299 OS << ", VTLists+" << VTSeqs.get(VTs) << " }, // " 1300 << RC.getName() << '\n'; 1301 } 1302 } 1303 OS << "};\n"; 1304 1305 1306 OS << "\nstatic const TargetRegisterClass *const " 1307 << "NullRegClasses[] = { nullptr };\n\n"; 1308 1309 // Emit register class bit mask tables. The first bit mask emitted for a 1310 // register class, RC, is the set of sub-classes, including RC itself. 1311 // 1312 // If RC has super-registers, also create a list of subreg indices and bit 1313 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, 1314 // SuperRC, that satisfies: 1315 // 1316 // For all SuperReg in SuperRC: SuperReg:Idx in RC 1317 // 1318 // The 0-terminated list of subreg indices starts at: 1319 // 1320 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... 1321 // 1322 // The corresponding bitmasks follow the sub-class mask in memory. Each 1323 // mask has RCMaskWords uint32_t entries. 1324 // 1325 // Every bit mask present in the list has at least one bit set. 1326 1327 // Compress the sub-reg index lists. 1328 typedef std::vector<const CodeGenSubRegIndex*> IdxList; 1329 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); 1330 SequenceToOffsetTable<IdxList, deref<std::less<>>> SuperRegIdxSeqs; 1331 BitVector MaskBV(RegisterClasses.size()); 1332 1333 for (const auto &RC : RegisterClasses) { 1334 OS << "static const uint32_t " << RC.getName() 1335 << "SubClassMask[] = {\n "; 1336 printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1337 1338 // Emit super-reg class masks for any relevant SubRegIndices that can 1339 // project into RC. 1340 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue]; 1341 for (auto &Idx : SubRegIndices) { 1342 MaskBV.reset(); 1343 RC.getSuperRegClasses(&Idx, MaskBV); 1344 if (MaskBV.none()) 1345 continue; 1346 SRIList.push_back(&Idx); 1347 OS << "\n "; 1348 printBitVectorAsHex(OS, MaskBV, 32); 1349 OS << "// " << Idx.getName(); 1350 } 1351 SuperRegIdxSeqs.add(SRIList); 1352 OS << "\n};\n\n"; 1353 } 1354 1355 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1356 SuperRegIdxSeqs.layout(); 1357 SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1358 OS << "};\n\n"; 1359 1360 // Emit NULL terminated super-class lists. 1361 for (const auto &RC : RegisterClasses) { 1362 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); 1363 1364 // Skip classes without supers. We can reuse NullRegClasses. 1365 if (Supers.empty()) 1366 continue; 1367 1368 OS << "static const TargetRegisterClass *const " 1369 << RC.getName() << "Superclasses[] = {\n"; 1370 for (const auto *Super : Supers) 1371 OS << " &" << Super->getQualifiedName() << "RegClass,\n"; 1372 OS << " nullptr\n};\n\n"; 1373 } 1374 1375 // Emit methods. 1376 for (const auto &RC : RegisterClasses) { 1377 if (!RC.AltOrderSelect.empty()) { 1378 OS << "\nstatic inline unsigned " << RC.getName() 1379 << "AltOrderSelect(const MachineFunction &MF) {" 1380 << RC.AltOrderSelect << "}\n\n" 1381 << "static ArrayRef<MCPhysReg> " << RC.getName() 1382 << "GetRawAllocationOrder(const MachineFunction &MF) {\n"; 1383 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 1384 ArrayRef<Record*> Elems = RC.getOrder(oi); 1385 if (!Elems.empty()) { 1386 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; 1387 for (unsigned elem = 0; elem != Elems.size(); ++elem) 1388 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1389 OS << " };\n"; 1390 } 1391 } 1392 OS << " const MCRegisterClass &MCR = " << Target.getName() 1393 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" 1394 << " const ArrayRef<MCPhysReg> Order[] = {\n" 1395 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; 1396 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 1397 if (RC.getOrder(oi).empty()) 1398 OS << "),\n ArrayRef<MCPhysReg>("; 1399 else 1400 OS << "),\n makeArrayRef(AltOrder" << oi; 1401 OS << ")\n };\n const unsigned Select = " << RC.getName() 1402 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 1403 << ");\n return Order[Select];\n}\n"; 1404 } 1405 } 1406 1407 // Now emit the actual value-initialized register class instances. 1408 OS << "\nnamespace " << RegisterClasses.front().Namespace 1409 << " { // Register class instances\n"; 1410 1411 for (const auto &RC : RegisterClasses) { 1412 OS << " extern const TargetRegisterClass " << RC.getName() 1413 << "RegClass = {\n " << '&' << Target.getName() 1414 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " 1415 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " 1416 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "; 1417 printMask(OS, RC.LaneMask); 1418 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " 1419 << (RC.HasDisjunctSubRegs?"true":"false") 1420 << ", /* HasDisjunctSubRegs */\n " 1421 << (RC.CoveredBySubRegs?"true":"false") 1422 << ", /* CoveredBySubRegs */\n "; 1423 if (RC.getSuperClasses().empty()) 1424 OS << "NullRegClasses,\n "; 1425 else 1426 OS << RC.getName() << "Superclasses,\n "; 1427 if (RC.AltOrderSelect.empty()) 1428 OS << "nullptr\n"; 1429 else 1430 OS << RC.getName() << "GetRawAllocationOrder\n"; 1431 OS << " };\n\n"; 1432 } 1433 1434 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; 1435 } 1436 1437 OS << "\nnamespace {\n"; 1438 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 1439 for (const auto &RC : RegisterClasses) 1440 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; 1441 OS << " };\n"; 1442 OS << "} // end anonymous namespace\n"; 1443 1444 // Emit extra information about registers. 1445 const std::string &TargetName = std::string(Target.getName()); 1446 OS << "\nstatic const TargetRegisterInfoDesc " 1447 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n"; 1448 OS << " { 0, false },\n"; 1449 1450 const auto &Regs = RegBank.getRegisters(); 1451 for (const auto &Reg : Regs) { 1452 OS << " { "; 1453 OS << Reg.CostPerUse << ", " 1454 << ( AllocatableRegs.count(Reg.TheDef) != 0 ? "true" : "false" ) 1455 << " },\n"; 1456 } 1457 OS << "};\n"; // End of register descriptors... 1458 1459 1460 std::string ClassName = Target.getName().str() + "GenRegisterInfo"; 1461 1462 auto SubRegIndicesSize = 1463 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 1464 1465 if (!SubRegIndices.empty()) { 1466 emitComposeSubRegIndices(OS, RegBank, ClassName); 1467 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); 1468 } 1469 1470 // Emit getSubClassWithSubReg. 1471 if (!SubRegIndices.empty()) { 1472 OS << "const TargetRegisterClass *" << ClassName 1473 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 1474 << " const {\n"; 1475 // Use the smallest type that can hold a regclass ID with room for a 1476 // sentinel. 1477 if (RegisterClasses.size() < UINT8_MAX) 1478 OS << " static const uint8_t Table["; 1479 else if (RegisterClasses.size() < UINT16_MAX) 1480 OS << " static const uint16_t Table["; 1481 else 1482 PrintFatalError("Too many register classes."); 1483 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; 1484 for (const auto &RC : RegisterClasses) { 1485 OS << " {\t// " << RC.getName() << "\n"; 1486 for (auto &Idx : SubRegIndices) { 1487 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) 1488 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() 1489 << " -> " << SRC->getName() << "\n"; 1490 else 1491 OS << " 0,\t// " << Idx.getName() << "\n"; 1492 } 1493 OS << " },\n"; 1494 } 1495 OS << " };\n assert(RC && \"Missing regclass\");\n" 1496 << " if (!Idx) return RC;\n --Idx;\n" 1497 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n" 1498 << " unsigned TV = Table[RC->getID()][Idx];\n" 1499 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; 1500 } 1501 1502 EmitRegUnitPressure(OS, RegBank, ClassName); 1503 1504 // Emit the constructor of the class... 1505 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1506 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; 1507 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; 1508 OS << "extern const char " << TargetName << "RegStrings[];\n"; 1509 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; 1510 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; 1511 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1512 OS << "extern const MCRegisterInfo::SubRegCoveredBits " 1513 << TargetName << "SubRegIdxRanges[];\n"; 1514 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1515 1516 EmitRegMappingTables(OS, Regs, true); 1517 1518 OS << ClassName << "::\n" << ClassName 1519 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,\n" 1520 " unsigned PC, unsigned HwMode)\n" 1521 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" 1522 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() << ",\n" 1523 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable,\n" 1524 << " "; 1525 printMask(OS, RegBank.CoveringLanes); 1526 OS << ", RegClassInfos, HwMode) {\n" 1527 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1 1528 << ", RA, PC,\n " << TargetName 1529 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" 1530 << " " << TargetName << "RegUnitRoots,\n" 1531 << " " << RegBank.getNumNativeRegUnits() << ",\n" 1532 << " " << TargetName << "RegDiffLists,\n" 1533 << " " << TargetName << "LaneMaskLists,\n" 1534 << " " << TargetName << "RegStrings,\n" 1535 << " " << TargetName << "RegClassStrings,\n" 1536 << " " << TargetName << "SubRegIdxLists,\n" 1537 << " " << SubRegIndicesSize + 1 << ",\n" 1538 << " " << TargetName << "SubRegIdxRanges,\n" 1539 << " " << TargetName << "RegEncodingTable);\n\n"; 1540 1541 EmitRegMapping(OS, Regs, true); 1542 1543 OS << "}\n\n"; 1544 1545 // Emit CalleeSavedRegs information. 1546 std::vector<Record*> CSRSets = 1547 Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1548 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) { 1549 Record *CSRSet = CSRSets[i]; 1550 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); 1551 assert(Regs && "Cannot expand CalleeSavedRegs instance"); 1552 1553 // Emit the *_SaveList list of callee-saved registers. 1554 OS << "static const MCPhysReg " << CSRSet->getName() 1555 << "_SaveList[] = { "; 1556 for (unsigned r = 0, re = Regs->size(); r != re; ++r) 1557 OS << getQualifiedName((*Regs)[r]) << ", "; 1558 OS << "0 };\n"; 1559 1560 // Emit the *_RegMask bit mask of call-preserved registers. 1561 BitVector Covered = RegBank.computeCoveredRegisters(*Regs); 1562 1563 // Check for an optional OtherPreserved set. 1564 // Add those registers to RegMask, but not to SaveList. 1565 if (DagInit *OPDag = 1566 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) { 1567 SetTheory::RecSet OPSet; 1568 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc()); 1569 Covered |= RegBank.computeCoveredRegisters( 1570 ArrayRef<Record*>(OPSet.begin(), OPSet.end())); 1571 } 1572 1573 OS << "static const uint32_t " << CSRSet->getName() 1574 << "_RegMask[] = { "; 1575 printBitVectorAsHex(OS, Covered, 32); 1576 OS << "};\n"; 1577 } 1578 OS << "\n\n"; 1579 1580 OS << "ArrayRef<const uint32_t *> " << ClassName 1581 << "::getRegMasks() const {\n"; 1582 if (!CSRSets.empty()) { 1583 OS << " static const uint32_t *const Masks[] = {\n"; 1584 for (Record *CSRSet : CSRSets) 1585 OS << " " << CSRSet->getName() << "_RegMask,\n"; 1586 OS << " };\n"; 1587 OS << " return makeArrayRef(Masks);\n"; 1588 } else { 1589 OS << " return None;\n"; 1590 } 1591 OS << "}\n\n"; 1592 1593 OS << "ArrayRef<const char *> " << ClassName 1594 << "::getRegMaskNames() const {\n"; 1595 if (!CSRSets.empty()) { 1596 OS << " static const char *const Names[] = {\n"; 1597 for (Record *CSRSet : CSRSets) 1598 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; 1599 OS << " };\n"; 1600 OS << " return makeArrayRef(Names);\n"; 1601 } else { 1602 OS << " return None;\n"; 1603 } 1604 OS << "}\n\n"; 1605 1606 OS << "const " << TargetName << "FrameLowering *\n" << TargetName 1607 << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n" 1608 << " return static_cast<const " << TargetName << "FrameLowering *>(\n" 1609 << " MF.getSubtarget().getFrameLowering());\n" 1610 << "}\n\n"; 1611 1612 OS << "} // end namespace llvm\n\n"; 1613 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 1614} 1615 1616void RegisterInfoEmitter::run(raw_ostream &OS) { 1617 CodeGenRegBank &RegBank = Target.getRegBank(); 1618 runEnums(OS, Target, RegBank); 1619 runMCDesc(OS, Target, RegBank); 1620 runTargetHeader(OS, Target, RegBank); 1621 runTargetDesc(OS, Target, RegBank); 1622 1623 if (RegisterInfoDebug) 1624 debugDump(errs()); 1625} 1626 1627void RegisterInfoEmitter::debugDump(raw_ostream &OS) { 1628 CodeGenRegBank &RegBank = Target.getRegBank(); 1629 const CodeGenHwModes &CGH = Target.getHwModes(); 1630 unsigned NumModes = CGH.getNumModeIds(); 1631 auto getModeName = [CGH] (unsigned M) -> StringRef { 1632 if (M == 0) 1633 return "Default"; 1634 return CGH.getMode(M).Name; 1635 }; 1636 1637 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { 1638 OS << "RegisterClass " << RC.getName() << ":\n"; 1639 OS << "\tSpillSize: {"; 1640 for (unsigned M = 0; M != NumModes; ++M) 1641 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; 1642 OS << " }\n\tSpillAlignment: {"; 1643 for (unsigned M = 0; M != NumModes; ++M) 1644 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; 1645 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; 1646 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; 1647 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; 1648 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; 1649 OS << "\tRegs:"; 1650 for (const CodeGenRegister *R : RC.getMembers()) { 1651 OS << " " << R->getName(); 1652 } 1653 OS << '\n'; 1654 OS << "\tSubClasses:"; 1655 const BitVector &SubClasses = RC.getSubClasses(); 1656 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { 1657 if (!SubClasses.test(SRC.EnumValue)) 1658 continue; 1659 OS << " " << SRC.getName(); 1660 } 1661 OS << '\n'; 1662 OS << "\tSuperClasses:"; 1663 for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) { 1664 OS << " " << SRC->getName(); 1665 } 1666 OS << '\n'; 1667 } 1668 1669 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { 1670 OS << "SubRegIndex " << SRI.getName() << ":\n"; 1671 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; 1672 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; 1673 } 1674 1675 for (const CodeGenRegister &R : RegBank.getRegisters()) { 1676 OS << "Register " << R.getName() << ":\n"; 1677 OS << "\tCostPerUse: " << R.CostPerUse << '\n'; 1678 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; 1679 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; 1680 for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : R.getSubRegs()) { 1681 OS << "\tSubReg " << P.first->getName() 1682 << " = " << P.second->getName() << '\n'; 1683 } 1684 } 1685} 1686 1687namespace llvm { 1688 1689void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { 1690 RegisterInfoEmitter(RK).run(OS); 1691} 1692 1693} // end namespace llvm 1694