| /freebsd-10.1-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 338 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { argument
599 LowerTlsAddr(MCStreamer &OutStreamer, X86MCInstLower &MCInstLowering, const MachineInstr &MI) argument
764 LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM, const MachineInstr &MI) argument
780 LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM, const MachineInstr &MI) argument
810 EmitInstruction(const MachineInstr *MI) argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/include/llvm/CodeGen/ |
| H A D | MachineBasicBlock.h | 450 void push_back(MachineInstr *MI) { Insts.push_back(MI); } argument
467 iterator insert(iterator I, MachineInstr *MI) { argument
474 insertAfter(iterator I, MachineInstr *MI) argument
[all...] |
| H A D | ScheduleDAG.h | 379 void setInstr(MachineInstr *MI) { argument
|
| /freebsd-10.1-release/contrib/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 168 bool getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI, argument
286 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const { argument
557 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/include/llvm/Target/ |
| H A D | TargetInstrInfo.h | 68 bool isTriviallyReMaterializable(const MachineInstr *MI, argument
83 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, argument
113 virtual bool isCoalescableExtInstr(const MachineInstr &MI, argument
124 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, argument
132 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, argument
153 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const argument
161 isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const argument
179 isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, int &SrcFrameIndex) const argument
454 analyzeSelect(const MachineInstr *MI, SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const argument
475 optimizeSelect(MachineInstr *MI, bool PreferFalse = false) const argument
489 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
501 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
514 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
554 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI, const SmallVectorImpl<unsigned> &Ops, int FrameIndex) const argument
564 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI, const SmallVectorImpl<unsigned> &Ops, MachineInstr* LoadMI) const argument
581 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
697 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument
756 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
779 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const argument
880 verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const argument
913 setExecutionDomain(MachineInstr *MI, unsigned Domain) const argument
956 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const argument
976 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const argument
1000 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/CodeGen/ |
| H A D | BranchFolding.cpp | 253 static unsigned HashMachineInstr(const MachineInstr *MI) { argument
|
| H A D | InlineSpiller.cpp | 212 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) { argument
574 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); local
785 DEBUG(dbgs() << "Redundant spill " << Idx << '\\t' << *MI); local
823 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); local
835 reMaterializeFor(LiveInterval &VirtReg, MachineBasicBlock::iterator MI) argument
847 DEBUG(dbgs() << UseIdx << '\\t' << *MI); local
861 DEBUG(dbgs() << "\\tcannot remat for " << UseIdx << '\\t' << *MI); local
872 DEBUG(dbgs() << "\\tcannot remat tied reg: " << UseIdx << '\\t' << *MI); local
903 DEBUG(dbgs() << "\\t " << UseIdx << '\\t' << *MI << '\\n'); local
940 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); local
981 coalesceStackAccess(MachineInstr *MI, unsigned Reg) argument
1153 insertReload(unsigned NewVReg, SlotIndex Idx, MachineBasicBlock::iterator MI) argument
1170 insertSpill(unsigned NewVReg, bool isKill, MachineBasicBlock::iterator MI) argument
1277 DEBUG(dbgs() << "\\trewrite: " << Idx << '\\t' << *MI << '\\n'); local
[all...] |
| H A D | LiveDebugVariables.cpp | 450 bool LDVImpl::handleDebugValue(MachineInstr *MI, SlotIndex Idx) { argument
577 MachineInstr *MI = &*UI; local
906 MachineInstr *MI; local
[all...] |
| H A D | LiveIntervalAnalysis.cpp | 428 MachineInstr *MI = getInstructionFromIndex(VNI->def); local
546 MachineInstr *MI = getInstructionFromIndex(RI->end); local
736 updateAllRanges(MachineInstr *MI) argument
737 DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI); local
983 const MachineInstr* MI = &*UI; local
1027 handleMove(MachineInstr* MI, bool UpdateFlags) argument
1040 handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart, bool UpdateFlags) argument
1071 MachineInstr *MI = I; local
1103 MachineInstr *MI = I; local
[all...] |
| H A D | MachineBasicBlock.cpp | 146 void ilist_traits<MachineInstr>::deleteNode(MachineInstr* MI) { argument
722 MachineInstr *MI = I; local
742 MachineInstr *MI = I; local
953 unbundleSingleMI(MachineInstr *MI) argument
970 remove_instr(MachineInstr *MI) argument
978 insert(instr_iterator I, MachineInstr *MI) argument
[all...] |
| H A D | MachineFunction.cpp | 194 MachineFunction::DeleteMachineInstr(MachineInstr *MI) { argument
|
| H A D | MachineLICM.cpp | 153 MachineInstr *MI; member in struct:__anon2262::MachineLICM::CandidateInfo
387 InstructionStoresToFI(const MachineInstr *MI, int FI) argument
403 ProcessMI(MachineInstr *MI, BitVector &PhysRegDefs, BitVector &PhysRegClobbers, SmallSet<int, 32> &StoredFIs, SmallVectorImpl<CandidateInfo> &Candidates) argument
527 MachineInstr *MI = &*MII; local
564 MachineInstr *MI = Candidates[i].MI; local
594 MachineInstr *MI = &*MII; local
608 HoistPostRA(MachineInstr *MI, unsigned Def) argument
761 MachineInstr *MI = &*MII; local
779 getRegisterClassIDAndCost(const MachineInstr *MI, unsigned Reg, unsigned OpIdx, unsigned &RCId, unsigned &RCCost) const argument
812 MachineInstr *MI = &*MII; local
840 UpdateRegPressure(const MachineInstr *MI) argument
878 isLoadFromGOTOrConstantPool(MachineInstr &MI) argument
1009 HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, unsigned Reg) const argument
1099 UpdateBackTraceRegPressure(const MachineInstr *MI) argument
1144 IsProfitableToHoist(MachineInstr &MI) argument
1242 ExtractHoistableLoad(MachineInstr *MI) argument
1301 const MachineInstr *MI = &*I; local
1316 LookForDuplicate(const MachineInstr *MI, std::vector<const MachineInstr*> &PrevMIs) argument
1326 EliminateCSE(MachineInstr *MI, DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) argument
1385 MayCSE(MachineInstr *MI) argument
1400 Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) argument
[all...] |
| H A D | RegisterPressure.cpp | 359 static void collectOperands(const MachineInstr *MI, argument
700 void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) { argument
749 getMaxUpwardPressureDelta(const MachineInstr *MI, PressureDiff *PDiff, argument
817 getUpwardPressureDelta(const MachineInstr *MI, PressureDiff &PDiff, RegPressureDelta &Delta, ArrayRef<PressureChange> CriticalPSets, ArrayRef<unsigned> MaxPressureLimit) const argument
882 const MachineInstr* MI = &*UI; local
898 bumpDownwardPressure(const MachineInstr *MI) argument
946 getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta, ArrayRef<PressureChange> CriticalPSets, ArrayRef<unsigned> MaxPressureLimit) argument
969 getUpwardPressure(const MachineInstr *MI, std::vector<unsigned> &PressureResult, std::vector<unsigned> &MaxPressureResult) argument
985 getDownwardPressure(const MachineInstr *MI, std::vector<unsigned> &PressureResult, std::vector<unsigned> &MaxPressureResult) argument
[all...] |
| H A D | ScheduleDAGInstrs.cpp | 127 static void getUnderlyingObjectsForInstr(const MachineInstr *MI, argument
287 const MachineInstr *MI = SU->getInstr(); local
366 const MachineInstr *MI local
404 MachineInstr *MI = SU->getInstr(); local
451 isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) argument
461 isUnsafeMemoryObject(MachineInstr *MI, const MachineFrameInfo *MFI) argument
678 MachineInstr *MI = I; local
750 MachineInstr *MI = prior(MII); local
[all...] |
| H A D | SplitKit.cpp | 491 MachineInstr *MI = LIS.getInstructionFromIndex(Idx); local
508 MachineInstr *MI = LIS.getInstructionFromIndex(Idx); local
558 MachineInstr *MI = LIS.getInstructionFromIndex(Boundary); local
590 MachineInstr *MI = LIS.getInstructionFromIndex(Idx); local
643 MachineInstr *MI = LIS.getInstructionFromIndex(Def); local
652 DEBUG(dbgs() << "Removing " << Def << '\\t' << *MI); local
976 MachineInstr *MI = MO.getParent(); local
997 << Idx << ':' << RegIdx << '\\t' << *MI); local
1028 MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def); local
[all...] |
| H A D | TwoAddressInstructionPass.cpp | 179 sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg, argument
321 MachineInstr *MI = MO.getParent(); local
339 isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, unsigned &SrcReg, unsigned &DstReg, bool &IsSrcPhys, bool &IsDstPhys) argument
360 isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS) argument
402 isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives) argument
435 isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) argument
508 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC, MachineInstr *MI, unsigned Dist) argument
577 MachineInstr *MI = mi; local
718 processCopy(MachineInstr *MI) argument
915 isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI) argument
1299 collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) argument
1338 processTiedPairs(MachineInstr *MI, TiedPairList &TiedPairs, unsigned &Dist) argument
1607 MachineInstr *MI = MBBI; local
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 265 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, argument
|
| /freebsd-10.1-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 167 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument
249 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, argument
424 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
853 EmitJumpTable(const MachineInstr *MI) argument
904 EmitJump2Table(const MachineInstr *MI) argument
965 EmitUnwindingInstruction(const MachineInstr *MI) argument
1108 EmitInstruction(const MachineInstr *MI) argument
[all...] |
| H A D | ARMFrameLowering.cpp | 85 static bool isCSRestore(MachineInstr *MI, argument
581 emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, unsigned StmOpc, unsigned StrOpc, bool NoGap, bool(*Func)(unsigned, bool), unsigned NumAlignedDPRCS2Regs, unsigned MIFlags) const argument
650 emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, unsigned LdmOpc, unsigned LdrOpc, bool isVarArg, bool NoGap, bool(*Func)(unsigned, bool), unsigned NumAlignedDPRCS2Regs) const argument
736 emitAlignedDPRCS2Spills(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) argument
867 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs) argument
895 emitAlignedDPRCS2Restores(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) argument
974 spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
1005 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 168 getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
231 getCCOutOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const argument
239 getSOImmOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const argument
255 getT2SOImmOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const argument
280 getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const argument
351 NEONThumb2DataIPostEncoder(const MCInst &MI, unsigned EncodedValue) const argument
370 NEONThumb2LoadStorePostEncoder(const MCInst &MI, unsigned EncodedValue) const argument
383 NEONThumb2DupPostEncoder(const MCInst &MI, unsigned EncodedValue) const argument
395 NEONThumb2V8PostEncoder(const MCInst &MI, unsigned EncodedValue) const argument
407 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const argument
418 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups) const argument
446 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const argument
474 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl<MCFixup> &Fixups) argument
511 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
523 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
534 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
545 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
556 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
565 HasConditionalBranch(const MCInst &MI) argument
584 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
597 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
612 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
626 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
638 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
667 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
707 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
726 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
738 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &) const argument
752 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
803 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
834 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
874 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
899 getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
958 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
991 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1005 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1027 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1038 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1057 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1093 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1108 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1122 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1132 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1170 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1217 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVLIWPacketizer.cpp | 217 MachineBasicBlock::iterator MI = MBB->begin(); local
267 IsIndirectCall(MachineInstr* MI) argument
274 reserveResourcesForConstExt(MachineInstr* MI) argument
290 canReserveResourcesForConstExt(MachineInstr *MI) argument
304 tryAllocateResourcesForConstExt(MachineInstr* MI) argument
321 IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg) argument
369 IsDirectJump(MachineInstr* MI) argument
373 IsSchedBarrier(MachineInstr* MI) argument
381 IsControlFlow(MachineInstr* MI) argument
385 IsLoopN(MachineInstr *MI) argument
392 DoesModifyCalleeSavedReg(MachineInstr *MI, const TargetRegisterInfo *TRI) argument
404 isNewifiable(MachineInstr* MI) argument
412 isCondInst(MachineInstr* MI) argument
431 PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass* RC) argument
448 DemoteToDotOld(MachineInstr* MI) argument
463 getPredicateSense(MachineInstr* MI, const HexagonInstrInfo *QII) argument
474 GetPostIncrementOperand(MachineInstr *MI, const HexagonInstrInfo *QII) argument
514 GetStoreValueOperand(MachineInstr *MI) argument
538 CanPromoteToNewValueStore( MachineInstr *MI, MachineInstr *PacketMI, unsigned DepReg, std::map <MachineInstr*, SUnit*> MIToSUnit) argument
719 CanPromoteToNewValue( MachineInstr *MI, SUnit *PacketSU, unsigned DepReg, std::map <MachineInstr*, SUnit*> MIToSUnit, MachineBasicBlock::iterator &MII) argument
748 CanPromoteToDotNew( MachineInstr *MI, SUnit *PacketSU, unsigned DepReg, std::map <MachineInstr*, SUnit*> MIToSUnit, MachineBasicBlock::iterator &MII, const TargetRegisterClass* RC ) argument
805 RestrictingDepExistInPacket(MachineInstr* MI, unsigned DepReg, std::map <MachineInstr*, SUnit*> MIToSUnit) argument
841 getPredicatedRegister(MachineInstr *MI, const HexagonInstrInfo *QII) argument
956 ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB) argument
977 isSoloInstruction(MachineInstr *MI) argument
1351 addToPacket(MachineInstr *MI) argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 1198 MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI, argument
1306 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 47 static void RemoveVRSaveCode(MachineInstr *MI) { argument
93 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { argument
1194 spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
1261 restoreCRs(bool isPPC64, bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) argument
1314 MachineInstr *MI = I; local
1339 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
[all...] |
| H A D | PPCInstrInfo.cpp | 89 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, argument
103 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, argument
127 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const argument
154 commuteInstruction(MachineInstr *MI, bool NewMI) const argument
470 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc dl, unsigned DestReg, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg) const argument
657 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
770 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
930 PredicateInstruction( MachineInstr *MI, const SmallVectorImpl<MachineOperand> &Pred) const argument
1016 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument
1067 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
1124 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); local
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Target/R600/ |
| H A D | SIISelLowering.cpp | 335 EmitInstrWithCustomInserter( MachineInstr * MI, MachineBasicBlock * BB) const argument
1329 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const argument
[all...] |