Target/PowerPC/PPCInstrInfo.cpp

89 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
92   switch (MI.getOpcode()) {
96     SrcReg = MI.getOperand(1).getReg();
97     DstReg = MI.getOperand(0).getReg();
103 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
106   switch (MI->getOpcode()) {
117     if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
118         MI->getOperand(2).isFI()) {
119       FrameIndex = MI->getOperand(2).getIndex();
120       return MI->getOperand(0).getReg();
127 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
130   switch (MI->getOpcode()) {
141     if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
142         MI->getOperand(2).isFI()) {
143       FrameIndex = MI->getOperand(2).getIndex();
144       return MI->getOperand(0).getReg();
154 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
155   MachineFunction &MF = *MI->getParent()->getParent();
158   if (MI->getOpcode() != PPC::RLWIMI &&
159       MI->getOpcode() != PPC::RLWIMIo)
160     return TargetInstrInfo::commuteInstruction(MI, NewMI);
163   if (MI->getOperand(3).getImm() != 0)
174   unsigned Reg0 = MI->getOperand(0).getReg();
175   unsigned Reg1 = MI->getOperand(1).getReg();
176   unsigned Reg2 = MI->getOperand(2).getReg();
177   bool Reg1IsKill = MI->getOperand(1).isKill();
178   bool Reg2IsKill = MI->getOperand(2).isKill();
184     assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
191   unsigned MB = MI->getOperand(4).getImm();
192   unsigned ME = MI->getOperand(5).getImm();
196     unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
197     bool Reg0IsDead = MI->getOperand(0).isDead();
198     return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
207     MI->getOperand(0).setReg(Reg2);
208   MI->getOperand(2).setReg(Reg1);
209   MI->getOperand(1).setReg(Reg2);
210   MI->getOperand(2).setIsKill(Reg1IsKill);
211   MI->getOperand(1).setIsKill(Reg2IsKill);
214   MI->getOperand(4).setImm((ME+1) & 31);
215   MI->getOperand(5).setImm((MB-1) & 31);
216   return MI;
220                               MachineBasicBlock::iterator MI) const {
222   BuildMI(MBB, MI, DL, get(PPC::NOP));
471                                 MachineBasicBlock::iterator MI, DebugLoc dl,
524     BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
528   BuildMI(MBB, MI, dl, get(OpCode), DestReg)
658                                   MachineBasicBlock::iterator MI,
680     MBB.insert(MI, NewMIs[i]);
771                                    MachineBasicBlock::iterator MI,
778   if (MI != MBB.end()) DL = MI->getDebugLoc();
795     MBB.insert(MI, NewMIs[i]);
908 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
919 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
920   if (!MI->isTerminator())
924   if (MI->isBranch() && !MI->isBarrier())
927   return !isPredicated(MI);
931                      MachineInstr *MI,
933   unsigned OpC = MI->getOpcode();
937       MI->setDesc(get(Pred[0].getImm() ?
941       MI->setDesc(get(PPC::BCLR));
942       MachineInstrBuilder(*MI->getParent()->getParent(), MI)
951       MI->setDesc(get(Pred[0].getImm() ?
955       MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
956       MI->RemoveOperand(0);
958       MI->setDesc(get(PPC::BCC));
959       MachineInstrBuilder(*MI->getParent()->getParent(), MI)
973     MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
975     MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1016 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
1029   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1030     const MachineOperand &MO = MI->getOperand(i);
1052 bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
1053   unsigned OpC = MI->getOpcode();
1067 bool PPCInstrInfo::analyzeCompare(const MachineInstr *MI,
1070   unsigned Opc = MI->getOpcode();
1078     SrcReg = MI->getOperand(1).getReg();
1080     Value = MI->getOperand(2).getImm();
1089     SrcReg = MI->getOperand(1).getReg();
1090     SrcReg2 = MI->getOperand(2).getReg();
1124   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1125   if (!MI) return false;
1126   int MIOpC = MI->getOpcode();
1132       // We can perform this optimization only if MI is sign-extending.
1142       // We can perform this optimization, equality only, if MI is
1194   // One is MI, the other is a SUB instruction.
1198     // MI is not a candidate for CMPrr.
1199     MI = NULL;
1204   else if (MI->getParent() != CmpInstr->getParent() || Value != 0) {
1214   MachineBasicBlock::iterator E = MI,
1249   if (!MI && !Sub)
1252   // The single candidate is called MI.
1253   if (!MI) MI = Sub;
1256   MIOpC = MI->getOpcode();
1324   MachineBasicBlock::iterator MII = MI;
1325   BuildMI(*MI->getParent(), llvm::next(MII), MI->getDebugLoc(),
1338     MI->setDesc(NewDesc);
1343         if (!MI->definesRegister(*ImpDefs))
1344           MI->addOperand(*MI->getParent()->getParent(),
1349         if (!MI->readsRegister(*ImpUses))
1350           MI->addOperand(*MI->getParent()->getParent(),
1369 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
1370   switch (MI->getOpcode()) {
1372     const MachineFunction *MF = MI->getParent()->getParent();
1373     const char *AsmStr = MI->getOperand(0).getSymbolName();