Lines Matching defs:MI
153 MachineInstr *MI;
157 : MI(mi), Def(def), FI(fi) {}
167 void HoistPostRA(MachineInstr *MI, unsigned Def);
171 void ProcessMI(MachineInstr *MI,
195 bool HasLoopPHIUse(const MachineInstr *MI) const;
200 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
203 bool IsCheapInstruction(MachineInstr &MI) const;
212 /// effect of hoisting MI from the current block to the preheader.
213 void UpdateBackTraceRegPressure(const MachineInstr *MI);
217 bool IsProfitableToHoist(MachineInstr &MI);
243 /// getRegisterClassIDAndCost - For a given MI, register, and the operand
246 void getRegisterClassIDAndCost(const MachineInstr *MI,
257 void UpdateRegPressure(const MachineInstr *MI);
263 MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
266 /// duplicate of MI. Return this instruction if it's found.
267 const MachineInstr *LookForDuplicate(const MachineInstr *MI,
274 bool EliminateCSE(MachineInstr *MI,
279 bool MayCSE(MachineInstr *MI);
284 bool Hoist(MachineInstr *MI, MachineBasicBlock *Preheader);
387 static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
388 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
389 oe = MI->memoperands_end(); o != oe; ++o) {
403 void MachineLICM::ProcessMI(MachineInstr *MI,
411 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
412 const MachineOperand &MO = MI->getOperand(i);
418 InstructionStoresToFI(MI, FI))
474 // MI defined register is seen defined by another instruction in
483 if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
484 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
485 Candidates.push_back(CandidateInfo(MI, Def, FI));
527 MachineInstr *MI = &*MII;
528 ProcessMI(MI, PhysRegDefs, PhysRegClobbers, StoredFIs, Candidates);
564 MachineInstr *MI = Candidates[i].MI;
565 for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
566 const MachineOperand &MO = MI->getOperand(j);
579 HoistPostRA(MI, Candidates[i].Def);
594 MachineInstr *MI = &*MII;
595 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
596 MachineOperand &MO = MI->getOperand(i);
608 void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
614 << MI->getParent()->getNumber() << ": " << *MI);
617 MachineBasicBlock *MBB = MI->getParent();
618 Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
761 MachineInstr *MI = &*MII;
762 if (!Hoist(MI, Preheader))
763 UpdateRegPressure(MI);
776 /// getRegisterClassIDAndCost - For a given MI, register, and the operand
779 MachineLICM::getRegisterClassIDAndCost(const MachineInstr *MI,
812 MachineInstr *MI = &*MII;
813 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
814 const MachineOperand &MO = MI->getOperand(i);
823 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
840 void MachineLICM::UpdateRegPressure(const MachineInstr *MI) {
841 if (MI->isImplicitDef())
845 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
846 const MachineOperand &MO = MI->getOperand(i);
858 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
870 getRegisterClassIDAndCost(MI, Reg, Idx, RCId, RCCost);
878 static bool isLoadFromGOTOrConstantPool(MachineInstr &MI) {
879 assert (MI.mayLoad() && "Expected MI that loads!");
880 for (MachineInstr::mmo_iterator I = MI.memoperands_begin(),
881 E = MI.memoperands_end(); I != E; ++I) {
971 bool MachineLICM::HasLoopPHIUse(const MachineInstr *MI) const {
972 SmallVector<const MachineInstr*, 8> Work(1, MI);
974 MI = Work.pop_back_val();
975 for (ConstMIOperands MO(MI); MO.isValid(); ++MO) {
1009 bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
1029 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i))
1042 bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
1043 if (MI.isAsCheapAsAMove() || MI.isCopyLike())
1049 unsigned NumDefs = MI.getDesc().getNumDefs();
1050 for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {
1051 MachineOperand &DefMO = MI.getOperand(i);
1059 if (!TII->hasLowDefLatency(InstrItins, &MI, i))
1098 /// of hoisting MI from the current block to the preheader.
1099 void MachineLICM::UpdateBackTraceRegPressure(const MachineInstr *MI) {
1100 if (MI->isImplicitDef())
1106 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
1107 const MachineOperand &MO = MI->getOperand(i);
1115 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
1144 bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
1145 if (MI.isImplicitDef())
1160 bool CheapInstr = IsCheapInstruction(MI);
1161 bool CreatesCopy = HasLoopPHIUse(&MI);
1165 DEBUG(dbgs() << "Won't hoist cheap instr with loop PHI use: " << MI);
1171 if (TII->isTriviallyReMaterializable(&MI, AA))
1183 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
1184 const MachineOperand &MO = MI.getOperand(i);
1192 getRegisterClassIDAndCost(&MI, Reg, i, RCId, RCCost);
1194 if (HasHighOperandLatency(MI, i, Reg)) {
1195 DEBUG(dbgs() << "Hoist High Latency: " << MI);
1211 DEBUG(dbgs() << "Hoist non-reg-pressure: " << MI);
1218 DEBUG(dbgs() << "Won't hoist instr with loop PHI use: " << MI);
1226 (!IsGuaranteedToExecute(MI.getParent()) && !MayCSE(&MI))) {
1227 DEBUG(dbgs() << "Won't speculate: " << MI);
1233 if (!TII->isTriviallyReMaterializable(&MI, AA) &&
1234 !MI.isInvariantLoad(AA)) {
1235 DEBUG(dbgs() << "Can't remat / high reg-pressure: " << MI);
1242 MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
1244 if (MI->canFoldAsLoad())
1250 if (!MI->isInvariantLoad(AA))
1256 TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
1263 MachineFunction &MF = *MI->getParent()->getParent();
1270 TII->unfoldMemoryOperand(MF, MI, Reg,
1279 MachineBasicBlock *MBB = MI->getParent();
1280 MachineBasicBlock::iterator Pos = MI;
1295 MI->eraseFromParent();
1301 const MachineInstr *MI = &*I;
1302 unsigned Opcode = MI->getOpcode();
1306 CI->second.push_back(MI);
1309 CSEMIs.push_back(MI);
1316 MachineLICM::LookForDuplicate(const MachineInstr *MI,
1320 if (TII->produceSameValue(MI, PrevMI, (PreRegAlloc ? MRI : 0)))
1326 bool MachineLICM::EliminateCSE(MachineInstr *MI,
1330 if (CI == CSEMap.end() || MI->isImplicitDef())
1333 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
1334 DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
1336 // Replace virtual registers defined by MI by their counterparts defined
1339 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1340 const MachineOperand &MO = MI->getOperand(i);
1356 unsigned Reg = MI->getOperand(Idx).getReg();
1370 unsigned Reg = MI->getOperand(Idx).getReg();
1376 MI->eraseFromParent();
1385 bool MachineLICM::MayCSE(MachineInstr *MI) {
1386 unsigned Opcode = MI->getOpcode();
1391 if (CI == CSEMap.end() || MI->isImplicitDef())
1394 return LookForDuplicate(MI, CI->second) != 0;
1400 bool MachineLICM::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
1402 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
1404 MI = ExtractHoistableLoad(MI);
1405 if (!MI) return false;
1411 dbgs() << "Hoisting " << *MI;
1415 if (MI->getParent()->getBasicBlock())
1417 << MI->getParent()->getName();
1429 unsigned Opcode = MI->getOpcode();
1432 if (!EliminateCSE(MI, CI)) {
1434 Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
1437 UpdateBackTraceRegPressure(MI);
1442 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1443 MachineOperand &MO = MI->getOperand(i);
1450 CI->second.push_back(MI);
1453 CSEMIs.push_back(MI);