Target/ARM/ARMFrameLowering.cpp

36 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
85 static bool isCSRestore(MachineInstr *MI,
89   if (isPopOpcode(MI->getOpcode())) {
92     for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
93       if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
97   if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
98        MI->getOpcode() == ARM::LDR_POST_REG ||
99        MI->getOpcode() == ARM::t2LDR_POST) &&
100       isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
101       MI->getOperand(1).getReg() == ARM::SP)
582                                     MachineBasicBlock::iterator MI,
593   if (MI != MBB.end()) DL = MI->getDebugLoc();
634         AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
639       MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
651                                    MachineBasicBlock::iterator MI,
660   DebugLoc DL = MI->getDebugLoc();
661   unsigned RetOpcode = MI->getOpcode();
702         AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
707         MIB.copyImplicitOps(&*MI);
708         MI->eraseFromParent();
710       MI = MIB;
717         BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
737                                     MachineBasicBlock::iterator MI,
743   DebugLoc DL = MI->getDebugLoc();
783   AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
790   AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
799   MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
815     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
833     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
845     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
855     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
861   llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI);
867 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
872   ++MI; ++MI; ++MI;
873   assert(MI->mayStore() && "Expecting spill instruction");
878     ++MI;
879     assert(MI->mayStore() && "Expecting spill instruction");
881     ++MI;
882     assert(MI->mayStore() && "Expecting spill instruction");
886     assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
887     ++MI;
889   return MI;
896                                       MachineBasicBlock::iterator MI,
902   DebugLoc DL = MI->getDebugLoc();
922   AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
932     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
948     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
959     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
967     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
971   llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI);
975                                         MachineBasicBlock::iterator MI,
989   emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
991   emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
993   emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
1000     emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1006                                         MachineBasicBlock::iterator MI,
1020     emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1025   emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1027   emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1029   emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,