Target/R600/SIISelLowering.cpp

336     MachineInstr * MI, MachineBasicBlock * BB) const {
338   MachineBasicBlock::iterator I = *MI;
340   switch (MI->getOpcode()) {
342     return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
348     unsigned SuperReg = MI->getOperand(0).getReg();
353     BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
354             .addOperand(MI->getOperand(1));
355     BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
357     BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
359     BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
364     BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
369     MI->eraseFromParent();
375     BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64),
376             MI->getOperand(0).getReg())
377             .addReg(MI->getOperand(1).getReg())
378             .addReg(MI->getOperand(2).getReg())
384     MI->eraseFromParent();
393         BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
395     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
396       MIB.addOperand(MI->getOperand(i));
398     MI->eraseFromParent();
1329 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
1333   if (!TII->isMIMG(MI->getOpcode()))
1336   unsigned VReg = MI->getOperand(0).getReg();
1337   unsigned Writemask = MI->getOperand(1).getImm();
1350   unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
1351   MI->setDesc(TII->get(NewOpcode));
1352   MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();