Searched defs:CC (Results 176 - 195 of 195) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp604 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { argument
632 static bool invertFPCondCodeUser(Mips::CondCode CC) { argument
111 getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const argument
121 getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const argument
131 getVectorTypeBreakdownForCallingConv( LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const argument
659 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); local
668 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); local
709 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); local
746 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); local
2042 Mips::CondCode CC = local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2921 get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, int64_t RHSValue, SDLoc dl) argument
3094 get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, int64_t RHSValue, SDLoc dl) argument
3266 get64BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, int64_t RHSValue, SDLoc dl) argument
3423 get64BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, int64_t RHSValue, SDLoc dl) argument
3624 ISD::CondCode CC = local
3710 SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, const SDLoc &dl) argument
3867 getPredicateForSetCC(ISD::CondCode CC, const EVT &VT, const PPCSubtarget *Subtarget) argument
3908 getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) argument
3940 getVCmpInst(MVT VecVT, ISD::CondCode CC, bool HasVSX, bool &Swap, bool &Negate) argument
4051 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); local
4248 mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG, bool &NeedSwapOps, bool &IsUnCmp) argument
4989 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); local
5195 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); local
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H A DPPCISelLowering.cpp3194 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); local
3301 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, local
13218 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); local
13267 ISD::CondCode CC = local
13809 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); local
15433 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp514 const CallingConv::ID CC = TLI.getLibcallCallingConv(Libcall); local
491 createLibcall(MachineIRBuilder &MIRBuilder, const char *Name, const CallLowering::ArgInfo &Result, ArrayRef<CallLowering::ArgInfo> Args, const CallingConv::ID CC) argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp2691 AArch64CC::CondCode CC = StringSwitch<AArch64CC::CondCode>(Cond.lower()) local
2739 AArch64CC::CondCode CC = parseCondCodeString(Cond); local
3825 AArch64CC::CondCode CC = parseCondCodeString(Head); local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp932 CCAssignFn *AMDGPUCallLowering::CCAssignFnForCall(CallingConv::ID CC, argument
954 CCAssignFn *AMDGPUCallLowering::CCAssignFnForReturn(CallingConv::ID CC, argument
1011 CallingConv::ID CC = Fn.getCallingConv(); local
1133 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForCall(CallingConv::ID CC, argument
1138 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForReturn(CallingConv::ID CC, argument
1369 combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const argument
3583 SDValue CC = Cond.getOperand(2); local
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H A DSIISelLowering.cpp882 getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const argument
905 getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const argument
930 getVectorTypeBreakdownForCallingConv( LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const argument
2693 canGuaranteeTCO(CallingConv::ID CC) argument
2698 mayTailCallThisCC(CallingConv::ID CC) argument
10343 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2010 CCMaskForCondCode(ISD::CondCode CC) argument
2521 getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode, SDValue Call, unsigned CCValid, uint64_t CC, ISD::CondCode Cond) argument
4137 SDValue CC = getCCResult(DAG, SDValue(Node, 0)); local
4138 DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC); local
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/freebsd-13-stable/contrib/llvm-project/clang/lib/Sema/
H A DSemaDeclAttr.cpp4556 bool Sema::CheckCallingConvAttr(const ParsedAttr &Attrs, CallingConv &CC, argument
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H A DSemaType.cpp3740 CallingConv CC; local
3789 CallingConv CC = S.Context.getDefaultCallingConvention(FTI.isVariadic, local
7374 CallingConv CC = fn->getCallConv(); local
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H A DSemaChecking.cpp5503 CallingConv CC = CC_C; local
11277 CheckImplicitArgumentConversions(Sema &S, CallExpr *TheCall, SourceLocation CC) argument
11298 DiagnoseNullConversion(Sema &S, Expr *E, QualType T, SourceLocation CC) argument
11443 isSameWidthConstantConversion(Sema &S, Expr *E, QualType T, SourceLocation CC) argument
11516 CheckImplicitConversion(Sema &S, Expr *E, QualType T, SourceLocation CC, bool *ICContext = nullptr, bool IsListInit = false) argument
11951 CheckConditionalOperand(Sema &S, Expr *E, QualType T, SourceLocation CC, bool &ICContext) argument
11963 CheckConditionalOperator(Sema &S, AbstractConditionalOperator *E, SourceLocation CC, QualType T) argument
12000 CheckBoolLikeConversion(Sema &S, Expr *E, SourceLocation CC) argument
12011 SourceLocation CC; member in struct:__anon2029::AnalyzeImplicitConversionsWorkItem
12022 SourceLocation CC = Item.CC; local
12152 AnalyzeImplicitConversions(Sema &S, Expr *OrigE, SourceLocation CC, bool IsListInit ) argument
12421 CheckImplicitConversions(Expr *E, SourceLocation CC) argument
12441 CheckBoolLikeConversion(Expr *E, SourceLocation CC) argument
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H A DSemaDecl.cpp9371 CallingConv CC = FT->getExtInfo().getCC(); local
H A DSemaExpr.cpp16460 CallingConv CC = FD->getType()->castAs<FunctionType>()->getCallConv(); local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp777 RegsForValue(const SmallVector<unsigned, 4> &regs, MVT regvt, EVT valuevt, Optional<CallingConv::ID> CC) argument
782 RegsForValue(LLVMContext &Context, const TargetLowering &TLI, const DataLayout &DL, unsigned Reg, Type *Ty, Optional<CallingConv::ID> CC) argument
1885 CallingConv::ID CC = F->getCallingConv(); local
8808 CallingConv::ID CC = CB.getCallingConv(); local
10320 ISD::CondCode CC; local
10355 caseClusterRank(const CaseCluster &CC, CaseClusterIt First, CaseClusterIt Last) argument
10412 CaseCluster &CC = *FirstRight; local
10533 CaseCluster &CC = Clusters[Index]; local
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H A DDAGCombiner.cpp2104 ISD::CondCode CC local
884 isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, SDValue &CC, bool MatchStrict) const argument
7320 SDValue LHS, RHS, CC; local
8723 combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode CC, const TargetLowering &TLI, SelectionDAG &DAG) argument
8788 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); local
9044 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); local
9301 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); local
9401 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); local
9591 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); local
9990 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); local
10148 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); local
12972 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); local
14157 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); local
20968 ISD::CondCode CC; local
21149 foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC) argument
21224 convertSelectOfFPConstantsToLoadOffset( const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC) argument
21279 SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, bool NotExtCompare) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp899 struct CCOp CC; member in union:__anon4036::ARMOperand::__anon4039
3456 CreateCondCode(ARMCC::CondCodes CC, SMLoc S) argument
3465 CreateVPTPred(ARMVCC::VPTCodes CC, SMLoc S) argument
4226 unsigned CC = ARMCondCodeFromString(Tok.getString()); local
6352 unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2)); local
6400 unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1)); local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp6155 int CC; local
6233 int CC; local
6298 int CC; local
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/freebsd-13-stable/contrib/llvm-project/clang/include/clang/Sema/
H A DSema.h4298 FullExprArg MakeFullExpr(Expr *Arg, SourceLocation CC) { argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1712 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) { argument
1740 static void changeFPCCToAArch64CC(ISD::CondCode CC, argument
1803 static void changeFPCCToANDAArch64CC(ISD::CondCode CC, argument
1833 changeVectorFPCCToAArch64CC(ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert) argument
1882 isCMN(SDValue Op, ISD::CondCode CC) argument
1898 emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) argument
2004 emitConditionalComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue CCOp, AArch64CC::CondCode Predicate, AArch64CC::CondCode OutCC, const SDLoc &DL, SelectionDAG &DAG) argument
2122 ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get(); local
2274 getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, const SDLoc &dl) argument
2406 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) argument
2553 AArch64CC::CondCode CC; local
2656 AArch64CC::CondCode CC; local
3644 CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const argument
4102 canGuaranteeTCO(CallingConv::ID CC) argument
4107 mayTailCallThisCC(CallingConv::ID CC) argument
5363 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); local
5650 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(OpNo + 2))->get(); local
5725 LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS, SDValue TVal, SDValue FVal, const SDLoc &dl, SelectionDAG &DAG) const argument
5915 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); local
5956 ISD::CondCode CC; local
9013 EmitVectorComparison(SDValue LHS, SDValue RHS, AArch64CC::CondCode CC, bool NoNans, EVT VT, const SDLoc &dl, SelectionDAG &DAG) argument
9116 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); local
11396 ISD::CondCode CC; member in struct:GenericSetCCInfo
11402 AArch64CC::CondCode CC; member in struct:AArch64SetCCInfo
11785 tryConvertSVEWideCompare(SDNode *N, ISD::CondCode CC, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
11868 SDValue CC = DAG.getConstant(getInvertedCondCode(Cond), DL, MVT::i32); local
12980 isEquivalentMaskless(unsigned CC, unsigned width, ISD::LoadExtType ExtType, int AddConstant, int CompConstant) argument
13060 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue(); local
13148 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue(); local
14816 shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd( SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp545 const CallingConv::ID CC; member in struct:__anon4021
642 const CallingConv::ID CC; member in struct:__anon4022
665 const CallingConv::ID CC; member in struct:__anon4023
712 const CallingConv::ID CC; member in struct:__anon4024
1194 const CallingConv::ID CC; member in struct:__anon4025
1215 const CallingConv::ID CC; member in struct:__anon4026
1912 IntCCToARMCC(ISD::CondCode CC) argument
1929 FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, ARMCC::CondCodes &CondCode2) argument
1965 getEffectiveCallingConv(CallingConv::ID CC, bool isVarArg) const argument
2003 CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const argument
2008 CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const argument
2015 CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const argument
4462 getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const argument
4894 checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool &swpCmpOps, bool &swpVselOps) argument
4970 isGTorGE(ISD::CondCode CC) argument
4974 isLTorLE(ISD::CondCode CC) argument
4984 isLowerSaturate(const SDValue LHS, const SDValue RHS, const SDValue TrueVal, const SDValue FalseVal, const ISD::CondCode CC, const SDValue K) argument
4994 isUpperSaturate(const SDValue LHS, const SDValue RHS, const SDValue TrueVal, const SDValue FalseVal, const ISD::CondCode CC, const SDValue K) argument
5124 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); local
5202 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); local
5408 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); local
5495 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); local
6413 SDValue CC = Op.getOperand(2); local
9223 CallingConv::ID CC = getLibcallCallingConv(LC); local
9678 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(3))->get(); local
11416 isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG) argument
13021 isValidMVECond(unsigned CC, bool IsFloat) argument
13048 ARMCC::CondCodes CC = ARMCC::getOppositeCondition(getVCMPCondCode(N)); local
13206 ARMCC::CondCodes CC = ARMCC::getOppositeCondition(getVCMPCondCode(N0)); local
15432 auto CC = CCNode->getAPIntValue().getLimitedValue(); local
15511 SearchLoopIntrinsic(SDValue N, ISD::CondCode &CC, int &Imm, bool &Negate) argument
15563 ISD::CondCode CC; local
15685 ARMCC::CondCodes CC = local
15725 ARMCC::CondCodes CC = local
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