Lines Matching defs:CC
545 const CallingConv::ID CC;
631 setLibcallCallingConv(LC.Op, LC.CC);
642 const CallingConv::ID CC;
654 setLibcallCallingConv(LC.Op, LC.CC);
665 const CallingConv::ID CC;
679 setLibcallCallingConv(LC.Op, LC.CC);
712 const CallingConv::ID CC;
721 setLibcallCallingConv(LC.Op, LC.CC);
1194 const CallingConv::ID CC;
1209 setLibcallCallingConv(LC.Op, LC.CC);
1215 const CallingConv::ID CC;
1230 setLibcallCallingConv(LC.Op, LC.CC);
1911 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1912 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1913 switch (CC) {
1928 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1929 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1932 switch (CC) {
1965 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1967 switch (CC) {
1974 return CC;
2003 CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2005 return CCAssignFnForNode(CC, false, isVarArg);
2008 CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
2010 return CCAssignFnForNode(CC, true, isVarArg);
2015 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
2018 switch (getEffectiveCallingConv(CC, isVarArg)) {
4194 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
4195 bool IsABIRegCopy = CC.hasValue();
4212 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
4213 bool IsABIRegCopy = CC.hasValue();
4462 SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4469 switch (CC) {
4474 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4481 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4488 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4495 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4505 CC = ISD::getSetCCSwappedOperands(CC);
4533 !isSignedIntSetCC(CC)) {
4556 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4570 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4894 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4898 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4899 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
4903 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
4904 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
4909 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4910 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
4921 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4922 CC == ISD::SETUGT) {
4930 if (CC == ISD::SETO) {
4938 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
4970 static bool isGTorGE(ISD::CondCode CC) {
4971 return CC == ISD::SETGT || CC == ISD::SETGE;
4974 static bool isLTorLE(ISD::CondCode CC) {
4975 return CC == ISD::SETLT || CC == ISD::SETLE;
4978 // See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
4986 const ISD::CondCode CC, const SDValue K) {
4987 return (isGTorGE(CC) &&
4989 (isLTorLE(CC) &&
4996 const ISD::CondCode CC, const SDValue K) {
4997 return (isGTorGE(CC) &&
4999 (isLTorLE(CC) &&
5124 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5145 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
5202 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5224 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5234 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5243 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5252 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5260 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5266 CC = ISD::SETNE;
5284 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5287 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5294 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5302 FPCCToARMCC(CC, CondCode, CondCode2);
5315 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5408 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5422 if (CC == ISD::SETOEQ)
5423 CC = ISD::SETEQ;
5424 else if (CC == ISD::SETUNE)
5425 CC = ISD::SETNE;
5434 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5446 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5495 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5503 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5509 CC = ISD::SETNE;
5521 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5531 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5546 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5553 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5554 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5560 FPCCToARMCC(CC, CondCode, CondCode2);
6413 SDValue CC = Op.getOperand(2);
6415 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9223 CallingConv::ID CC = getLibcallCallingConv(LC);
9229 .setCallee(CC, RetTy, Callee, std::move(Args))
9678 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(3))->get();
9685 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS, Chain, IsSignaling);
9688 CC = ISD::SETNE;
9691 DAG.getCondCode(CC));
9696 FPCCToARMCC(CC, CondCode, CondCode2);
11231 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
11414 // Invert is set when N is the null/all ones constant when CC is false.
11417 SDValue &CC, bool &Invert,
11423 CC = N->getOperand(0);
11446 CC = N->getOperand(0);
11447 if (CC.getValueType() != MVT::i1 || CC.getOpcode() != ISD::SETCC)
11502 // Slct is now know to be the desired identity constant when CC is true.
11506 // Unless SwapSelectOps says CC should be false.
13021 static bool isValidMVECond(unsigned CC, bool IsFloat) {
13022 switch (CC) {
13048 ARMCC::CondCodes CC = ARMCC::getOppositeCondition(getVCMPCondCode(N));
13049 return isValidMVECond(CC, N->getOperand(0).getValueType().isFloatingPoint());
13206 ARMCC::CondCodes CC = ARMCC::getOppositeCondition(getVCMPCondCode(N0));
13212 Ops.push_back(DCI.DAG.getConstant(CC, DL, MVT::i32));
15432 auto CC = CCNode->getAPIntValue().getLimitedValue();
15448 if (CC == ARMCC::EQ) {
15453 assert(CC == ARMCC::NE && "How can a CMPZ node not be EQ or NE?");
15511 static SDValue SearchLoopIntrinsic(SDValue N, ISD::CondCode &CC, int &Imm,
15522 return SearchLoopIntrinsic(N.getOperand(0), CC, Imm, Negate);
15534 CC = cast<CondCodeSDNode>(N.getOperand(2))->get();
15535 return SearchLoopIntrinsic(N->getOperand(0), CC, Imm, Negate);
15563 ISD::CondCode CC;
15571 CC = ISD::SETEQ;
15576 CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
15587 SDValue Int = SearchLoopIntrinsic(Cond, CC, Imm, Negate);
15592 CC = ISD::getSetCCInverse(CC, /* Integer inverse */ MVT::i32);
15594 auto IsTrueIfZero = [](ISD::CondCode CC, int Imm) {
15595 return (CC == ISD::SETEQ && Imm == 0) ||
15596 (CC == ISD::SETNE && Imm == 1) ||
15597 (CC == ISD::SETLT && Imm == 1) ||
15598 (CC == ISD::SETULT && Imm == 1);
15601 auto IsFalseIfZero = [](ISD::CondCode CC, int Imm) {
15602 return (CC == ISD::SETEQ && Imm == 1) ||
15603 (CC == ISD::SETNE && Imm == 0) ||
15604 (CC == ISD::SETGT && Imm == 0) ||
15605 (CC == ISD::SETUGT && Imm == 0) ||
15606 (CC == ISD::SETGE && Imm == 1) ||
15607 (CC == ISD::SETUGE && Imm == 1);
15610 assert((IsTrueIfZero(CC, Imm) || IsFalseIfZero(CC, Imm)) &&
15632 if (IsTrueIfZero(CC, Imm)) {
15654 SDValue Target = IsFalseIfZero(CC, Imm) ? Dest : OtherTarget;
15685 ARMCC::CondCodes CC =
15688 // (brcond Chain BB ne CPSR (cmpz (and (cmov 0 1 CC CPSR Cmp) 1) 0))
15689 // -> (brcond Chain BB CC CPSR Cmp)
15690 if (CC == ARMCC::NE && LHS.getOpcode() == ISD::AND && LHS->hasOneUse() &&
15725 ARMCC::CondCodes CC =
15753 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
15756 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
15763 // (cmov F T ne CPSR (cmpz (cmov 0 1 CC CPSR Cmp) 0))
15764 // -> (cmov F T CC CPSR Cmp)
15765 if (CC == ARMCC::NE && LHS.getOpcode() == ARMISD::CMOV && LHS->hasOneUse()) {
15783 if (CC == ARMCC::EQ && isOneConstant(TrueVal)) {
15811 } else if (CC == ARMCC::NE && !isNullConstant(RHS) &&
15824 if (CC == ARMCC::EQ && !isNullConstant(RHS) &&
15854 if (Subtarget->isThumb1Only() && CC == ARMCC::NE &&