Synch the cpu match/attach/identify code with arm64. This drops some
information from dmesg that is no longer relevant to ARMv7 CPUs in favour
of printing the full architected cache hierarchy in the same way as we
do on arm64. It also is another small step towards SMP support on armv7.

ok patrick@

Add Cortex-A55 and Cortex-A75 part numbers.

Bring over the changes to mainbus(4) and simplebus(4) from arm64.

Add support for Cortex-A12. Even though ARM rebranded these as Cortex-A17
they have a different ID from "real" Cortex-A17 cores.

ok phessler@, patrick@

unifdef CPU_XSCALE_PXA2X0, ARM_MMU_XSCALE, ARM_MMU_GENERIC (armv3)
and remove some xscale definitions.

ok kettenis@

recognise Cortex A32

Enable the UWXN bit in the SCTRL register when available. This should
prevent the kernel from accidentally executing userland pages that are
writable.

ok jsg@, patrick@

Replace pmap_fault_fixup() with an access flag fault handler on armv7.

ok tom@

Remove code for Intel 80219/80321 xscale processors used by armish.
Generic xscale support and support for pxa2x0 used by zaurus remains.

Fix setting the SMP bit in the Auxiliary Control Register. The old code was
toggling the bit, clearing it when already set. On Cortex-A7 setting the SMP
bit is essential since without it the CPU doesn't actually use its caches.

The SMP bit supposed to be set before turning on the caches and the MMU, so
move the setting of the Auxiliary Control Register before setting the
System Control Register.

ok jsg@

Put page tables in normal cachable memory on armv7. Check if the MMU walks
the page tables coherently and also skip flushing modified ptes out of the
cache in that case. Speeds up building a kernel with a factor of two on
Cortex-A9 (tested by me) and Cortex-A8 (tested by mglocker@).

ok patrick@

Recognise Cortex A35 and Cortex A73.

Instead of testing MIDR values for every model of Cortex processor check
MMFR0 for an ARMv7 VMSA MMU that can handle short descriptors when
setting ARMv7 function pointers. ARMv8 in AArch32 mode is documented to
set the same bits.

ok patrick@

Read cache line sizes from CP15 Cache Type Register.

Previously we used the primary data cache's information on how big
the cache lines are. The CTR gives us better information about how
big the smallest cache line sizes (controlled by the CPU) are.

ok jsg@

Set the SMP/coherency bit in ACTLR on Cortex A models it is documented
to exist on. This is required to use ldrex/strex in some cases.

ok patrick@

Remove support for ARM11. This was the last unused and unmaintained
processor in our code. Now we're left with only armv7 and XScale for
armish and zaurus.

ok jsg@

Remove support for ARM10.

ok jsg@

Remove support for ARM9E. This is another step in the plan to remove
all unused and unmaintained ARM processors from the past.

ok bmercer@ jsg@

Remove defines for unsupported chips, add V5TEJ and remove incorrect
ARCH_V7 define. The number ARM Ltd armv7 chips set here is 0xf,
documented as 'Defined by CPUID scheme'.

ok patrick@ bmercer@

Remove support for the XScale 80200. We don't use it, it didn't compile
and the included headers didn't even exist.

ok jsg@

Remove support for IXP425. This is another architecture that is not
used and has probably never been used at all. Some included headers
do not even exist.

ok jsg@

Remove support for StrongARM (SA1) and IXP12x0. Both are ARMv4 and
are not used by any of the arm platforms.

ok jsg@

Remove support for ARM9T (armv4t). Not used by any of the arm platforms.
From Patrick Wildt.

Remove support for ARM8, an old armv4 processor without thumb that was
never supported by any arm port and wouldn't have built due to a missing
cpufunc_asm_arm8.S file.

From Patrick Wildt.

fix the name of the define for the a72 mask
from Patrick Wildt

Switch from PSR_X_bit and X32_bit PSR macro names to just PSR_X.
This matches FreeBSD and makes things a bit more consistent.
Discussed with Patrick.

In some cases machines with virtualisation extensions will boot into a
HYP processor mode that has different memory management and register
behaviour among other things. In this case switch to SVC mode to
prevent an early crash.

From Patrick Wildt based on code in FreeBSD.

add some more cortex A ids

Add an ascii bit/field diagram for armv7-a psr to match the
existing one for earlier arm revisions.

1 << 31 cleanup. Eitan Adler pointed out that there has been a
resurrection of the bad idiom in the tree.
sufficient review by miod, kettenis, tedu

add Cortex A15 R4
ok patrick@

Improved dealing of ARMv7 faults. Added ARMv7 fault descriptions.

ok bmercer@
tested on zaurus by todd@ and patrick@
tested on armv7 boards

Update the ARM CPU ID information. The IDs aren't vendor/product
specific, they are specific to the ARM CPUs themselves.

ok bmercer@ jsg@ deraadt@

Late spring cleaning of the arm code for old dusty bits we do not want to
keep:
- remove bootconfig parameter passing feature (unused).
- unifdef __PROG32 and remove all remains of arm26 code.
- remove ARMFPE support (unused).
- remove support for ARM2, ARM2AS, ARM3, ARM6, ARM7, ARM7TDMI and StrongARM
processor families, and the related silicon bug workarounds (especially
the SA-110 STM^ bug).
- remove cpu_functions no longer necessary after previous removals.
- remove ARM32_DISABLE_ALIGNMENT_FAULTS option (unused).
- make FIQ support conditional on option FIQ (unused, but may be eventually).

Discussed with drahn@ and jasper@ long ago, I was sitting on this commit for
no good reason.

- recognize OMAP3630/DM3730, as found in the beagleboard xM

ok drahn@

typo. CPU_ID_ARM1022EJS -> CPU_ID_ARM1026EJS

ok drahn@

Improve the ARMv7 support, still work in progress.

Add some (not used yet) control regiser bit definitions.

Pieces of arm11 and armv7 support for newer cpus. This is work in progress
and not complete.

add support for arm9e core, taken from NetBSD.
ok drahn@

Add support for i80321 based systems.

Add pxa270 id

branches: 1.1.2;
Arm port, NetBSD codebase stripped down, 32bit only support.

Add Cortex-A55 and Cortex-A75 part numbers.

Bring over the changes to mainbus(4) and simplebus(4) from arm64.

Add support for Cortex-A12. Even though ARM rebranded these as Cortex-A17
they have a different ID from "real" Cortex-A17 cores.

ok phessler@, patrick@

unifdef CPU_XSCALE_PXA2X0, ARM_MMU_XSCALE, ARM_MMU_GENERIC (armv3)
and remove some xscale definitions.

ok kettenis@

recognise Cortex A32

Enable the UWXN bit in the SCTRL register when available. This should
prevent the kernel from accidentally executing userland pages that are
writable.

ok jsg@, patrick@

Replace pmap_fault_fixup() with an access flag fault handler on armv7.

ok tom@

Remove code for Intel 80219/80321 xscale processors used by armish.
Generic xscale support and support for pxa2x0 used by zaurus remains.

Fix setting the SMP bit in the Auxiliary Control Register. The old code was
toggling the bit, clearing it when already set. On Cortex-A7 setting the SMP
bit is essential since without it the CPU doesn't actually use its caches.

The SMP bit supposed to be set before turning on the caches and the MMU, so
move the setting of the Auxiliary Control Register before setting the
System Control Register.

ok jsg@

Put page tables in normal cachable memory on armv7. Check if the MMU walks
the page tables coherently and also skip flushing modified ptes out of the
cache in that case. Speeds up building a kernel with a factor of two on
Cortex-A9 (tested by me) and Cortex-A8 (tested by mglocker@).

ok patrick@

Recognise Cortex A35 and Cortex A73.

Instead of testing MIDR values for every model of Cortex processor check
MMFR0 for an ARMv7 VMSA MMU that can handle short descriptors when
setting ARMv7 function pointers. ARMv8 in AArch32 mode is documented to
set the same bits.

ok patrick@

Read cache line sizes from CP15 Cache Type Register.

Previously we used the primary data cache's information on how big
the cache lines are. The CTR gives us better information about how
big the smallest cache line sizes (controlled by the CPU) are.

ok jsg@

Set the SMP/coherency bit in ACTLR on Cortex A models it is documented
to exist on. This is required to use ldrex/strex in some cases.

ok patrick@

Remove support for ARM11. This was the last unused and unmaintained
processor in our code. Now we're left with only armv7 and XScale for
armish and zaurus.

ok jsg@

Remove support for ARM10.

ok jsg@

Remove support for ARM9E. This is another step in the plan to remove
all unused and unmaintained ARM processors from the past.

ok bmercer@ jsg@

Remove defines for unsupported chips, add V5TEJ and remove incorrect
ARCH_V7 define. The number ARM Ltd armv7 chips set here is 0xf,
documented as 'Defined by CPUID scheme'.

ok patrick@ bmercer@

Remove support for the XScale 80200. We don't use it, it didn't compile
and the included headers didn't even exist.

ok jsg@

Remove support for IXP425. This is another architecture that is not
used and has probably never been used at all. Some included headers
do not even exist.

ok jsg@

Remove support for StrongARM (SA1) and IXP12x0. Both are ARMv4 and
are not used by any of the arm platforms.

ok jsg@

Remove support for ARM9T (armv4t). Not used by any of the arm platforms.
From Patrick Wildt.

Remove support for ARM8, an old armv4 processor without thumb that was
never supported by any arm port and wouldn't have built due to a missing
cpufunc_asm_arm8.S file.

From Patrick Wildt.

fix the name of the define for the a72 mask
from Patrick Wildt

Switch from PSR_X_bit and X32_bit PSR macro names to just PSR_X.
This matches FreeBSD and makes things a bit more consistent.
Discussed with Patrick.

In some cases machines with virtualisation extensions will boot into a
HYP processor mode that has different memory management and register
behaviour among other things. In this case switch to SVC mode to
prevent an early crash.

From Patrick Wildt based on code in FreeBSD.

add some more cortex A ids

Add an ascii bit/field diagram for armv7-a psr to match the
existing one for earlier arm revisions.

1 << 31 cleanup. Eitan Adler pointed out that there has been a
resurrection of the bad idiom in the tree.
sufficient review by miod, kettenis, tedu

add Cortex A15 R4
ok patrick@

Improved dealing of ARMv7 faults. Added ARMv7 fault descriptions.

ok bmercer@
tested on zaurus by todd@ and patrick@
tested on armv7 boards

Update the ARM CPU ID information. The IDs aren't vendor/product
specific, they are specific to the ARM CPUs themselves.

ok bmercer@ jsg@ deraadt@

Late spring cleaning of the arm code for old dusty bits we do not want to
keep:
- remove bootconfig parameter passing feature (unused).
- unifdef __PROG32 and remove all remains of arm26 code.
- remove ARMFPE support (unused).
- remove support for ARM2, ARM2AS, ARM3, ARM6, ARM7, ARM7TDMI and StrongARM
processor families, and the related silicon bug workarounds (especially
the SA-110 STM^ bug).
- remove cpu_functions no longer necessary after previous removals.
- remove ARM32_DISABLE_ALIGNMENT_FAULTS option (unused).
- make FIQ support conditional on option FIQ (unused, but may be eventually).

Discussed with drahn@ and jasper@ long ago, I was sitting on this commit for
no good reason.

- recognize OMAP3630/DM3730, as found in the beagleboard xM

ok drahn@

typo. CPU_ID_ARM1022EJS -> CPU_ID_ARM1026EJS

ok drahn@

Improve the ARMv7 support, still work in progress.

Add some (not used yet) control regiser bit definitions.

Pieces of arm11 and armv7 support for newer cpus. This is work in progress
and not complete.

add support for arm9e core, taken from NetBSD.
ok drahn@

Add support for i80321 based systems.

Add pxa270 id

branches: 1.1.2;
Arm port, NetBSD codebase stripped down, 32bit only support.