armreg.h revision 1.18
1/* $OpenBSD: armreg.h,v 1.18 2016/01/31 00:14:50 jsg Exp $ */ 2/* $NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $ */ 3 4/* 5 * Copyright (c) 1998, 2001 Ben Harris 6 * Copyright (c) 1994-1996 Mark Brinicombe. 7 * Copyright (c) 1994 Brini. 8 * All rights reserved. 9 * 10 * This code is derived from software written for Brini by Mark Brinicombe 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by Brini. 23 * 4. The name of the company nor the name of the author may be used to 24 * endorse or promote products derived from this software without specific 25 * prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 31 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 32 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 */ 39 40#ifndef _ARM_ARMREG_H 41#define _ARM_ARMREG_H 42 43/* 44 * ARM Process Status Register 45 * 46 * The picture in early ARM manuals looks like this: 47 * 3 3 2 2 2 2 48 * 1 0 9 8 7 6 8 7 6 5 4 0 49 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 50 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| 51 * | | | | | | | | | |4 3 2 1 0| 52 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 53 * 54 * The picture in the ARMv7-A manuals looks like this: 55 * 3 3 2 2 2 2 2 2 2 2 1 1 1 1 56 * 1 0 9 8 7 6 5 4 3 0 9 6 5 0 9 8 7 6 5 4 0 57 * +-+-+-+-+-+---+-+-------+-------+-----------+-+-+-+-+-+---------+ 58 * |N|Z|C|V|Q|I I|J|reserv-|G G G G|I I I I I I|E|A|I|F|T|M M M M M| 59 * | | | | | |T T| |ed |E E E E|T T T T T T| | | | | | | 60 * | | | | | |1 0| | |3 2 1 0|7 6 5 4 3 2| | | | | |4 3 2 1 0| 61 * +-+-+-+-+-+---+-+-------+-------+-----------+-+-+-+-+-+---------+ 62 * | flags 'f' | status 's' | extension 'x' | control 'c' | 63 */ 64 65#define PSR_FLAGS 0xf0000000 /* flags */ 66#define PSR_N (1U << 31) /* negative */ 67#define PSR_Z (1 << 30) /* zero */ 68#define PSR_C (1 << 29) /* carry */ 69#define PSR_V (1 << 28) /* overflow */ 70 71#define PSR_Q (1 << 27) /* saturation */ 72 73#define PSR_A (1 << 8) /* Asynchronous abort disable */ 74#define PSR_I (1 << 7) /* IRQ disable */ 75#define PSR_F (1 << 6) /* FIQ disable */ 76 77#define PSR_T (1 << 5) /* Thumb state */ 78#define PSR_J (1 << 24) /* Java mode */ 79 80#define PSR_MODE 0x0000001f /* mode mask */ 81#define PSR_USR26_MODE 0x00000000 82#define PSR_FIQ26_MODE 0x00000001 83#define PSR_IRQ26_MODE 0x00000002 84#define PSR_SVC26_MODE 0x00000003 85#define PSR_USR32_MODE 0x00000010 86#define PSR_FIQ32_MODE 0x00000011 87#define PSR_IRQ32_MODE 0x00000012 88#define PSR_SVC32_MODE 0x00000013 89#define PSR_MON32_MODE 0x00000016 90#define PSR_ABT32_MODE 0x00000017 91#define PSR_HYP32_MODE 0x0000001a 92#define PSR_UND32_MODE 0x0000001b 93#define PSR_SYS32_MODE 0x0000001f 94#define PSR_32_MODE 0x00000010 95 96#define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ 97 98/* 99 * Co-processor 15: The system control co-processor. 100 */ 101 102#define ARM_CP15_CPU_ID 0 103 104/* 105 * The CPU ID register is theoretically structured, but the definitions of 106 * the fields keep changing. 107 */ 108 109/* The high-order byte is always the implementor */ 110#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 111#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 112#define CPU_ID_DEC 0x44000000 /* 'D' */ 113#define CPU_ID_INTEL 0x69000000 /* 'i' */ 114#define CPU_ID_TI 0x54000000 /* 'T' */ 115 116/* How to decide what format the CPUID is in. */ 117#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 118#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 119#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 120 121/* On ARM3 and ARM6, this byte holds the foundry ID. */ 122#define CPU_ID_FOUNDRY_MASK 0x00ff0000 123#define CPU_ID_FOUNDRY_VLSI 0x00560000 124 125/* On ARM7 it holds the architecture and variant (sub-model) */ 126#define CPU_ID_7ARCH_MASK 0x00800000 127#define CPU_ID_7ARCH_V3 0x00000000 128#define CPU_ID_7ARCH_V4T 0x00800000 129#define CPU_ID_7VARIANT_MASK 0x007f0000 130 131/* On more recent ARMs, it does the same, but in a different format */ 132#define CPU_ID_ARCH_MASK 0x000f0000 133#define CPU_ID_ARCH_V3 0x00000000 134#define CPU_ID_ARCH_V4 0x00010000 135#define CPU_ID_ARCH_V4T 0x00020000 136#define CPU_ID_ARCH_V5 0x00030000 137#define CPU_ID_ARCH_V5T 0x00040000 138#define CPU_ID_ARCH_V5TE 0x00050000 139#define CPU_ID_ARCH_V6 0x00070000 140#define CPU_ID_ARCH_V7 0x00080000 141#define CPU_ID_VARIANT_MASK 0x00f00000 142 143/* Next three nybbles are part number */ 144#define CPU_ID_PARTNO_MASK 0x0000fff0 145 146/* Intel XScale has sub fields in part number */ 147#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 148#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 149#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 150 151/* And finally, the revision number. */ 152#define CPU_ID_REVISION_MASK 0x0000000f 153 154/* Individual CPUs are probably best IDed by everything but the revision. */ 155#define CPU_ID_CPU_MASK 0xfffffff0 156 157/* Fake CPU IDs for ARMs without CP15 */ 158#define CPU_ID_ARM2 0x41560200 159#define CPU_ID_ARM250 0x41560250 160 161/* Pre-ARM7 CPUs -- [15:12] == 0 */ 162#define CPU_ID_ARM3 0x41560300 163#define CPU_ID_ARM600 0x41560600 164#define CPU_ID_ARM610 0x41560610 165#define CPU_ID_ARM620 0x41560620 166 167/* ARM7 CPUs -- [15:12] == 7 */ 168#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 169#define CPU_ID_ARM710 0x41007100 170#define CPU_ID_ARM7500 0x41027100 /* XXX This is a guess. */ 171#define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ 172#define CPU_ID_ARM7500FE 0x41077100 173#define CPU_ID_ARM710T 0x41807100 174#define CPU_ID_ARM720T 0x41807200 175#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 176#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 177 178/* Post-ARM7 CPUs */ 179#define CPU_ID_ARM810 0x41018100 180#define CPU_ID_ARM920T 0x41129200 181#define CPU_ID_ARM922T 0x41029220 182#define CPU_ID_ARM926EJS 0x41069260 183#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 184#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 185#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 186#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 187#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 188#define CPU_ID_ARM1022ES 0x4105a220 189#define CPU_ID_ARM1026EJS 0x4106a260 190#define CPU_ID_ARM1136JS 0x4107b360 191#define CPU_ID_ARM1136JSR1 0x4117b360 192#define CPU_ID_SA110 0x4401a100 193#define CPU_ID_SA1100 0x4401a110 194#define CPU_ID_TI925T 0x54029250 195#define CPU_ID_SA1110 0x6901b110 196#define CPU_ID_IXP1200 0x6901c120 197#define CPU_ID_80200 0x69052000 198#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 199#define CPU_ID_PXA210 0x69052120 200#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 201#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 202#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 203#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 204#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 205#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 206#define CPU_ID_80219_400 0x69052e20 207#define CPU_ID_80219_600 0x69052e30 208#define CPU_ID_PXA27X 0x69054110 209#define CPU_ID_80321_400 0x69052420 210#define CPU_ID_80321_600 0x69052430 211#define CPU_ID_80321_400_B0 0x69052c20 212#define CPU_ID_80321_600_B0 0x69052c30 213#define CPU_ID_IXP425_533 0x690541c0 214#define CPU_ID_IXP425_400 0x690541d0 215#define CPU_ID_IXP425_266 0x690541f0 216#define CPU_ID_CORTEX_A5 0x410fc050 217#define CPU_ID_CORTEX_A5_MASK 0xff0ffff0 218#define CPU_ID_CORTEX_A7 0x410fc070 219#define CPU_ID_CORTEX_A7_MASK 0xff0ffff0 220#define CPU_ID_CORTEX_A8_R1 0x411fc080 221#define CPU_ID_CORTEX_A8_R2 0x412fc080 222#define CPU_ID_CORTEX_A8_R3 0x413fc080 223#define CPU_ID_CORTEX_A8 0x410fc080 224#define CPU_ID_CORTEX_A8_MASK 0xff0ffff0 225#define CPU_ID_CORTEX_A9 0x410fc090 226#define CPU_ID_CORTEX_A9_R1 0x411fc090 227#define CPU_ID_CORTEX_A9_R2 0x412fc090 228#define CPU_ID_CORTEX_A9_R3 0x413fc090 229#define CPU_ID_CORTEX_A9_R4 0x414fc090 230#define CPU_ID_CORTEX_A9_MASK 0xff0ffff0 231#define CPU_ID_CORTEX_A15 0x410fc0f0 232#define CPU_ID_CORTEX_A15_R1 0x411fc0f0 233#define CPU_ID_CORTEX_A15_R2 0x412fc0f0 234#define CPU_ID_CORTEX_A15_R3 0x413fc0f0 235#define CPU_ID_CORTEX_A15_R4 0x414fc0f0 236#define CPU_ID_CORTEX_A15_MASK 0xff0ffff0 237#define CPU_ID_CORTEX_A17 0x410fc0e0 238#define CPU_ID_CORTEX_A17_R1 0x411fc0e0 239#define CPU_ID_CORTEX_A17_MASK 0xff0ffff0 240#define CPU_ID_CORTEX_A53 0x410fd030 241#define CPU_ID_CORTEX_A53_R1 0x411fd030 242#define CPU_ID_CORTEX_A53_MASK 0xff0ffff0 243#define CPU_ID_CORTEX_A57 0x410fd070 244#define CPU_ID_CORTEX_A57_R1 0x411fd070 245#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0 246#define CPU_ID_CORTEX_A72 0x410fd080 247#define CPU_ID_CORTEX_A72_R1 0x411fd080 248#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0 249 250/* ARM3-specific coprocessor 15 registers */ 251#define ARM3_CP15_FLUSH 1 252#define ARM3_CP15_CONTROL 2 253#define ARM3_CP15_CACHEABLE 3 254#define ARM3_CP15_UPDATEABLE 4 255#define ARM3_CP15_DISRUPTIVE 5 256 257/* ARM3 Control register bits */ 258#define ARM3_CTL_CACHE_ON 0x00000001 259#define ARM3_CTL_SHARED 0x00000002 260#define ARM3_CTL_MONITOR 0x00000004 261 262/* 263 * Post-ARM3 CP15 registers: 264 * 265 * 1 Control register 266 * 267 * 2 Translation Table Base 268 * 269 * 3 Domain Access Control 270 * 271 * 4 Reserved 272 * 273 * 5 Fault Status 274 * 275 * 6 Fault Address 276 * 277 * 7 Cache/write-buffer Control 278 * 279 * 8 TLB Control 280 * 281 * 9 Cache Lockdown 282 * 283 * 10 TLB Lockdown 284 * 285 * 11 Reserved 286 * 287 * 12 Reserved 288 * 289 * 13 Process ID (for FCSE) 290 * 291 * 14 Reserved 292 * 293 * 15 Implementation Dependent 294 */ 295 296/* Some of the definitions below need cleaning up for V3/V4 architectures */ 297 298/* CPU control register (CP15 register 1) */ 299#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 300#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 301#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 302#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 303#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 304#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 305#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 306#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 307#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 308#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 309#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 310#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 311#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 312#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 313#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 314#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 315 316/* below were added by V6 */ 317#define CPU_CONTROL_FI (1<<21) /* FI: fast interrupts */ 318#define CPU_CONTROL_U (1<<22) /* U: Unaligned */ 319#define CPU_CONTROL_VE (1<<24) /* VE: Vector enable */ 320#define CPU_CONTROL_EE (1<<25) /* EE: Exception Endianness */ 321#define CPU_CONTROL_L2 (1<<25) /* L2: L2 cache enable */ 322 323/* added with v7 */ 324#define CPU_CONTROL_NMFI (1<<27) /* NMFI: Non Maskable fast interrupt */ 325#define CPU_CONTROL_TRE (1<<28) /* TRE: TEX Remap Enable */ 326#define CPU_CONTROL_AFE (1<<29) /* AFE: Access Flag Enable */ 327#define CPU_CONTROL_TE (1<<30) /* TE: Thumb Exception Enable */ 328 329#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 330 331/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 332#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 333#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 334#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 335#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 336#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 337#define XSCALE_AUXCTL_MD_MASK 0x00000030 338 339/* Cache type register definitions */ 340#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 341#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 342#define CPU_CT_S (1U << 24) /* split cache */ 343#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 344 345#define CPU_CT_CTYPE_WT 0 /* write-through */ 346#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 347#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 348#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 349#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 350 351#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 352#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 353#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 354#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 355 356/* Fault status register definitions */ 357 358#define FAULT_USER 0x20 359 360#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 361#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 362#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 363#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 364#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 365#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 366#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 367#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 368#define FAULT_ALIGN_0 0x01 /* Alignment */ 369#define FAULT_ALIGN_1 0x03 /* Alignment */ 370#define FAULT_TRANS_S 0x05 /* Translation -- Section */ 371#define FAULT_TRANS_P 0x07 /* Translation -- Page */ 372#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 373#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 374#define FAULT_PERM_S 0x0d /* Permission -- Section */ 375#define FAULT_PERM_P 0x0f /* Permission -- Page */ 376 377#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 378 379#define FAULT_EXT 0x00001000 /* external abort */ 380#define FAULT_WNR 0x00000800 /* write fault */ 381 382#define FAULT_TYPE(fsr) ((fsr) & 0x0f) 383#define FAULT_TYPE_V7(fsr) (((fsr) & 0x0f) | (((fsr) & 0x00000400) >> 6)) 384 385/* 386 * Address of the vector page, low and high versions. 387 */ 388#define ARM_VECTORS_LOW 0x00000000U 389#define ARM_VECTORS_HIGH 0xffff0000U 390 391/* 392 * ARM Instructions 393 * 394 * 3 3 2 2 2 395 * 1 0 9 8 7 0 396 * +-------+-------------------------------------------------------+ 397 * | cond | instruction dependant | 398 * |c c c c| | 399 * +-------+-------------------------------------------------------+ 400 */ 401 402#define INSN_SIZE 4 /* Always 4 bytes */ 403#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 404#define INSN_COND_AL 0xe0000000 /* Always condition */ 405 406#endif 407