armreg.h revision 1.26
1/* $OpenBSD: armreg.h,v 1.26 2016/03/22 11:18:17 patrick Exp $ */ 2/* $NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $ */ 3 4/* 5 * Copyright (c) 1998, 2001 Ben Harris 6 * Copyright (c) 1994-1996 Mark Brinicombe. 7 * Copyright (c) 1994 Brini. 8 * All rights reserved. 9 * 10 * This code is derived from software written for Brini by Mark Brinicombe 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by Brini. 23 * 4. The name of the company nor the name of the author may be used to 24 * endorse or promote products derived from this software without specific 25 * prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 31 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 32 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 */ 39 40#ifndef _ARM_ARMREG_H 41#define _ARM_ARMREG_H 42 43/* 44 * ARM Process Status Register 45 * 46 * The picture in early ARM manuals looks like this: 47 * 3 3 2 2 2 2 48 * 1 0 9 8 7 6 8 7 6 5 4 0 49 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 50 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| 51 * | | | | | | | | | |4 3 2 1 0| 52 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 53 * 54 * The picture in the ARMv7-A manuals looks like this: 55 * 3 3 2 2 2 2 2 2 2 2 1 1 1 1 56 * 1 0 9 8 7 6 5 4 3 0 9 6 5 0 9 8 7 6 5 4 0 57 * +-+-+-+-+-+---+-+-------+-------+-----------+-+-+-+-+-+---------+ 58 * |N|Z|C|V|Q|I I|J|reserv-|G G G G|I I I I I I|E|A|I|F|T|M M M M M| 59 * | | | | | |T T| |ed |E E E E|T T T T T T| | | | | | | 60 * | | | | | |1 0| | |3 2 1 0|7 6 5 4 3 2| | | | | |4 3 2 1 0| 61 * +-+-+-+-+-+---+-+-------+-------+-----------+-+-+-+-+-+---------+ 62 * | flags 'f' | status 's' | extension 'x' | control 'c' | 63 */ 64 65#define PSR_FLAGS 0xf0000000 /* flags */ 66#define PSR_N (1U << 31) /* negative */ 67#define PSR_Z (1 << 30) /* zero */ 68#define PSR_C (1 << 29) /* carry */ 69#define PSR_V (1 << 28) /* overflow */ 70 71#define PSR_Q (1 << 27) /* saturation */ 72 73#define PSR_A (1 << 8) /* Asynchronous abort disable */ 74#define PSR_I (1 << 7) /* IRQ disable */ 75#define PSR_F (1 << 6) /* FIQ disable */ 76 77#define PSR_T (1 << 5) /* Thumb state */ 78#define PSR_J (1 << 24) /* Java mode */ 79 80#define PSR_MODE 0x0000001f /* mode mask */ 81#define PSR_USR26_MODE 0x00000000 82#define PSR_FIQ26_MODE 0x00000001 83#define PSR_IRQ26_MODE 0x00000002 84#define PSR_SVC26_MODE 0x00000003 85#define PSR_USR32_MODE 0x00000010 86#define PSR_FIQ32_MODE 0x00000011 87#define PSR_IRQ32_MODE 0x00000012 88#define PSR_SVC32_MODE 0x00000013 89#define PSR_MON32_MODE 0x00000016 90#define PSR_ABT32_MODE 0x00000017 91#define PSR_HYP32_MODE 0x0000001a 92#define PSR_UND32_MODE 0x0000001b 93#define PSR_SYS32_MODE 0x0000001f 94#define PSR_32_MODE 0x00000010 95 96#define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ 97 98/* 99 * Co-processor 15: The system control co-processor. 100 */ 101 102#define ARM_CP15_CPU_ID 0 103 104/* 105 * The CPU ID register is theoretically structured, but the definitions of 106 * the fields keep changing. 107 */ 108 109/* The high-order byte is always the implementor */ 110#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 111#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 112#define CPU_ID_INTEL 0x69000000 /* 'i' */ 113 114#define CPU_ID_ARCH_MASK 0x000f0000 115#define CPU_ID_ARCH_V5TE 0x00050000 116#define CPU_ID_ARCH_V5TEJ 0x00060000 117#define CPU_ID_ARCH_V6 0x00070000 118#define CPU_ID_ARCH_CPUID 0x000f0000 119#define CPU_ID_VARIANT_MASK 0x00f00000 120 121/* Next three nybbles are part number */ 122#define CPU_ID_PARTNO_MASK 0x0000fff0 123 124/* Intel XScale has sub fields in part number */ 125#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 126#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 127#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 128 129/* And finally, the revision number. */ 130#define CPU_ID_REVISION_MASK 0x0000000f 131 132/* Individual CPUs are probably best IDed by everything but the revision. */ 133#define CPU_ID_CPU_MASK 0xfffffff0 134#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 135#define CPU_ID_ARM1022ES 0x4105a220 136#define CPU_ID_ARM1026EJS 0x4106a260 137#define CPU_ID_ARM1136JS 0x4107b360 138#define CPU_ID_ARM1136JSR1 0x4117b360 139#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 140#define CPU_ID_PXA210 0x69052120 141#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 142#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 143#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 144#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 145#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 146#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 147#define CPU_ID_80219_400 0x69052e20 148#define CPU_ID_80219_600 0x69052e30 149#define CPU_ID_PXA27X 0x69054110 150#define CPU_ID_80321_400 0x69052420 151#define CPU_ID_80321_600 0x69052430 152#define CPU_ID_80321_400_B0 0x69052c20 153#define CPU_ID_80321_600_B0 0x69052c30 154#define CPU_ID_CORTEX_A5 0x410fc050 155#define CPU_ID_CORTEX_A5_MASK 0xff0ffff0 156#define CPU_ID_CORTEX_A7 0x410fc070 157#define CPU_ID_CORTEX_A7_MASK 0xff0ffff0 158#define CPU_ID_CORTEX_A8_R1 0x411fc080 159#define CPU_ID_CORTEX_A8_R2 0x412fc080 160#define CPU_ID_CORTEX_A8_R3 0x413fc080 161#define CPU_ID_CORTEX_A8 0x410fc080 162#define CPU_ID_CORTEX_A8_MASK 0xff0ffff0 163#define CPU_ID_CORTEX_A9 0x410fc090 164#define CPU_ID_CORTEX_A9_R1 0x411fc090 165#define CPU_ID_CORTEX_A9_R2 0x412fc090 166#define CPU_ID_CORTEX_A9_R3 0x413fc090 167#define CPU_ID_CORTEX_A9_R4 0x414fc090 168#define CPU_ID_CORTEX_A9_MASK 0xff0ffff0 169#define CPU_ID_CORTEX_A15 0x410fc0f0 170#define CPU_ID_CORTEX_A15_R1 0x411fc0f0 171#define CPU_ID_CORTEX_A15_R2 0x412fc0f0 172#define CPU_ID_CORTEX_A15_R3 0x413fc0f0 173#define CPU_ID_CORTEX_A15_R4 0x414fc0f0 174#define CPU_ID_CORTEX_A15_MASK 0xff0ffff0 175#define CPU_ID_CORTEX_A17 0x410fc0e0 176#define CPU_ID_CORTEX_A17_R1 0x411fc0e0 177#define CPU_ID_CORTEX_A17_MASK 0xff0ffff0 178#define CPU_ID_CORTEX_A53 0x410fd030 179#define CPU_ID_CORTEX_A53_R1 0x411fd030 180#define CPU_ID_CORTEX_A53_MASK 0xff0ffff0 181#define CPU_ID_CORTEX_A57 0x410fd070 182#define CPU_ID_CORTEX_A57_R1 0x411fd070 183#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0 184#define CPU_ID_CORTEX_A72 0x410fd080 185#define CPU_ID_CORTEX_A72_R1 0x411fd080 186#define CPU_ID_CORTEX_A72_MASK 0xff0ffff0 187 188/* 189 * Post-ARM3 CP15 registers: 190 * 191 * 1 Control register 192 * 193 * 2 Translation Table Base 194 * 195 * 3 Domain Access Control 196 * 197 * 4 Reserved 198 * 199 * 5 Fault Status 200 * 201 * 6 Fault Address 202 * 203 * 7 Cache/write-buffer Control 204 * 205 * 8 TLB Control 206 * 207 * 9 Cache Lockdown 208 * 209 * 10 TLB Lockdown 210 * 211 * 11 Reserved 212 * 213 * 12 Reserved 214 * 215 * 13 Process ID (for FCSE) 216 * 217 * 14 Reserved 218 * 219 * 15 Implementation Dependent 220 */ 221 222/* Some of the definitions below need cleaning up for V3/V4 architectures */ 223 224/* CPU control register (CP15 register 1) */ 225#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 226#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 227#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 228#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 229#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 230#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 231#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 232#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 233#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 234#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 235#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 236#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 237#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 238#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 239#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 240#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 241 242/* below were added by V6 */ 243#define CPU_CONTROL_FI (1<<21) /* FI: fast interrupts */ 244#define CPU_CONTROL_U (1<<22) /* U: Unaligned */ 245#define CPU_CONTROL_VE (1<<24) /* VE: Vector enable */ 246#define CPU_CONTROL_EE (1<<25) /* EE: Exception Endianness */ 247#define CPU_CONTROL_L2 (1<<25) /* L2: L2 cache enable */ 248 249/* added with v7 */ 250#define CPU_CONTROL_NMFI (1<<27) /* NMFI: Non Maskable fast interrupt */ 251#define CPU_CONTROL_TRE (1<<28) /* TRE: TEX Remap Enable */ 252#define CPU_CONTROL_AFE (1<<29) /* AFE: Access Flag Enable */ 253#define CPU_CONTROL_TE (1<<30) /* TE: Thumb Exception Enable */ 254 255#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 256 257/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 258#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 259#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 260#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 261#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 262#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 263#define XSCALE_AUXCTL_MD_MASK 0x00000030 264 265/* Cache type register definitions */ 266#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 267#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 268#define CPU_CT_S (1U << 24) /* split cache */ 269#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 270 271#define CPU_CT_CTYPE_WT 0 /* write-through */ 272#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 273#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 274#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 275#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 276 277#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 278#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 279#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 280#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 281 282/* Fault status register definitions */ 283 284#define FAULT_USER 0x20 285 286#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 287#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 288#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 289#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 290#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 291#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 292#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 293#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 294#define FAULT_ALIGN_0 0x01 /* Alignment */ 295#define FAULT_ALIGN_1 0x03 /* Alignment */ 296#define FAULT_TRANS_S 0x05 /* Translation -- Section */ 297#define FAULT_TRANS_P 0x07 /* Translation -- Page */ 298#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 299#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 300#define FAULT_PERM_S 0x0d /* Permission -- Section */ 301#define FAULT_PERM_P 0x0f /* Permission -- Page */ 302 303#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 304 305#define FAULT_EXT 0x00001000 /* external abort */ 306#define FAULT_WNR 0x00000800 /* write fault */ 307 308#define FAULT_TYPE(fsr) ((fsr) & 0x0f) 309#define FAULT_TYPE_V7(fsr) (((fsr) & 0x0f) | (((fsr) & 0x00000400) >> 6)) 310 311/* 312 * Address of the vector page, low and high versions. 313 */ 314#define ARM_VECTORS_LOW 0x00000000U 315#define ARM_VECTORS_HIGH 0xffff0000U 316 317/* 318 * ARM Instructions 319 * 320 * 3 3 2 2 2 321 * 1 0 9 8 7 0 322 * +-------+-------------------------------------------------------+ 323 * | cond | instruction dependant | 324 * |c c c c| | 325 * +-------+-------------------------------------------------------+ 326 */ 327 328#define INSN_SIZE 4 /* Always 4 bytes */ 329#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 330#define INSN_COND_AL 0xe0000000 /* Always condition */ 331 332#endif 333