armreg.h revision 1.15
1/* $OpenBSD: armreg.h,v 1.15 2015/01/17 08:00:41 jsg Exp $ */ 2/* $NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $ */ 3 4/* 5 * Copyright (c) 1998, 2001 Ben Harris 6 * Copyright (c) 1994-1996 Mark Brinicombe. 7 * Copyright (c) 1994 Brini. 8 * All rights reserved. 9 * 10 * This code is derived from software written for Brini by Mark Brinicombe 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by Brini. 23 * 4. The name of the company nor the name of the author may be used to 24 * endorse or promote products derived from this software without specific 25 * prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 31 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 32 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 */ 39 40#ifndef _ARM_ARMREG_H 41#define _ARM_ARMREG_H 42 43/* 44 * ARM Process Status Register 45 * 46 * The picture in early ARM manuals looks like this: 47 * 3 3 2 2 2 2 48 * 1 0 9 8 7 6 8 7 6 5 4 0 49 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 50 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| 51 * | | | | | | | | | |4 3 2 1 0| 52 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 53 * 54 * The picture in the ARMv7-A manuals looks like this: 55 * 3 3 2 2 2 2 2 2 2 2 1 1 1 1 56 * 1 0 9 8 7 6 5 4 3 0 9 6 5 0 9 8 7 6 5 4 0 57 * +-+-+-+-+-+---+-+-------+-------+-----------+-+-+-+-+-+---------+ 58 * |N|Z|C|V|Q|I I|J|reserv-|G G G G|I I I I I I|E|A|I|F|T|M M M M M| 59 * | | | | | |T T| |ed |E E E E|T T T T T T| | | | | | | 60 * | | | | | |1 0| | |3 2 1 0|7 6 5 4 3 2| | | | | |4 3 2 1 0| 61 * +-+-+-+-+-+---+-+-------+-------+-----------+-+-+-+-+-+---------+ 62 * | flags 'f' | status 's' | extension 'x' | control 'c' | 63 */ 64 65#define PSR_FLAGS 0xf0000000 /* flags */ 66#define PSR_N_bit (1U << 31) /* negative */ 67#define PSR_Z_bit (1 << 30) /* zero */ 68#define PSR_C_bit (1 << 29) /* carry */ 69#define PSR_V_bit (1 << 28) /* overflow */ 70 71#define PSR_Q_bit (1 << 27) /* saturation */ 72 73#define I32_bit (1 << 7) /* IRQ disable */ 74#define F32_bit (1 << 6) /* FIQ disable */ 75 76#define PSR_T_bit (1 << 5) /* Thumb state */ 77#define PSR_J_bit (1 << 24) /* Java mode */ 78 79#define PSR_MODE 0x0000001f /* mode mask */ 80#define PSR_USR26_MODE 0x00000000 81#define PSR_FIQ26_MODE 0x00000001 82#define PSR_IRQ26_MODE 0x00000002 83#define PSR_SVC26_MODE 0x00000003 84#define PSR_USR32_MODE 0x00000010 85#define PSR_FIQ32_MODE 0x00000011 86#define PSR_IRQ32_MODE 0x00000012 87#define PSR_SVC32_MODE 0x00000013 88#define PSR_ABT32_MODE 0x00000017 89#define PSR_UND32_MODE 0x0000001b 90#define PSR_SYS32_MODE 0x0000001f 91#define PSR_32_MODE 0x00000010 92 93#define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ 94 95/* 96 * Co-processor 15: The system control co-processor. 97 */ 98 99#define ARM_CP15_CPU_ID 0 100 101/* 102 * The CPU ID register is theoretically structured, but the definitions of 103 * the fields keep changing. 104 */ 105 106/* The high-order byte is always the implementor */ 107#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 108#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 109#define CPU_ID_DEC 0x44000000 /* 'D' */ 110#define CPU_ID_INTEL 0x69000000 /* 'i' */ 111#define CPU_ID_TI 0x54000000 /* 'T' */ 112 113/* How to decide what format the CPUID is in. */ 114#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 115#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 116#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 117 118/* On ARM3 and ARM6, this byte holds the foundry ID. */ 119#define CPU_ID_FOUNDRY_MASK 0x00ff0000 120#define CPU_ID_FOUNDRY_VLSI 0x00560000 121 122/* On ARM7 it holds the architecture and variant (sub-model) */ 123#define CPU_ID_7ARCH_MASK 0x00800000 124#define CPU_ID_7ARCH_V3 0x00000000 125#define CPU_ID_7ARCH_V4T 0x00800000 126#define CPU_ID_7VARIANT_MASK 0x007f0000 127 128/* On more recent ARMs, it does the same, but in a different format */ 129#define CPU_ID_ARCH_MASK 0x000f0000 130#define CPU_ID_ARCH_V3 0x00000000 131#define CPU_ID_ARCH_V4 0x00010000 132#define CPU_ID_ARCH_V4T 0x00020000 133#define CPU_ID_ARCH_V5 0x00030000 134#define CPU_ID_ARCH_V5T 0x00040000 135#define CPU_ID_ARCH_V5TE 0x00050000 136#define CPU_ID_ARCH_V6 0x00070000 137#define CPU_ID_ARCH_V7 0x00080000 138#define CPU_ID_VARIANT_MASK 0x00f00000 139 140/* Next three nybbles are part number */ 141#define CPU_ID_PARTNO_MASK 0x0000fff0 142 143/* Intel XScale has sub fields in part number */ 144#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 145#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 146#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 147 148/* And finally, the revision number. */ 149#define CPU_ID_REVISION_MASK 0x0000000f 150 151/* Individual CPUs are probably best IDed by everything but the revision. */ 152#define CPU_ID_CPU_MASK 0xfffffff0 153 154/* Fake CPU IDs for ARMs without CP15 */ 155#define CPU_ID_ARM2 0x41560200 156#define CPU_ID_ARM250 0x41560250 157 158/* Pre-ARM7 CPUs -- [15:12] == 0 */ 159#define CPU_ID_ARM3 0x41560300 160#define CPU_ID_ARM600 0x41560600 161#define CPU_ID_ARM610 0x41560610 162#define CPU_ID_ARM620 0x41560620 163 164/* ARM7 CPUs -- [15:12] == 7 */ 165#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 166#define CPU_ID_ARM710 0x41007100 167#define CPU_ID_ARM7500 0x41027100 /* XXX This is a guess. */ 168#define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ 169#define CPU_ID_ARM7500FE 0x41077100 170#define CPU_ID_ARM710T 0x41807100 171#define CPU_ID_ARM720T 0x41807200 172#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 173#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 174 175/* Post-ARM7 CPUs */ 176#define CPU_ID_ARM810 0x41018100 177#define CPU_ID_ARM920T 0x41129200 178#define CPU_ID_ARM922T 0x41029220 179#define CPU_ID_ARM926EJS 0x41069260 180#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 181#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 182#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 183#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 184#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 185#define CPU_ID_ARM1022ES 0x4105a220 186#define CPU_ID_ARM1026EJS 0x4106a260 187#define CPU_ID_ARM1136JS 0x4107b360 188#define CPU_ID_ARM1136JSR1 0x4117b360 189#define CPU_ID_SA110 0x4401a100 190#define CPU_ID_SA1100 0x4401a110 191#define CPU_ID_TI925T 0x54029250 192#define CPU_ID_SA1110 0x6901b110 193#define CPU_ID_IXP1200 0x6901c120 194#define CPU_ID_80200 0x69052000 195#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 196#define CPU_ID_PXA210 0x69052120 197#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 198#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 199#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 200#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 201#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 202#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 203#define CPU_ID_80219_400 0x69052e20 204#define CPU_ID_80219_600 0x69052e30 205#define CPU_ID_PXA27X 0x69054110 206#define CPU_ID_80321_400 0x69052420 207#define CPU_ID_80321_600 0x69052430 208#define CPU_ID_80321_400_B0 0x69052c20 209#define CPU_ID_80321_600_B0 0x69052c30 210#define CPU_ID_IXP425_533 0x690541c0 211#define CPU_ID_IXP425_400 0x690541d0 212#define CPU_ID_IXP425_266 0x690541f0 213#define CPU_ID_CORTEX_A5 0x410fc050 214#define CPU_ID_CORTEX_A5_MASK 0xff0ffff0 215#define CPU_ID_CORTEX_A7 0x410fc070 216#define CPU_ID_CORTEX_A7_MASK 0xff0ffff0 217#define CPU_ID_CORTEX_A8_R1 0x411fc080 218#define CPU_ID_CORTEX_A8_R2 0x412fc080 219#define CPU_ID_CORTEX_A8_R3 0x413fc080 220#define CPU_ID_CORTEX_A8 0x410fc080 221#define CPU_ID_CORTEX_A8_MASK 0xff0ffff0 222#define CPU_ID_CORTEX_A9 0x410fc090 223#define CPU_ID_CORTEX_A9_R1 0x411fc090 224#define CPU_ID_CORTEX_A9_R2 0x412fc090 225#define CPU_ID_CORTEX_A9_R3 0x413fc090 226#define CPU_ID_CORTEX_A9_R4 0x414fc090 227#define CPU_ID_CORTEX_A9_MASK 0xff0ffff0 228#define CPU_ID_CORTEX_A15 0x410fc0f0 229#define CPU_ID_CORTEX_A15_R1 0x411fc0f0 230#define CPU_ID_CORTEX_A15_R2 0x412fc0f0 231#define CPU_ID_CORTEX_A15_R3 0x413fc0f0 232#define CPU_ID_CORTEX_A15_R4 0x414fc0f0 233#define CPU_ID_CORTEX_A15_MASK 0xff0ffff0 234 235 236/* ARM3-specific coprocessor 15 registers */ 237#define ARM3_CP15_FLUSH 1 238#define ARM3_CP15_CONTROL 2 239#define ARM3_CP15_CACHEABLE 3 240#define ARM3_CP15_UPDATEABLE 4 241#define ARM3_CP15_DISRUPTIVE 5 242 243/* ARM3 Control register bits */ 244#define ARM3_CTL_CACHE_ON 0x00000001 245#define ARM3_CTL_SHARED 0x00000002 246#define ARM3_CTL_MONITOR 0x00000004 247 248/* 249 * Post-ARM3 CP15 registers: 250 * 251 * 1 Control register 252 * 253 * 2 Translation Table Base 254 * 255 * 3 Domain Access Control 256 * 257 * 4 Reserved 258 * 259 * 5 Fault Status 260 * 261 * 6 Fault Address 262 * 263 * 7 Cache/write-buffer Control 264 * 265 * 8 TLB Control 266 * 267 * 9 Cache Lockdown 268 * 269 * 10 TLB Lockdown 270 * 271 * 11 Reserved 272 * 273 * 12 Reserved 274 * 275 * 13 Process ID (for FCSE) 276 * 277 * 14 Reserved 278 * 279 * 15 Implementation Dependent 280 */ 281 282/* Some of the definitions below need cleaning up for V3/V4 architectures */ 283 284/* CPU control register (CP15 register 1) */ 285#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 286#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 287#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 288#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 289#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 290#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 291#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 292#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 293#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 294#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 295#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 296#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 297#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 298#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 299#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 300#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 301 302/* below were added by V6 */ 303#define CPU_CONTROL_FI (1<<21) /* FI: fast interrupts */ 304#define CPU_CONTROL_U (1<<22) /* U: Unaligned */ 305#define CPU_CONTROL_VE (1<<24) /* VE: Vector enable */ 306#define CPU_CONTROL_EE (1<<25) /* EE: Exception Endianness */ 307#define CPU_CONTROL_L2 (1<<25) /* L2: L2 cache enable */ 308 309/* added with v7 */ 310#define CPU_CONTROL_NMFI (1<<27) /* NMFI: Non Maskable fast interrupt */ 311#define CPU_CONTROL_TRE (1<<28) /* TRE: TEX Remap Enable */ 312#define CPU_CONTROL_AFE (1<<29) /* AFE: Access Flag Enable */ 313#define CPU_CONTROL_TE (1<<30) /* TE: Thumb Exception Enable */ 314 315#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 316 317/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 318#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 319#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 320#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 321#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 322#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 323#define XSCALE_AUXCTL_MD_MASK 0x00000030 324 325/* Cache type register definitions */ 326#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 327#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 328#define CPU_CT_S (1U << 24) /* split cache */ 329#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 330 331#define CPU_CT_CTYPE_WT 0 /* write-through */ 332#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 333#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 334#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 335#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 336 337#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 338#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 339#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 340#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 341 342/* Fault status register definitions */ 343 344#define FAULT_USER 0x20 345 346#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 347#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 348#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 349#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 350#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 351#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 352#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 353#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 354#define FAULT_ALIGN_0 0x01 /* Alignment */ 355#define FAULT_ALIGN_1 0x03 /* Alignment */ 356#define FAULT_TRANS_S 0x05 /* Translation -- Section */ 357#define FAULT_TRANS_P 0x07 /* Translation -- Page */ 358#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 359#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 360#define FAULT_PERM_S 0x0d /* Permission -- Section */ 361#define FAULT_PERM_P 0x0f /* Permission -- Page */ 362 363#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 364 365#define FAULT_EXT 0x00001000 /* external abort */ 366#define FAULT_WNR 0x00000800 /* write fault */ 367 368#define FAULT_TYPE(fsr) ((fsr) & 0x0f) 369#define FAULT_TYPE_V7(fsr) (((fsr) & 0x0f) | (((fsr) & 0x00000400) >> 6)) 370 371/* 372 * Address of the vector page, low and high versions. 373 */ 374#define ARM_VECTORS_LOW 0x00000000U 375#define ARM_VECTORS_HIGH 0xffff0000U 376 377/* 378 * ARM Instructions 379 * 380 * 3 3 2 2 2 381 * 1 0 9 8 7 0 382 * +-------+-------------------------------------------------------+ 383 * | cond | instruction dependant | 384 * |c c c c| | 385 * +-------+-------------------------------------------------------+ 386 */ 387 388#define INSN_SIZE 4 /* Always 4 bytes */ 389#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 390#define INSN_COND_AL 0xe0000000 /* Always condition */ 391 392#endif 393