Print TLB message consistently to improve readability.

Example:
cpu0: L2 cache: 256KB 64B/line 4-way
cpu0: L3 cache: 4MB 64B/line 16-way
cpu0: 64B prefetching
-cpu0: ITLB: 64 4KB entries 8-way, 2M/4M: 8 entries
+cpu0: ITLB: 64 4KB entries 8-way, 8 2M/4M entries
cpu0: DTLB: 64 4KB entries 4-way, 4 1GB entries 4-way
cpu0: L2 STLB: 1536 4KB entries 6-way
cpu0: Initial APIC ID 0

Move some common functions into x86/identcpu_subr.c. No functional change.

Add Load Only TLB and Store Only TLB.

- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
Intel Deterministic Cache Parameter Leaf(0x04), so make new
cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?

It seems that AMD zen2's CPUID 0x80000006 leaf's spec has changed.
The EDX register's acsociativity field has 9. In the latest available document,
it's a reserved value. I have no access to zen2's document, but many websites
say that the acsociativity is 16. Add it.

branches: 1.26.2;
AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.

Add 3way and 6way of L2 cache or TLB on AMD CPU.

Add yet another Shared L2 TLB (2M/4M pages).

XXX need redesign.

branches: 1.23.2;
Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.

branches: 1.22.10;
Add new desc 0x64 and 0xc4.

Index 0x6c is not 126 entries but 128 entries. The old value was from
previous SDM.

Add some TLB entries from the latest Intel SDM. This change might be incorrect
because the document itself is very strange.

branches: 1.19.2;
Add new cache descriptor (0xc3) from the latest Intel SDM.

branches: 1.18.2;
Fix some entries:
- Desc 0x55 and 0xb1 are Instruction TLB but not fixed to 4K.
- Desc 0x5a and 0xc0 are Data TLB but not fixed to 4K.
- Desc 0x57 and 0x59 are 4K fixed DTLB.
- Fix string of desc 0xc2 and it's not fixed to 4K.
- Desc 0xca is 4K fixed L2 shared TLB.
- Add desc 0xa0.

BUG: A lot of CPUs have multiple CAI_DTLB and/or CAI_DTLB2 entries. Currently
TLB info is indexed in ci_cinfo[CAI_COUNT], so some info is overwritten.

Nowadays CPUs have very complexed TLBs. It's hard to manage with CAI_* index.
We should think to separate TLB info structure from ci_cinfo[CAI_COUNT]
in struct cpu_info.

branches: 1.17.2;
Support prefetch size.

Add Shared L2 TLB and some cache and tlb entries from the latest document.

Add some new TLB and cache entries from document (Table 3-22 Encoding of CPUID
Leaf 2 Descriptors, Intel 64 and IA-32 Architectures Software Developer's
Manual Vol. 2A.)

Fix 0x0d's DCACHE entry and 0xeb's L3CACHE entry from the document
(Table 3-22 Encoding of CPUID Leaf 2 Descriptors, Intel 64 and IA-32
Architectures Software Developer's Manual Vol. 2A.)

branches: 1.13.2; 1.13.6; 1.13.10;
add info on L2 TLBs and 1GB pages.

branches: 1.12.12; 1.12.16;
Fix toyp in previous. Pointed out by snj@

1. Extend CPU probe of Intel processors to handle extended-models. This
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.

2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.

3. Convert decode of the various features masks to use the newly added
snprintb_m(3) routine.

Addresses my PR bin/41289
Addresses my PR bin/41290

Constify a userland-only member.

branches: 1.9.6; 1.9.8; 1.9.12; 1.9.16;
don't undef __CI_TBL before we use it :-)

- fix an amd cache entry.
- merge tables
- support phenom
from Paul Goyette

PR/38722: Paul Goyette: Share cacheinfo information

print L3 and TLB cache information for AMD Barcelona/Phenom

Simplify x86 identcpu code, and share between i386/amd64.

branches: 1.4.82; 1.4.84; 1.4.86; 1.4.88;
make multi inclusion protection macros consistent.

branches: 1.3.4; 1.3.10;
Get correct cache information for earlier VIA C3 models.
Mostly from PR kern/26689 submitted by Michael van Elst.

VIA C3 cache info.

branches: 1.1.2; 1.1.4;
Share some common cache info cpuid code between i386 and x86_64.

Move some common functions into x86/identcpu_subr.c. No functional change.

Add Load Only TLB and Store Only TLB.

- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
Intel Deterministic Cache Parameter Leaf(0x04), so make new
cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?

It seems that AMD zen2's CPUID 0x80000006 leaf's spec has changed.
The EDX register's acsociativity field has 9. In the latest available document,
it's a reserved value. I have no access to zen2's document, but many websites
say that the acsociativity is 16. Add it.

branches: 1.26.2;
AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.

Add 3way and 6way of L2 cache or TLB on AMD CPU.

Add yet another Shared L2 TLB (2M/4M pages).

XXX need redesign.

branches: 1.23.2;
Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.

branches: 1.22.10;
Add new desc 0x64 and 0xc4.

Index 0x6c is not 126 entries but 128 entries. The old value was from
previous SDM.

Add some TLB entries from the latest Intel SDM. This change might be incorrect
because the document itself is very strange.

branches: 1.19.2;
Add new cache descriptor (0xc3) from the latest Intel SDM.

branches: 1.18.2;
Fix some entries:
- Desc 0x55 and 0xb1 are Instruction TLB but not fixed to 4K.
- Desc 0x5a and 0xc0 are Data TLB but not fixed to 4K.
- Desc 0x57 and 0x59 are 4K fixed DTLB.
- Fix string of desc 0xc2 and it's not fixed to 4K.
- Desc 0xca is 4K fixed L2 shared TLB.
- Add desc 0xa0.

BUG: A lot of CPUs have multiple CAI_DTLB and/or CAI_DTLB2 entries. Currently
TLB info is indexed in ci_cinfo[CAI_COUNT], so some info is overwritten.

Nowadays CPUs have very complexed TLBs. It's hard to manage with CAI_* index.
We should think to separate TLB info structure from ci_cinfo[CAI_COUNT]
in struct cpu_info.

branches: 1.17.2;
Support prefetch size.

Add Shared L2 TLB and some cache and tlb entries from the latest document.

Add some new TLB and cache entries from document (Table 3-22 Encoding of CPUID
Leaf 2 Descriptors, Intel 64 and IA-32 Architectures Software Developer's
Manual Vol. 2A.)

Fix 0x0d's DCACHE entry and 0xeb's L3CACHE entry from the document
(Table 3-22 Encoding of CPUID Leaf 2 Descriptors, Intel 64 and IA-32
Architectures Software Developer's Manual Vol. 2A.)

branches: 1.13.2; 1.13.6; 1.13.10;
add info on L2 TLBs and 1GB pages.

branches: 1.12.12; 1.12.16;
Fix toyp in previous. Pointed out by snj@

1. Extend CPU probe of Intel processors to handle extended-models. This
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.

2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.

3. Convert decode of the various features masks to use the newly added
snprintb_m(3) routine.

Addresses my PR bin/41289
Addresses my PR bin/41290

Constify a userland-only member.

branches: 1.9.6; 1.9.8; 1.9.12; 1.9.16;
don't undef __CI_TBL before we use it :-)

- fix an amd cache entry.
- merge tables
- support phenom
from Paul Goyette

PR/38722: Paul Goyette: Share cacheinfo information

print L3 and TLB cache information for AMD Barcelona/Phenom

Simplify x86 identcpu code, and share between i386/amd64.

branches: 1.4.82; 1.4.84; 1.4.86; 1.4.88;
make multi inclusion protection macros consistent.

branches: 1.3.4; 1.3.10;
Get correct cache information for earlier VIA C3 models.
Mostly from PR kern/26689 submitted by Michael van Elst.

VIA C3 cache info.

branches: 1.1.2; 1.1.4;
Share some common cache info cpuid code between i386 and x86_64.

Add Load Only TLB and Store Only TLB.

- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
Intel Deterministic Cache Parameter Leaf(0x04), so make new
cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?

It seems that AMD zen2's CPUID 0x80000006 leaf's spec has changed.
The EDX register's acsociativity field has 9. In the latest available document,
it's a reserved value. I have no access to zen2's document, but many websites
say that the acsociativity is 16. Add it.

branches: 1.26.2;
AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.

Add 3way and 6way of L2 cache or TLB on AMD CPU.

Add yet another Shared L2 TLB (2M/4M pages).

XXX need redesign.

branches: 1.23.2;
Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.

branches: 1.22.10;
Add new desc 0x64 and 0xc4.

Index 0x6c is not 126 entries but 128 entries. The old value was from
previous SDM.

Add some TLB entries from the latest Intel SDM. This change might be incorrect
because the document itself is very strange.

branches: 1.19.2;
Add new cache descriptor (0xc3) from the latest Intel SDM.

branches: 1.18.2;
Fix some entries:
- Desc 0x55 and 0xb1 are Instruction TLB but not fixed to 4K.
- Desc 0x5a and 0xc0 are Data TLB but not fixed to 4K.
- Desc 0x57 and 0x59 are 4K fixed DTLB.
- Fix string of desc 0xc2 and it's not fixed to 4K.
- Desc 0xca is 4K fixed L2 shared TLB.
- Add desc 0xa0.

BUG: A lot of CPUs have multiple CAI_DTLB and/or CAI_DTLB2 entries. Currently
TLB info is indexed in ci_cinfo[CAI_COUNT], so some info is overwritten.

Nowadays CPUs have very complexed TLBs. It's hard to manage with CAI_* index.
We should think to separate TLB info structure from ci_cinfo[CAI_COUNT]
in struct cpu_info.

branches: 1.17.2;
Support prefetch size.

Add Shared L2 TLB and some cache and tlb entries from the latest document.

Add some new TLB and cache entries from document (Table 3-22 Encoding of CPUID
Leaf 2 Descriptors, Intel 64 and IA-32 Architectures Software Developer's
Manual Vol. 2A.)

Fix 0x0d's DCACHE entry and 0xeb's L3CACHE entry from the document
(Table 3-22 Encoding of CPUID Leaf 2 Descriptors, Intel 64 and IA-32
Architectures Software Developer's Manual Vol. 2A.)

branches: 1.13.2; 1.13.6; 1.13.10;
add info on L2 TLBs and 1GB pages.

branches: 1.12.12; 1.12.16;
Fix toyp in previous. Pointed out by snj@

1. Extend CPU probe of Intel processors to handle extended-models. This
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.

2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.

3. Convert decode of the various features masks to use the newly added
snprintb_m(3) routine.

Addresses my PR bin/41289
Addresses my PR bin/41290

Constify a userland-only member.

branches: 1.9.6; 1.9.8; 1.9.12; 1.9.16;
don't undef __CI_TBL before we use it :-)

- fix an amd cache entry.
- merge tables
- support phenom
from Paul Goyette

PR/38722: Paul Goyette: Share cacheinfo information

print L3 and TLB cache information for AMD Barcelona/Phenom

Simplify x86 identcpu code, and share between i386/amd64.

branches: 1.4.82; 1.4.84; 1.4.86; 1.4.88;
make multi inclusion protection macros consistent.

branches: 1.3.4; 1.3.10;
Get correct cache information for earlier VIA C3 models.
Mostly from PR kern/26689 submitted by Michael van Elst.

VIA C3 cache info.

branches: 1.1.2; 1.1.4;
Share some common cache info cpuid code between i386 and x86_64.

- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
Intel Deterministic Cache Parameter Leaf(0x04), so make new
cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?

It seems that AMD zen2's CPUID 0x80000006 leaf's spec has changed.
The EDX register's acsociativity field has 9. In the latest available document,
it's a reserved value. I have no access to zen2's document, but many websites
say that the acsociativity is 16. Add it.

AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.

Add 3way and 6way of L2 cache or TLB on AMD CPU.

Add yet another Shared L2 TLB (2M/4M pages).

XXX need redesign.

branches: 1.23.2;
Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.

branches: 1.22.10;
Add new desc 0x64 and 0xc4.

Index 0x6c is not 126 entries but 128 entries. The old value was from
previous SDM.

Add some TLB entries from the latest Intel SDM. This change might be incorrect
because the document itself is very strange.

branches: 1.19.2;
Add new cache descriptor (0xc3) from the latest Intel SDM.

branches: 1.18.2;
Fix some entries:
- Desc 0x55 and 0xb1 are Instruction TLB but not fixed to 4K.
- Desc 0x5a and 0xc0 are Data TLB but not fixed to 4K.
- Desc 0x57 and 0x59 are 4K fixed DTLB.
- Fix string of desc 0xc2 and it's not fixed to 4K.
- Desc 0xca is 4K fixed L2 shared TLB.
- Add desc 0xa0.

BUG: A lot of CPUs have multiple CAI_DTLB and/or CAI_DTLB2 entries. Currently
TLB info is indexed in ci_cinfo[CAI_COUNT], so some info is overwritten.

Nowadays CPUs have very complexed TLBs. It's hard to manage with CAI_* index.
We should think to separate TLB info structure from ci_cinfo[CAI_COUNT]
in struct cpu_info.

branches: 1.17.2;
Support prefetch size.

Add Shared L2 TLB and some cache and tlb entries from the latest document.

Add some new TLB and cache entries from document (Table 3-22 Encoding of CPUID
Leaf 2 Descriptors, Intel 64 and IA-32 Architectures Software Developer's
Manual Vol. 2A.)

Fix 0x0d's DCACHE entry and 0xeb's L3CACHE entry from the document
(Table 3-22 Encoding of CPUID Leaf 2 Descriptors, Intel 64 and IA-32
Architectures Software Developer's Manual Vol. 2A.)

branches: 1.13.2; 1.13.6; 1.13.10;
add info on L2 TLBs and 1GB pages.

branches: 1.12.12; 1.12.16;
Fix toyp in previous. Pointed out by snj@

1. Extend CPU probe of Intel processors to handle extended-models. This
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.

2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.

3. Convert decode of the various features masks to use the newly added
snprintb_m(3) routine.

Addresses my PR bin/41289
Addresses my PR bin/41290

Constify a userland-only member.

branches: 1.9.6; 1.9.8; 1.9.12; 1.9.16;
don't undef __CI_TBL before we use it :-)

- fix an amd cache entry.
- merge tables
- support phenom
from Paul Goyette

PR/38722: Paul Goyette: Share cacheinfo information

print L3 and TLB cache information for AMD Barcelona/Phenom

Simplify x86 identcpu code, and share between i386/amd64.

branches: 1.4.82; 1.4.84; 1.4.86; 1.4.88;
make multi inclusion protection macros consistent.

branches: 1.3.4; 1.3.10;
Get correct cache information for earlier VIA C3 models.
Mostly from PR kern/26689 submitted by Michael van Elst.

VIA C3 cache info.

branches: 1.1.2; 1.1.4;
Share some common cache info cpuid code between i386 and x86_64.

It seems that AMD zen2's CPUID 0x80000006 leaf's spec has changed.
The EDX register's acsociativity field has 9. In the latest available document,
it's a reserved value. I have no access to zen2's document, but many websites
say that the acsociativity is 16. Add it.

AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.

Add 3way and 6way of L2 cache or TLB on AMD CPU.

Add yet another Shared L2 TLB (2M/4M pages).

XXX need redesign.

branches: 1.23.2;
Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.

branches: 1.22.10;
Add new desc 0x64 and 0xc4.

Index 0x6c is not 126 entries but 128 entries. The old value was from
previous SDM.

Add some TLB entries from the latest Intel SDM. This change might be incorrect
because the document itself is very strange.

branches: 1.19.2;
Add new cache descriptor (0xc3) from the latest Intel SDM.

branches: 1.18.2;
Fix some entries:
- Desc 0x55 and 0xb1 are Instruction TLB but not fixed to 4K.
- Desc 0x5a and 0xc0 are Data TLB but not fixed to 4K.
- Desc 0x57 and 0x59 are 4K fixed DTLB.
- Fix string of desc 0xc2 and it's not fixed to 4K.
- Desc 0xca is 4K fixed L2 shared TLB.
- Add desc 0xa0.

BUG: A lot of CPUs have multiple CAI_DTLB and/or CAI_DTLB2 entries. Currently
TLB info is indexed in ci_cinfo[CAI_COUNT], so some info is overwritten.

Nowadays CPUs have very complexed TLBs. It's hard to manage with CAI_* index.
We should think to separate TLB info structure from ci_cinfo[CAI_COUNT]
in struct cpu_info.

branches: 1.17.2;
Support prefetch size.

Add Shared L2 TLB and some cache and tlb entries from the latest document.

Add some new TLB and cache entries from document (Table 3-22 Encoding of CPUID
Leaf 2 Descriptors, Intel 64 and IA-32 Architectures Software Developer's
Manual Vol. 2A.)

Fix 0x0d's DCACHE entry and 0xeb's L3CACHE entry from the document
(Table 3-22 Encoding of CPUID Leaf 2 Descriptors, Intel 64 and IA-32
Architectures Software Developer's Manual Vol. 2A.)

branches: 1.13.2; 1.13.6; 1.13.10;
add info on L2 TLBs and 1GB pages.

branches: 1.12.12; 1.12.16;
Fix toyp in previous. Pointed out by snj@

1. Extend CPU probe of Intel processors to handle extended-models. This
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.

2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.

3. Convert decode of the various features masks to use the newly added
snprintb_m(3) routine.

Addresses my PR bin/41289
Addresses my PR bin/41290

Constify a userland-only member.

branches: 1.9.6; 1.9.8; 1.9.12; 1.9.16;
don't undef __CI_TBL before we use it :-)

- fix an amd cache entry.
- merge tables
- support phenom
from Paul Goyette

PR/38722: Paul Goyette: Share cacheinfo information

print L3 and TLB cache information for AMD Barcelona/Phenom

Simplify x86 identcpu code, and share between i386/amd64.

branches: 1.4.82; 1.4.84; 1.4.86; 1.4.88;
make multi inclusion protection macros consistent.

branches: 1.3.4; 1.3.10;
Get correct cache information for earlier VIA C3 models.
Mostly from PR kern/26689 submitted by Michael van Elst.

VIA C3 cache info.

branches: 1.1.2; 1.1.4;
Share some common cache info cpuid code between i386 and x86_64.

AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.

Add 3way and 6way of L2 cache or TLB on AMD CPU.

Add yet another Shared L2 TLB (2M/4M pages).

XXX need redesign.

branches: 1.23.2;
Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.

branches: 1.22.10;
Add new desc 0x64 and 0xc4.

Index 0x6c is not 126 entries but 128 entries. The old value was from
previous SDM.

Add some TLB entries from the latest Intel SDM. This change might be incorrect
because the document itself is very strange.

branches: 1.19.2;
Add new cache descriptor (0xc3) from the latest Intel SDM.

branches: 1.18.2;
Fix some entries:
- Desc 0x55 and 0xb1 are Instruction TLB but not fixed to 4K.
- Desc 0x5a and 0xc0 are Data TLB but not fixed to 4K.
- Desc 0x57 and 0x59 are 4K fixed DTLB.
- Fix string of desc 0xc2 and it's not fixed to 4K.
- Desc 0xca is 4K fixed L2 shared TLB.
- Add desc 0xa0.

BUG: A lot of CPUs have multiple CAI_DTLB and/or CAI_DTLB2 entries. Currently
TLB info is indexed in ci_cinfo[CAI_COUNT], so some info is overwritten.

Nowadays CPUs have very complexed TLBs. It's hard to manage with CAI_* index.
We should think to separate TLB info structure from ci_cinfo[CAI_COUNT]
in struct cpu_info.

branches: 1.17.2;
Support prefetch size.

Add Shared L2 TLB and some cache and tlb entries from the latest document.

Add some new TLB and cache entries from document (Table 3-22 Encoding of CPUID
Leaf 2 Descriptors, Intel 64 and IA-32 Architectures Software Developer's
Manual Vol. 2A.)

Fix 0x0d's DCACHE entry and 0xeb's L3CACHE entry from the document
(Table 3-22 Encoding of CPUID Leaf 2 Descriptors, Intel 64 and IA-32
Architectures Software Developer's Manual Vol. 2A.)

branches: 1.13.2; 1.13.6; 1.13.10;
add info on L2 TLBs and 1GB pages.

branches: 1.12.12; 1.12.16;
Fix toyp in previous. Pointed out by snj@

1. Extend CPU probe of Intel processors to handle extended-models. This
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.

2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.

3. Convert decode of the various features masks to use the newly added
snprintb_m(3) routine.

Addresses my PR bin/41289
Addresses my PR bin/41290

Constify a userland-only member.

branches: 1.9.6; 1.9.8; 1.9.12; 1.9.16;
don't undef __CI_TBL before we use it :-)

- fix an amd cache entry.
- merge tables
- support phenom
from Paul Goyette

PR/38722: Paul Goyette: Share cacheinfo information

print L3 and TLB cache information for AMD Barcelona/Phenom

Simplify x86 identcpu code, and share between i386/amd64.

branches: 1.4.82; 1.4.84; 1.4.86; 1.4.88;
make multi inclusion protection macros consistent.

branches: 1.3.4; 1.3.10;
Get correct cache information for earlier VIA C3 models.
Mostly from PR kern/26689 submitted by Michael van Elst.

VIA C3 cache info.

branches: 1.1.2; 1.1.4;
Share some common cache info cpuid code between i386 and x86_64.

Add new desc 0x64 and 0xc4.

Index 0x6c is not 126 entries but 128 entries. The old value was from
previous SDM.

Add some TLB entries from the latest Intel SDM. This change might be incorrect
because the document itself is very strange.

branches: 1.19.2;
Add new cache descriptor (0xc3) from the latest Intel SDM.

branches: 1.18.2;
Fix some entries:
- Desc 0x55 and 0xb1 are Instruction TLB but not fixed to 4K.
- Desc 0x5a and 0xc0 are Data TLB but not fixed to 4K.
- Desc 0x57 and 0x59 are 4K fixed DTLB.
- Fix string of desc 0xc2 and it's not fixed to 4K.
- Desc 0xca is 4K fixed L2 shared TLB.
- Add desc 0xa0.

BUG: A lot of CPUs have multiple CAI_DTLB and/or CAI_DTLB2 entries. Currently
TLB info is indexed in ci_cinfo[CAI_COUNT], so some info is overwritten.

Nowadays CPUs have very complexed TLBs. It's hard to manage with CAI_* index.
We should think to separate TLB info structure from ci_cinfo[CAI_COUNT]
in struct cpu_info.

branches: 1.17.2;
Support prefetch size.

Add Shared L2 TLB and some cache and tlb entries from the latest document.

Add some new TLB and cache entries from document (Table 3-22 Encoding of CPUID
Leaf 2 Descriptors, Intel 64 and IA-32 Architectures Software Developer's
Manual Vol. 2A.)

Fix 0x0d's DCACHE entry and 0xeb's L3CACHE entry from the document
(Table 3-22 Encoding of CPUID Leaf 2 Descriptors, Intel 64 and IA-32
Architectures Software Developer's Manual Vol. 2A.)

branches: 1.13.2; 1.13.6; 1.13.10;
add info on L2 TLBs and 1GB pages.

branches: 1.12.12; 1.12.16;
Fix toyp in previous. Pointed out by snj@

1. Extend CPU probe of Intel processors to handle extended-models. This
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.

2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.

3. Convert decode of the various features masks to use the newly added
snprintb_m(3) routine.

Addresses my PR bin/41289
Addresses my PR bin/41290

Constify a userland-only member.

branches: 1.9.6; 1.9.8; 1.9.12; 1.9.16;
don't undef __CI_TBL before we use it :-)

- fix an amd cache entry.
- merge tables
- support phenom
from Paul Goyette

PR/38722: Paul Goyette: Share cacheinfo information

print L3 and TLB cache information for AMD Barcelona/Phenom

Simplify x86 identcpu code, and share between i386/amd64.

branches: 1.4.82; 1.4.84; 1.4.86; 1.4.88;
make multi inclusion protection macros consistent.

branches: 1.3.4; 1.3.10;
Get correct cache information for earlier VIA C3 models.
Mostly from PR kern/26689 submitted by Michael van Elst.

VIA C3 cache info.

branches: 1.1.2; 1.1.4;
Share some common cache info cpuid code between i386 and x86_64.