cacheinfo.h revision 1.21 
1/*	$NetBSD: cacheinfo.h,v 1.21 2016/01/08 02:25:15 msaitoh Exp $	*/
2
3#ifndef _X86_CACHEINFO_H_
4#define _X86_CACHEINFO_H_
5
6struct x86_cache_info {
7	uint8_t		cai_index;
8	uint8_t		cai_desc;
9	uint8_t		cai_associativity;
10	u_int		cai_totalsize; /* #entries for TLB, bytes for cache */
11	u_int		cai_linesize;	/*
12					 * or page size for TLB,
13					 * or prefetch size
14					 */
15#ifndef _KERNEL
16	const char	*cai_string;
17#endif
18};
19
20#define	CAI_ITLB	0		/* Instruction TLB (4K pages) */
21#define	CAI_ITLB2	1		/* Instruction TLB (2/4M pages) */
22#define	CAI_DTLB	2		/* Data TLB (4K pages) */
23#define	CAI_DTLB2	3		/* Data TLB (2/4M pages) */
24#define	CAI_ICACHE	4		/* Instruction cache */
25#define	CAI_DCACHE	5		/* Data cache */
26#define	CAI_L2CACHE	6		/* Level 2 cache */
27#define	CAI_L3CACHE	7		/* Level 3 cache */
28#define	CAI_L1_1GBITLB	8		/* L1 1GB Page instruction TLB */
29#define	CAI_L1_1GBDTLB	9		/* L1 1GB Page data TLB */
30#define CAI_L2_1GBITLB	10		/* L2 1GB Page instruction TLB */
31#define CAI_L2_1GBDTLB	11		/* L2 1GB Page data TLB */
32#define CAI_L2_ITLB	12		/* L2 Instruction TLB (4K pages) */
33#define CAI_L2_ITLB2	13		/* L2 Instruction TLB (2/4M pages) */
34#define CAI_L2_DTLB	14		/* L2 Data TLB (4K pages) */
35#define CAI_L2_DTLB2	15		/* L2 Data TLB (2/4M pages) */
36#define CAI_L2_STLB	16		/* Shared L2 TLB (4K pages) */
37#define CAI_L2_STLB2	17		/* Shared L2 TLB (4K/2M pages) */
38#define CAI_PREFETCH	18		/* Prefetch */
39
40#define	CAI_COUNT	19
41
42/*
43 * AMD Cache Info:
44 *
45 *      Barcelona, Phenom:
46 *
47 *		Function 8000.0005 L1 TLB/Cache Information
48 *		EAX -- L1 TLB 2/4MB pages
49 *		EBX -- L1 TLB 4K pages
50 *		ECX -- L1 D-cache
51 *		EDX -- L1 I-cache
52 *
53 *		Function 8000.0006 L2 TLB/Cache Information
54 *		EAX -- L2 TLB 2/4MB pages
55 *		EBX -- L2 TLB 4K pages
56 *		ECX -- L2 Unified cache
57 *		EDX -- L3 Unified Cache
58 *
59 *		Function 8000.0019 TLB 1GB Page Information
60 *		EAX -- L1 1GB pages
61 *		EBX -- L2 1GB pages
62 *		ECX -- reserved
63 *		EDX -- reserved
64 *
65 *	Athlon, Duron:
66 *
67 *		Function 8000.0005 L1 TLB/Cache Information
68 *		EAX -- L1 TLB 2/4MB pages
69 *		EBX -- L1 TLB 4K pages
70 *		ECX -- L1 D-cache
71 *		EDX -- L1 I-cache
72 *
73 *		Function 8000.0006 L2 TLB/Cache Information
74 *		EAX -- L2 TLB 2/4MB pages
75 *		EBX -- L2 TLB 4K pages
76 *		ECX -- L2 Unified cache
77 *		EDX -- reserved
78 *
79 *	K5, K6:
80 *
81 *		Function 8000.0005 L1 TLB/Cache Information
82 *		EAX -- reserved
83 *		EBX -- TLB 4K pages
84 *		ECX -- L1 D-cache
85 *		EDX -- L1 I-cache
86 *
87 *	K6-III:
88 *
89 *		Function 8000.0006 L2 Cache Information
90 *		EAX -- reserved
91 *		EBX -- reserved
92 *		ECX -- L2 Unified cache
93 *		EDX -- reserved
94 */
95
96/* L1 TLB 2/4MB pages */
97#define	AMD_L1_EAX_DTLB_ASSOC(x)	(((x) >> 24) & 0xff)
98#define	AMD_L1_EAX_DTLB_ENTRIES(x)	(((x) >> 16) & 0xff)
99#define	AMD_L1_EAX_ITLB_ASSOC(x)	(((x) >> 8)  & 0xff)
100#define	AMD_L1_EAX_ITLB_ENTRIES(x)	( (x)        & 0xff)
101
102/* L1 TLB 4K pages */
103#define	AMD_L1_EBX_DTLB_ASSOC(x)	(((x) >> 24) & 0xff)
104#define	AMD_L1_EBX_DTLB_ENTRIES(x)	(((x) >> 16) & 0xff)
105#define	AMD_L1_EBX_ITLB_ASSOC(x)	(((x) >> 8)  & 0xff)
106#define	AMD_L1_EBX_ITLB_ENTRIES(x)	( (x)        & 0xff)
107
108/* L1 Data Cache */
109#define	AMD_L1_ECX_DC_SIZE(x)		((((x) >> 24) & 0xff) * 1024)
110#define	AMD_L1_ECX_DC_ASSOC(x)		 (((x) >> 16) & 0xff)
111#define	AMD_L1_ECX_DC_LPT(x)		 (((x) >> 8)  & 0xff)
112#define	AMD_L1_ECX_DC_LS(x)		 ( (x)        & 0xff)
113
114/* L1 Instruction Cache */
115#define	AMD_L1_EDX_IC_SIZE(x)		((((x) >> 24) & 0xff) * 1024)
116#define	AMD_L1_EDX_IC_ASSOC(x)		 (((x) >> 16) & 0xff)
117#define	AMD_L1_EDX_IC_LPT(x)		 (((x) >> 8)  & 0xff)
118#define	AMD_L1_EDX_IC_LS(x)		 ( (x)        & 0xff)
119
120/* Note for L2 TLB -- if the upper 16 bits are 0, it is a unified TLB */
121
122/* L2 TLB 2/4MB pages */
123#define	AMD_L2_EAX_DTLB_ASSOC(x)	(((x) >> 28)  & 0xf)
124#define	AMD_L2_EAX_DTLB_ENTRIES(x)	(((x) >> 16)  & 0xfff)
125#define	AMD_L2_EAX_IUTLB_ASSOC(x)	(((x) >> 12)  & 0xf)
126#define	AMD_L2_EAX_IUTLB_ENTRIES(x)	( (x)         & 0xfff)
127
128/* L2 TLB 4K pages */
129#define	AMD_L2_EBX_DTLB_ASSOC(x)	(((x) >> 28)  & 0xf)
130#define	AMD_L2_EBX_DTLB_ENTRIES(x)	(((x) >> 16)  & 0xfff)
131#define	AMD_L2_EBX_IUTLB_ASSOC(x)	(((x) >> 12)  & 0xf)
132#define	AMD_L2_EBX_IUTLB_ENTRIES(x)	( (x)         & 0xfff)
133
134/* L2 Cache */
135#define	AMD_L2_ECX_C_SIZE(x)		((((x) >> 16) & 0xffff) * 1024)
136#define	AMD_L2_ECX_C_ASSOC(x)		 (((x) >> 12) & 0xf)
137#define	AMD_L2_ECX_C_LPT(x)		 (((x) >> 8)  & 0xf)
138#define	AMD_L2_ECX_C_LS(x)		 ( (x)        & 0xff)
139
140/* L3 Cache */
141#define AMD_L3_EDX_C_SIZE(x)		((((x) >> 18) & 0xffff) * 1024 * 512)
142#define AMD_L3_EDX_C_ASSOC(x)		 (((x) >> 12) & 0xff)
143#define AMD_L3_EDX_C_LPT(x)		 (((x) >> 8)  & 0xf)
144#define AMD_L3_EDX_C_LS(x)		 ( (x)        & 0xff)
145
146/* L1 TLB 1GB pages */
147#define AMD_L1_1GB_EAX_DTLB_ASSOC(x)	(((x) >> 28) & 0xf)
148#define AMD_L1_1GB_EAX_DTLB_ENTRIES(x)	(((x) >> 16) & 0xfff)
149#define AMD_L1_1GB_EAX_IUTLB_ASSOC(x)	(((x) >> 12) & 0xf)
150#define AMD_L1_1GB_EAX_IUTLB_ENTRIES(x)	( (x)        & 0xfff)
151
152/* L2 TLB 1GB pages */
153#define AMD_L2_1GB_EBX_DUTLB_ASSOC(x)	(((x) >> 28) & 0xf)
154#define AMD_L2_1GB_EBX_DUTLB_ENTRIES(x)	(((x) >> 16) & 0xfff)
155#define AMD_L2_1GB_EBX_IUTLB_ASSOC(x)	(((x) >> 12) & 0xf)
156#define AMD_L2_1GB_EBX_IUTLB_ENTRIES(x)	( (x)        & 0xfff)
157
158/*
159 * VIA Cache Info:
160 *
161 *	Nehemiah (at least)
162 *
163 *		Function 8000.0005 L1 TLB/Cache Information
164 *		EAX -- reserved
165 *		EBX -- L1 TLB 4K pages
166 *		ECX -- L1 D-cache
167 *		EDX -- L1 I-cache
168 *
169 *		Function 8000.0006 L2 Cache Information
170 *		EAX -- reserved
171 *		EBX -- reserved
172 *		ECX -- L2 Unified cache
173 *		EDX -- reserved
174 */
175
176/* L1 TLB 4K pages */
177#define	VIA_L1_EBX_DTLB_ASSOC(x)	(((x) >> 24) & 0xff)
178#define	VIA_L1_EBX_DTLB_ENTRIES(x)	(((x) >> 16) & 0xff)
179#define	VIA_L1_EBX_ITLB_ASSOC(x)	(((x) >> 8)  & 0xff)
180#define	VIA_L1_EBX_ITLB_ENTRIES(x)	( (x)        & 0xff)
181
182/* L1 Data Cache */
183#define	VIA_L1_ECX_DC_SIZE(x)		((((x) >> 24) & 0xff) * 1024)
184#define	VIA_L1_ECX_DC_ASSOC(x)		 (((x) >> 16) & 0xff)
185#define	VIA_L1_ECX_DC_LPT(x)		 (((x) >> 8)  & 0xff)
186#define	VIA_L1_ECX_DC_LS(x)		 ( (x)        & 0xff)
187
188/* L1 Instruction Cache */
189#define	VIA_L1_EDX_IC_SIZE(x)		((((x) >> 24) & 0xff) * 1024)
190#define	VIA_L1_EDX_IC_ASSOC(x)		 (((x) >> 16) & 0xff)
191#define	VIA_L1_EDX_IC_LPT(x)		 (((x) >> 8)  & 0xff)
192#define	VIA_L1_EDX_IC_LS(x)		 ( (x)        & 0xff)
193
194/* L2 Cache (pre-Nehemiah) */
195#define	VIA_L2_ECX_C_SIZE(x)		((((x) >> 24) & 0xff) * 1024)
196#define	VIA_L2_ECX_C_ASSOC(x)		 (((x) >> 16) & 0xff)
197#define	VIA_L2_ECX_C_LPT(x)		 (((x) >> 8)  & 0xff)
198#define	VIA_L2_ECX_C_LS(x)		 ( (x)        & 0xff)
199
200/* L2 Cache (Nehemiah and newer) */
201#define	VIA_L2N_ECX_C_SIZE(x)		((((x) >> 16) & 0xffff) * 1024)
202#define	VIA_L2N_ECX_C_ASSOC(x)		 (((x) >> 12) & 0xf)
203#define	VIA_L2N_ECX_C_LPT(x)		 (((x) >> 8)  & 0xf)
204#define	VIA_L2N_ECX_C_LS(x)		 ( (x)        & 0xff)
205
206#ifdef _KERNEL
207#define __CI_TBL(a,b,c,d,e,f) { a, b, c, d, e }
208#else
209#define __CI_TBL(a,b,c,d,e,f) { a, b, c, d, e, f }
210#endif
211
212/*
213 * XXX Currently organized mostly by cache type, but would be
214 * XXX easier to maintain if it were in descriptor type order.
215 */
216#define INTEL_CACHE_INFO { \
217__CI_TBL(CAI_ITLB,     0x01,    4, 32,        4 * 1024, NULL), \
218__CI_TBL(CAI_ITLB2,    0x02, 0xff,  2, 4 * 1024 * 1024, NULL), \
219__CI_TBL(CAI_DTLB,     0x03,    4, 64,        4 * 1024, NULL), \
220__CI_TBL(CAI_DTLB2,    0x04,    4,  8, 4 * 1024 * 1024, NULL), \
221__CI_TBL(CAI_DTLB2,    0x05,    4, 32, 4 * 1024 * 1024, NULL), \
222__CI_TBL(CAI_ITLB2,    0x0b,    4,  4, 4 * 1024 * 1024, NULL), \
223__CI_TBL(CAI_ITLB,     0x4f, 0xff, 32,        4 * 1024, NULL), \
224__CI_TBL(CAI_ITLB,     0x50, 0xff, 64,        4 * 1024, "4K/4M: 64 entries"), \
225__CI_TBL(CAI_ITLB,     0x51, 0xff, 64,        4 * 1024, "4K/4M: 128 entries"),\
226__CI_TBL(CAI_ITLB,     0x52, 0xff, 64,        4 * 1024, "4K/4M: 256 entries"),\
227__CI_TBL(CAI_ITLB2,    0x55, 0xff, 64,        4 * 1024, "2M/4M: 7 entries"), \
228__CI_TBL(CAI_DTLB2,    0x56,    4, 16, 4 * 1024 * 1024, NULL), \
229__CI_TBL(CAI_DTLB,     0x57,    4, 16,        4 * 1024, NULL), \
230__CI_TBL(CAI_DTLB,     0x59, 0xff, 16,        4 * 1024, NULL), \
231__CI_TBL(CAI_DTLB2,    0x5a, 0xff, 64,        4 * 1024, "2M/4M: 32 entries (L0)"), \
232__CI_TBL(CAI_DTLB,     0x5b, 0xff, 64,        4 * 1024, "4K/4M: 64 entries"), \
233__CI_TBL(CAI_DTLB,     0x5c, 0xff, 64,        4 * 1024, "4K/4M: 128 entries"),\
234__CI_TBL(CAI_DTLB,     0x5d, 0xff, 64,        4 * 1024, "4K/4M: 256 entries"),\
235__CI_TBL(CAI_ITLB,     0x61, 0xff, 48,        4 * 1024, NULL), \
236__CI_TBL(CAI_L1_1GBDTLB,0x63,   4,  4,1024*1024 * 1024, NULL), \
237__CI_TBL(CAI_ITLB,     0x6a,    8, 64,        4 * 1024, NULL), \
238__CI_TBL(CAI_DTLB,     0x6b,    8,256,        4 * 1024, NULL), \
239__CI_TBL(CAI_L2_DTLB2, 0x6c,    8,128,               0, "2M/4M: 128 entries"),\
240__CI_TBL(CAI_L1_1GBDTLB,0x6d,0xff, 16,1024*1024 * 1024, NULL), \
241__CI_TBL(CAI_ITLB2,    0x76, 0xff,  8, 4 * 1024 * 1024, "2M/4M: 8 entries"), \
242__CI_TBL(CAI_DTLB,     0xa0, 0xff, 32,        4 * 1024, NULL), \
243__CI_TBL(CAI_ITLB,     0xb0,    4,128,        4 * 1024, NULL), \
244__CI_TBL(CAI_ITLB2,    0xb1,    4, 64,               0, "8 2M/4 4M entries"), \
245__CI_TBL(CAI_ITLB,     0xb2,    4, 64,        4 * 1024, NULL), \
246__CI_TBL(CAI_DTLB,     0xb3,    4,128,        4 * 1024, NULL), \
247__CI_TBL(CAI_DTLB,     0xb4,    4,256,        4 * 1024, NULL), \
248__CI_TBL(CAI_ITLB,     0xb5,    8, 64,        4 * 1024, NULL), \
249__CI_TBL(CAI_ITLB,     0xb6,    8,128,        4 * 1024, NULL), \
250__CI_TBL(CAI_DTLB,     0xba,    4, 64,        4 * 1024, NULL), \
251__CI_TBL(CAI_DTLB2,    0xc0,    4,  8,        4 * 1024, "4K/4M: 8 entries"), \
252__CI_TBL(CAI_L2_STLB2, 0xc1,    8,1024,       4 * 1024, "4K/2M: 1024 entries"), \
253__CI_TBL(CAI_DTLB2,    0xc2,    4, 16,        4 * 1024, "4K/2M: 16 entries"), \
254__CI_TBL(CAI_L2_STLB,  0xc3,    6,1536,       4 * 1024, NULL), \
255__CI_TBL(CAI_L2_STLB,  0xca,    4,512,        4 * 1024, NULL), \
256__CI_TBL(CAI_ICACHE,   0x06,    4,        8 * 1024, 32, NULL), \
257__CI_TBL(CAI_ICACHE,   0x08,    4,       16 * 1024, 32, NULL), \
258__CI_TBL(CAI_ICACHE,   0x09,    4,       32 * 1024, 64, NULL), \
259__CI_TBL(CAI_DCACHE,   0x0a,    2,        8 * 1024, 32, NULL), \
260__CI_TBL(CAI_DCACHE,   0x0c,    4,       16 * 1024, 32, NULL), \
261__CI_TBL(CAI_DCACHE,   0x0d,    4,       16 * 1024, 64, NULL), \
262__CI_TBL(CAI_DCACHE,   0x0e,    6,       24 * 1024, 64, NULL), \
263__CI_TBL(CAI_L2CACHE,  0x21,    8,      256 * 1024, 64, NULL), /* L2 (MLC) */ \
264__CI_TBL(CAI_L3CACHE,  0x22, 0xff,      512 * 1024, 64, "sectored, 4-way "), \
265__CI_TBL(CAI_L3CACHE,  0x23, 0xff, 1 * 1024 * 1024, 64, "sectored, 8-way "), \
266__CI_TBL(CAI_L2CACHE,  0x24,   16, 1 * 1024 * 1024, 64, NULL), \
267__CI_TBL(CAI_L3CACHE,  0x25, 0xff, 2 * 1024 * 1024, 64, "sectored, 8-way "), \
268__CI_TBL(CAI_L3CACHE,  0x29, 0xff, 4 * 1024 * 1024, 64, "sectored, 8-way "), \
269__CI_TBL(CAI_DCACHE,   0x2c,    8,       32 * 1024, 64, NULL), \
270__CI_TBL(CAI_ICACHE,   0x30,    8,       32 * 1024, 64, NULL), \
271__CI_TBL(CAI_L2CACHE,  0x39,    4,      128 * 1024, 64, NULL), \
272__CI_TBL(CAI_L2CACHE,  0x3a,    6,      192 * 1024, 64, NULL), \
273__CI_TBL(CAI_L2CACHE,  0x3b,    2,      128 * 1024, 64, NULL), \
274__CI_TBL(CAI_L2CACHE,  0x3c,    4,      256 * 1024, 64, NULL), \
275__CI_TBL(CAI_L2CACHE,  0x3d,    6,      384 * 1024, 64, NULL), \
276__CI_TBL(CAI_L2CACHE,  0x3e,    4,      512 * 1024, 64, NULL), \
277__CI_TBL(CAI_L2CACHE,  0x40,    0,               0,  0, "not present"), \
278__CI_TBL(CAI_L2CACHE,  0x41,    4,      128 * 1024, 32, NULL), \
279__CI_TBL(CAI_L2CACHE,  0x42,    4,      256 * 1024, 32, NULL), \
280__CI_TBL(CAI_L2CACHE,  0x43,    4,      512 * 1024, 32, NULL), \
281__CI_TBL(CAI_L2CACHE,  0x44,    4, 1 * 1024 * 1024, 32, NULL), \
282__CI_TBL(CAI_L2CACHE,  0x45,    4, 2 * 1024 * 1024, 32, NULL), \
283__CI_TBL(CAI_L3CACHE,  0x46,    4, 4 * 1024 * 1024, 64, NULL), \
284__CI_TBL(CAI_L3CACHE,  0x47,    8, 8 * 1024 * 1024, 64, NULL), \
285__CI_TBL(CAI_L2CACHE,  0x48,   12, 3 * 1024 * 1024, 64, NULL), \
286								\
287/* 0x49 Is L2 on Xeon MP (Family 0f, Model 06), L3 otherwise */	\
288__CI_TBL(CAI_L2CACHE,  0x49,   16, 4 * 1024 * 1024, 64, NULL), \
289__CI_TBL(CAI_L3CACHE,  0x49,   16, 4 * 1024 * 1024, 64, NULL), \
290__CI_TBL(CAI_L3CACHE,  0x4a,   12, 6 * 1024 * 1024, 64, NULL), \
291__CI_TBL(CAI_L3CACHE,  0x4b,   16, 8 * 1024 * 1024, 64, NULL), \
292__CI_TBL(CAI_L3CACHE,  0x4c,   12,12 * 1024 * 1024, 64, NULL), \
293__CI_TBL(CAI_L3CACHE,  0x4d,   16,16 * 1024 * 1024, 64, NULL), \
294__CI_TBL(CAI_L2CACHE,  0x4e,   24, 6 * 1024 * 1024, 64, NULL), \
295__CI_TBL(CAI_DCACHE,   0x60,    8,       16 * 1024, 64, NULL), \
296__CI_TBL(CAI_DCACHE,   0x66,    4,        8 * 1024, 64, NULL), \
297__CI_TBL(CAI_DCACHE,   0x67,    4,       16 * 1024, 64, NULL), \
298__CI_TBL(CAI_DCACHE,   0x68,    4,       32 * 1024, 64, NULL), \
299__CI_TBL(CAI_ICACHE,   0x70,    8,       12 * 1024, 64, "12K uOp cache"), \
300__CI_TBL(CAI_ICACHE,   0x71,    8,       16 * 1024, 64, "16K uOp cache"), \
301__CI_TBL(CAI_ICACHE,   0x72,    8,       32 * 1024, 64, "32K uOp cache"), \
302__CI_TBL(CAI_ICACHE,   0x73,    8,       64 * 1024, 64, "64K uOp cache"), \
303__CI_TBL(CAI_L2CACHE,  0x78,    4, 1 * 1024 * 1024, 64, NULL), \
304__CI_TBL(CAI_L2CACHE,  0x79,    8,      128 * 1024, 64, NULL), \
305__CI_TBL(CAI_L2CACHE,  0x7a,    8,      256 * 1024, 64, NULL), \
306__CI_TBL(CAI_L2CACHE,  0x7b,    8,      512 * 1024, 64, NULL), \
307__CI_TBL(CAI_L2CACHE,  0x7c,    8, 1 * 1024 * 1024, 64, NULL), \
308__CI_TBL(CAI_L2CACHE,  0x7d,    8, 2 * 1024 * 1024, 64, NULL), \
309__CI_TBL(CAI_L2CACHE,  0x7f,    2,      512 * 1024, 64, NULL), \
310__CI_TBL(CAI_L2CACHE,  0x80,    8,      512 * 1024, 64, NULL), \
311__CI_TBL(CAI_L2CACHE,  0x82,    8,      256 * 1024, 32, NULL), \
312__CI_TBL(CAI_L2CACHE,  0x83,    8,      512 * 1024, 32, NULL), \
313__CI_TBL(CAI_L2CACHE,  0x84,    8, 1 * 1024 * 1024, 32, NULL), \
314__CI_TBL(CAI_L2CACHE,  0x85,    8, 2 * 1024 * 1024, 32, NULL), \
315__CI_TBL(CAI_L2CACHE,  0x86,    4,      512 * 1024, 64, NULL), \
316__CI_TBL(CAI_L2CACHE,  0x87,    8, 1 * 1024 * 1024, 64, NULL), \
317__CI_TBL(CAI_L3CACHE,  0xd0,    4,      512 * 1024, 64, NULL), \
318__CI_TBL(CAI_L3CACHE,  0xd1,    4, 1 * 1024 * 1024, 64, NULL), \
319__CI_TBL(CAI_L3CACHE,  0xd2,    4, 2 * 1024 * 1024, 64, NULL), \
320__CI_TBL(CAI_L3CACHE,  0xd6,    8, 1 * 1024 * 1024, 64, NULL), \
321__CI_TBL(CAI_L3CACHE,  0xd7,    8, 2 * 1024 * 1024, 64, NULL), \
322__CI_TBL(CAI_L3CACHE,  0xd8,    8, 4 * 1024 * 1024, 64, NULL), \
323__CI_TBL(CAI_L3CACHE,  0xdc,   12, 3 *  512 * 1024, 64, NULL), \
324__CI_TBL(CAI_L3CACHE,  0xdd,   12, 3 * 1024 * 1024, 64, NULL), \
325__CI_TBL(CAI_L3CACHE,  0xde,   12, 6 * 1024 * 1024, 64, NULL), \
326__CI_TBL(CAI_L3CACHE,  0xe2,   16, 2 * 1024 * 1024, 64, NULL), \
327__CI_TBL(CAI_L3CACHE,  0xe3,   16, 4 * 1024 * 1024, 64, NULL), \
328__CI_TBL(CAI_L3CACHE,  0xe4,   16, 8 * 1024 * 1024, 64, NULL), \
329__CI_TBL(CAI_L3CACHE,  0xea,   24,12 * 1024 * 1024, 64, NULL), \
330__CI_TBL(CAI_L3CACHE,  0xeb,   24,18 * 1024 * 1024, 64, NULL), \
331__CI_TBL(CAI_L3CACHE,  0xec,   24,24 * 1024 * 1024, 64, NULL), \
332__CI_TBL(CAI_PREFETCH, 0xf0,    0,               0, 64, NULL), \
333__CI_TBL(CAI_PREFETCH, 0xf1,    0,               0,128, NULL), \
334/* 0xff means no cache information in CPUID leaf 2 (and use leaf 4) */ \
335__CI_TBL(0,               0,    0,               0,  0, NULL)  \
336}
337
338#define AMD_L2CACHE_INFO { \
339__CI_TBL(0, 0x01,    1, 0, 0, NULL), \
340__CI_TBL(0, 0x02,    2, 0, 0, NULL), \
341__CI_TBL(0, 0x04,    4, 0, 0, NULL), \
342__CI_TBL(0, 0x06,    8, 0, 0, NULL), \
343__CI_TBL(0, 0x08,   16, 0, 0, NULL), \
344__CI_TBL(0, 0x0a,   32, 0, 0, NULL), \
345__CI_TBL(0, 0x0b,   48, 0, 0, NULL), \
346__CI_TBL(0, 0x0c,   64, 0, 0, NULL), \
347__CI_TBL(0, 0x0d,   96, 0, 0, NULL), \
348__CI_TBL(0, 0x0e,  128, 0, 0, NULL), \
349__CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \
350__CI_TBL(0, 0x00,    0, 0, 0, NULL)  \
351}
352
353#define AMD_L3CACHE_INFO { \
354__CI_TBL(0, 0x01,    1, 0, 0, NULL), \
355__CI_TBL(0, 0x02,    2, 0, 0, NULL), \
356__CI_TBL(0, 0x04,    4, 0, 0, NULL), \
357__CI_TBL(0, 0x06,    8, 0, 0, NULL), \
358__CI_TBL(0, 0x08,   16, 0, 0, NULL), \
359__CI_TBL(0, 0x0a,   32, 0, 0, NULL), \
360__CI_TBL(0, 0x0b,   48, 0, 0, NULL), \
361__CI_TBL(0, 0x0c,   64, 0, 0, NULL), \
362__CI_TBL(0, 0x0d,   96, 0, 0, NULL), \
363__CI_TBL(0, 0x0e,  128, 0, 0, NULL), \
364__CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \
365__CI_TBL(0, 0x00,    0, 0, 0, NULL)  \
366}
367
368#endif /* _X86_CACHEINFO_H_ */
369