cacheinfo.h revision 1.1 
1/*	$NetBSD: cacheinfo.h,v 1.1 2003/04/25 21:54:30 fvdl Exp $	*/
2
3#ifndef _X86_CACHEINFO_H
4#define _X86_CACHEINFO_H
5
6struct x86_cache_info {
7	uint8_t		cai_index;
8	uint8_t		cai_desc;
9	uint8_t		cai_associativity;
10	u_int		cai_totalsize; /* #entries for TLB, bytes for cache */
11	u_int		cai_linesize;	/* or page size for TLB */
12	const char	*cai_string;
13};
14
15#define	CAI_ITLB	0		/* Instruction TLB (4K pages) */
16#define	CAI_ITLB2	1		/* Instruction TLB (2/4M pages) */
17#define	CAI_DTLB	2		/* Data TLB (4K pages) */
18#define	CAI_DTLB2	3		/* Data TLB (2/4M pages) */
19#define	CAI_ICACHE	4		/* Instruction cache */
20#define	CAI_DCACHE	5		/* Data cache */
21#define	CAI_L2CACHE	6		/* Level 2 cache */
22
23#define	CAI_COUNT	7
24
25struct cpu_info;
26
27const struct x86_cache_info *cache_info_lookup(const struct x86_cache_info *,
28					       u_int8_t);
29void amd_cpu_cacheinfo(struct cpu_info *);
30void x86_print_cacheinfo(struct cpu_info *);
31
32/*
33 * AMD Cache Info:
34 *
35 *	Athlon, Duron:
36 *
37 *		Function 8000.0005 L1 TLB/Cache Information
38 *		EAX -- L1 TLB 2/4MB pages
39 *		EBX -- L1 TLB 4K pages
40 *		ECX -- L1 D-cache
41 *		EDX -- L1 I-cache
42 *
43 *		Function 8000.0006 L2 TLB/Cache Information
44 *		EAX -- L2 TLB 2/4MB pages
45 *		EBX -- L2 TLB 4K pages
46 *		ECX -- L2 Unified cache
47 *		EDX -- reserved
48 *
49 *	K5, K6:
50 *
51 *		Function 8000.0005 L1 TLB/Cache Information
52 *		EAX -- reserved
53 *		EBX -- TLB 4K pages
54 *		ECX -- L1 D-cache
55 *		EDX -- L1 I-cache
56 *
57 *	K6-III:
58 *
59 *		Function 8000.0006 L2 Cache Information
60 *		EAX -- reserved
61 *		EBX -- reserved
62 *		ECX -- L2 Unified cache
63 *		EDX -- reserved
64 */
65
66/* L1 TLB 2/4MB pages */
67#define	AMD_L1_EAX_DTLB_ASSOC(x)	(((x) >> 24) & 0xff)
68#define	AMD_L1_EAX_DTLB_ENTRIES(x)	(((x) >> 16) & 0xff)
69#define	AMD_L1_EAX_ITLB_ASSOC(x)	(((x) >> 8)  & 0xff)
70#define	AMD_L1_EAX_ITLB_ENTRIES(x)	( (x)        & 0xff)
71
72/* L1 TLB 4K pages */
73#define	AMD_L1_EBX_DTLB_ASSOC(x)	(((x) >> 24) & 0xff)
74#define	AMD_L1_EBX_DTLB_ENTRIES(x)	(((x) >> 16) & 0xff)
75#define	AMD_L1_EBX_ITLB_ASSOC(x)	(((x) >> 8)  & 0xff)
76#define	AMD_L1_EBX_ITLB_ENTRIES(x)	( (x)        & 0xff)
77
78/* L1 Data Cache */
79#define	AMD_L1_ECX_DC_SIZE(x)		((((x) >> 24) & 0xff) * 1024)
80#define	AMD_L1_ECX_DC_ASSOC(x)		 (((x) >> 16) & 0xff)
81#define	AMD_L1_ECX_DC_LPT(x)		 (((x) >> 8)  & 0xff)
82#define	AMD_L1_ECX_DC_LS(x)		 ( (x)        & 0xff)
83
84/* L1 Instruction Cache */
85#define	AMD_L1_EDX_IC_SIZE(x)		((((x) >> 24) & 0xff) * 1024)
86#define	AMD_L1_EDX_IC_ASSOC(x)		 (((x) >> 16) & 0xff)
87#define	AMD_L1_EDX_IC_LPT(x)		 (((x) >> 8)  & 0xff)
88#define	AMD_L1_EDX_IC_LS(x)		 ( (x)        & 0xff)
89
90/* Note for L2 TLB -- if the upper 16 bits are 0, it is a unified TLB */
91
92/* L2 TLB 2/4MB pages */
93#define	AMD_L2_EAX_DTLB_ASSOC(x)	(((x) >> 28)  & 0xf)
94#define	AMD_L2_EAX_DTLB_ENTRIES(x)	(((x) >> 16)  & 0xfff)
95#define	AMD_L2_EAX_IUTLB_ASSOC(x)	(((x) >> 12)  & 0xf)
96#define	AMD_L2_EAX_IUTLB_ENTRIES(x)	( (x)         & 0xfff)
97
98/* L2 TLB 4K pages */
99#define	AMD_L2_EBX_DTLB_ASSOC(x)	(((x) >> 28)  & 0xf)
100#define	AMD_L2_EBX_DTLB_ENTRIES(x)	(((x) >> 16)  & 0xfff)
101#define	AMD_L2_EBX_IUTLB_ASSOC(x)	(((x) >> 12)  & 0xf)
102#define	AMD_L2_EBX_IUTLB_ENTRIES(x)	( (x)         & 0xfff)
103
104/* L2 Cache */
105#define	AMD_L2_ECX_C_SIZE(x)		((((x) >> 16) & 0xffff) * 1024)
106#define	AMD_L2_ECX_C_ASSOC(x)		 (((x) >> 12) & 0xf)
107#define	AMD_L2_ECX_C_LPT(x)		 (((x) >> 8)  & 0xf)
108#define	AMD_L2_ECX_C_LS(x)		 ( (x)        & 0xff)
109
110#endif /* _X86_CACHEINFO_H */
111