cacheinfo.h revision 1.7 
1/*	$NetBSD: cacheinfo.h,v 1.7 2008/05/30 14:42:42 christos Exp $	*/
2
3#ifndef _X86_CACHEINFO_H_
4#define _X86_CACHEINFO_H_
5
6struct x86_cache_info {
7	uint8_t		cai_index;
8	uint8_t		cai_desc;
9	uint8_t		cai_associativity;
10	u_int		cai_totalsize; /* #entries for TLB, bytes for cache */
11	u_int		cai_linesize;	/* or page size for TLB */
12#ifndef _KERNEL
13	char		*cai_string;
14#endif
15};
16
17#define	CAI_ITLB	0		/* Instruction TLB (4K pages) */
18#define	CAI_ITLB2	1		/* Instruction TLB (2/4M pages) */
19#define	CAI_DTLB	2		/* Data TLB (4K pages) */
20#define	CAI_DTLB2	3		/* Data TLB (2/4M pages) */
21#define	CAI_ICACHE	4		/* Instruction cache */
22#define	CAI_DCACHE	5		/* Data cache */
23#define	CAI_L2CACHE	6		/* Level 2 cache */
24#define	CAI_L3CACHE	7		/* Level 3 cache */
25#define	CAI_L1_1GBITLB	8		/* L1 1GB Page instruction TLB */
26#define	CAI_L1_1GBDTLB	9		/* L1 1GB Page data TLB */
27#define CAI_L2_1GBITLB	10		/* L2 1GB Page instruction TLB */
28#define CAI_L2_1GBDTLB	11		/* L2 1GB Page data TLB */
29
30#define	CAI_COUNT	12
31
32/*
33 * AMD Cache Info:
34 *
35 *      Barcelona, Phenom:
36 *
37 *		Function 8000.0005 L1 TLB/Cache Information
38 *		EAX -- L1 TLB 2/4MB pages
39 *		EBX -- L1 TLB 4K pages
40 *		ECX -- L1 D-cache
41 *		EDX -- L1 I-cache
42 *
43 *		Function 8000.0006 L2 TLB/Cache Information
44 *		EAX -- L2 TLB 2/4MB pages
45 *		EBX -- L2 TLB 4K pages
46 *		ECX -- L2 Unified cache
47 *		EDX -- L3 Unified Cache
48 *
49 *		Function 8000.0019 TLB 1GB Page Information
50 *		EAX -- L1 1GB pages
51 *		EBX -- L2 1GB pages
52 *		ECX -- reserved
53 *		EDX -- reserved
54 *
55 *	Athlon, Duron:
56 *
57 *		Function 8000.0005 L1 TLB/Cache Information
58 *		EAX -- L1 TLB 2/4MB pages
59 *		EBX -- L1 TLB 4K pages
60 *		ECX -- L1 D-cache
61 *		EDX -- L1 I-cache
62 *
63 *		Function 8000.0006 L2 TLB/Cache Information
64 *		EAX -- L2 TLB 2/4MB pages
65 *		EBX -- L2 TLB 4K pages
66 *		ECX -- L2 Unified cache
67 *		EDX -- reserved
68 *
69 *	K5, K6:
70 *
71 *		Function 8000.0005 L1 TLB/Cache Information
72 *		EAX -- reserved
73 *		EBX -- TLB 4K pages
74 *		ECX -- L1 D-cache
75 *		EDX -- L1 I-cache
76 *
77 *	K6-III:
78 *
79 *		Function 8000.0006 L2 Cache Information
80 *		EAX -- reserved
81 *		EBX -- reserved
82 *		ECX -- L2 Unified cache
83 *		EDX -- reserved
84 */
85
86/* L1 TLB 2/4MB pages */
87#define	AMD_L1_EAX_DTLB_ASSOC(x)	(((x) >> 24) & 0xff)
88#define	AMD_L1_EAX_DTLB_ENTRIES(x)	(((x) >> 16) & 0xff)
89#define	AMD_L1_EAX_ITLB_ASSOC(x)	(((x) >> 8)  & 0xff)
90#define	AMD_L1_EAX_ITLB_ENTRIES(x)	( (x)        & 0xff)
91
92/* L1 TLB 4K pages */
93#define	AMD_L1_EBX_DTLB_ASSOC(x)	(((x) >> 24) & 0xff)
94#define	AMD_L1_EBX_DTLB_ENTRIES(x)	(((x) >> 16) & 0xff)
95#define	AMD_L1_EBX_ITLB_ASSOC(x)	(((x) >> 8)  & 0xff)
96#define	AMD_L1_EBX_ITLB_ENTRIES(x)	( (x)        & 0xff)
97
98/* L1 Data Cache */
99#define	AMD_L1_ECX_DC_SIZE(x)		((((x) >> 24) & 0xff) * 1024)
100#define	AMD_L1_ECX_DC_ASSOC(x)		 (((x) >> 16) & 0xff)
101#define	AMD_L1_ECX_DC_LPT(x)		 (((x) >> 8)  & 0xff)
102#define	AMD_L1_ECX_DC_LS(x)		 ( (x)        & 0xff)
103
104/* L1 Instruction Cache */
105#define	AMD_L1_EDX_IC_SIZE(x)		((((x) >> 24) & 0xff) * 1024)
106#define	AMD_L1_EDX_IC_ASSOC(x)		 (((x) >> 16) & 0xff)
107#define	AMD_L1_EDX_IC_LPT(x)		 (((x) >> 8)  & 0xff)
108#define	AMD_L1_EDX_IC_LS(x)		 ( (x)        & 0xff)
109
110/* Note for L2 TLB -- if the upper 16 bits are 0, it is a unified TLB */
111
112/* L2 TLB 2/4MB pages */
113#define	AMD_L2_EAX_DTLB_ASSOC(x)	(((x) >> 28)  & 0xf)
114#define	AMD_L2_EAX_DTLB_ENTRIES(x)	(((x) >> 16)  & 0xfff)
115#define	AMD_L2_EAX_IUTLB_ASSOC(x)	(((x) >> 12)  & 0xf)
116#define	AMD_L2_EAX_IUTLB_ENTRIES(x)	( (x)         & 0xfff)
117
118/* L2 TLB 4K pages */
119#define	AMD_L2_EBX_DTLB_ASSOC(x)	(((x) >> 28)  & 0xf)
120#define	AMD_L2_EBX_DTLB_ENTRIES(x)	(((x) >> 16)  & 0xfff)
121#define	AMD_L2_EBX_IUTLB_ASSOC(x)	(((x) >> 12)  & 0xf)
122#define	AMD_L2_EBX_IUTLB_ENTRIES(x)	( (x)         & 0xfff)
123
124/* L2 Cache */
125#define	AMD_L2_ECX_C_SIZE(x)		((((x) >> 16) & 0xffff) * 1024)
126#define	AMD_L2_ECX_C_ASSOC(x)		 (((x) >> 12) & 0xf)
127#define	AMD_L2_ECX_C_LPT(x)		 (((x) >> 8)  & 0xf)
128#define	AMD_L2_ECX_C_LS(x)		 ( (x)        & 0xff)
129
130/* L3 Cache */
131#define AMD_L3_EDX_C_SIZE(x)		((((x) >> 18) & 0xffff) * 1024)
132#define AMD_L3_EDX_C_ASSOC(x)		 (((x) >> 12) & 0xff)
133#define AMD_L3_EDX_C_LPT(x)		 (((x) >> 8)  & 0xf)
134#define AMD_L3_EDX_C_LS(x)		 ( (x)        & 0xff)
135
136/* L1 TLB 1GB pages */
137#define AMD_L1_1GB_EAX_DTLB_ASSOC(x)	(((x) >> 28) & 0xf)
138#define AMD_L1_1GB_EAX_DTLB_ENTRIES(x)	(((x) >> 16) & 0xfff)
139#define AMD_L1_1GB_EAX_IUTLB_ASSOC(x)	(((x) >> 12) & 0xf)
140#define AMD_L1_1GB_EAX_IUTLB_ENTRIES(x)	( (x)        & 0xfff)
141
142/* L2 TLB 1GB pages */
143#define AMD_L2_1GB_EBX_DUTLB_ASSOC(x)	(((x) >> 28) & 0xf)
144#define AMD_L2_1GB_EBX_DUTLB_ENTRIES(x)	(((x) >> 16) & 0xfff)
145#define AMD_L2_1GB_EBX_IUTLB_ASSOC(x)	(((x) >> 12) & 0xf)
146#define AMD_L2_1GB_EBX_IUTLB_ENTRIES(x)	( (x)        & 0xfff)
147
148/*
149 * VIA Cache Info:
150 *
151 *	Nehemiah (at least)
152 *
153 *		Function 8000.0005 L1 TLB/Cache Information
154 *		EAX -- reserved
155 *		EBX -- L1 TLB 4K pages
156 *		ECX -- L1 D-cache
157 *		EDX -- L1 I-cache
158 *
159 *		Function 8000.0006 L2 Cache Information
160 *		EAX -- reserved
161 *		EBX -- reserved
162 *		ECX -- L2 Unified cache
163 *		EDX -- reserved
164 */
165
166/* L1 TLB 4K pages */
167#define	VIA_L1_EBX_DTLB_ASSOC(x)	(((x) >> 24) & 0xff)
168#define	VIA_L1_EBX_DTLB_ENTRIES(x)	(((x) >> 16) & 0xff)
169#define	VIA_L1_EBX_ITLB_ASSOC(x)	(((x) >> 8)  & 0xff)
170#define	VIA_L1_EBX_ITLB_ENTRIES(x)	( (x)        & 0xff)
171
172/* L1 Data Cache */
173#define	VIA_L1_ECX_DC_SIZE(x)		((((x) >> 24) & 0xff) * 1024)
174#define	VIA_L1_ECX_DC_ASSOC(x)		 (((x) >> 16) & 0xff)
175#define	VIA_L1_ECX_DC_LPT(x)		 (((x) >> 8)  & 0xff)
176#define	VIA_L1_ECX_DC_LS(x)		 ( (x)        & 0xff)
177
178/* L1 Instruction Cache */
179#define	VIA_L1_EDX_IC_SIZE(x)		((((x) >> 24) & 0xff) * 1024)
180#define	VIA_L1_EDX_IC_ASSOC(x)		 (((x) >> 16) & 0xff)
181#define	VIA_L1_EDX_IC_LPT(x)		 (((x) >> 8)  & 0xff)
182#define	VIA_L1_EDX_IC_LS(x)		 ( (x)        & 0xff)
183
184/* L2 Cache (pre-Nehemiah) */
185#define	VIA_L2_ECX_C_SIZE(x)		((((x) >> 24) & 0xff) * 1024)
186#define	VIA_L2_ECX_C_ASSOC(x)		 (((x) >> 16) & 0xff)
187#define	VIA_L2_ECX_C_LPT(x)		 (((x) >> 8)  & 0xff)
188#define	VIA_L2_ECX_C_LS(x)		 ( (x)        & 0xff)
189
190/* L2 Cache (Nehemiah and newer) */
191#define	VIA_L2N_ECX_C_SIZE(x)		((((x) >> 16) & 0xffff) * 1024)
192#define	VIA_L2N_ECX_C_ASSOC(x)		 (((x) >> 12) & 0xf)
193#define	VIA_L2N_ECX_C_LPT(x)		 (((x) >> 8)  & 0xf)
194#define	VIA_L2N_ECX_C_LS(x)		 ( (x)        & 0xff)
195
196#endif /* _X86_CACHEINFO_H_ */
197