cacheinfo.h revision 1.12
1/* $NetBSD: cacheinfo.h,v 1.12 2009/05/13 23:26:38 pgoyette Exp $ */ 2 3#ifndef _X86_CACHEINFO_H_ 4#define _X86_CACHEINFO_H_ 5 6struct x86_cache_info { 7 uint8_t cai_index; 8 uint8_t cai_desc; 9 uint8_t cai_associativity; 10 u_int cai_totalsize; /* #entries for TLB, bytes for cache */ 11 u_int cai_linesize; /* or page size for TLB */ 12#ifndef _KERNEL 13 const char *cai_string; 14#endif 15}; 16 17#define CAI_ITLB 0 /* Instruction TLB (4K pages) */ 18#define CAI_ITLB2 1 /* Instruction TLB (2/4M pages) */ 19#define CAI_DTLB 2 /* Data TLB (4K pages) */ 20#define CAI_DTLB2 3 /* Data TLB (2/4M pages) */ 21#define CAI_ICACHE 4 /* Instruction cache */ 22#define CAI_DCACHE 5 /* Data cache */ 23#define CAI_L2CACHE 6 /* Level 2 cache */ 24#define CAI_L3CACHE 7 /* Level 3 cache */ 25#define CAI_L1_1GBITLB 8 /* L1 1GB Page instruction TLB */ 26#define CAI_L1_1GBDTLB 9 /* L1 1GB Page data TLB */ 27#define CAI_L2_1GBITLB 10 /* L2 1GB Page instruction TLB */ 28#define CAI_L2_1GBDTLB 11 /* L2 1GB Page data TLB */ 29 30#define CAI_COUNT 12 31 32/* 33 * AMD Cache Info: 34 * 35 * Barcelona, Phenom: 36 * 37 * Function 8000.0005 L1 TLB/Cache Information 38 * EAX -- L1 TLB 2/4MB pages 39 * EBX -- L1 TLB 4K pages 40 * ECX -- L1 D-cache 41 * EDX -- L1 I-cache 42 * 43 * Function 8000.0006 L2 TLB/Cache Information 44 * EAX -- L2 TLB 2/4MB pages 45 * EBX -- L2 TLB 4K pages 46 * ECX -- L2 Unified cache 47 * EDX -- L3 Unified Cache 48 * 49 * Function 8000.0019 TLB 1GB Page Information 50 * EAX -- L1 1GB pages 51 * EBX -- L2 1GB pages 52 * ECX -- reserved 53 * EDX -- reserved 54 * 55 * Athlon, Duron: 56 * 57 * Function 8000.0005 L1 TLB/Cache Information 58 * EAX -- L1 TLB 2/4MB pages 59 * EBX -- L1 TLB 4K pages 60 * ECX -- L1 D-cache 61 * EDX -- L1 I-cache 62 * 63 * Function 8000.0006 L2 TLB/Cache Information 64 * EAX -- L2 TLB 2/4MB pages 65 * EBX -- L2 TLB 4K pages 66 * ECX -- L2 Unified cache 67 * EDX -- reserved 68 * 69 * K5, K6: 70 * 71 * Function 8000.0005 L1 TLB/Cache Information 72 * EAX -- reserved 73 * EBX -- TLB 4K pages 74 * ECX -- L1 D-cache 75 * EDX -- L1 I-cache 76 * 77 * K6-III: 78 * 79 * Function 8000.0006 L2 Cache Information 80 * EAX -- reserved 81 * EBX -- reserved 82 * ECX -- L2 Unified cache 83 * EDX -- reserved 84 */ 85 86/* L1 TLB 2/4MB pages */ 87#define AMD_L1_EAX_DTLB_ASSOC(x) (((x) >> 24) & 0xff) 88#define AMD_L1_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff) 89#define AMD_L1_EAX_ITLB_ASSOC(x) (((x) >> 8) & 0xff) 90#define AMD_L1_EAX_ITLB_ENTRIES(x) ( (x) & 0xff) 91 92/* L1 TLB 4K pages */ 93#define AMD_L1_EBX_DTLB_ASSOC(x) (((x) >> 24) & 0xff) 94#define AMD_L1_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff) 95#define AMD_L1_EBX_ITLB_ASSOC(x) (((x) >> 8) & 0xff) 96#define AMD_L1_EBX_ITLB_ENTRIES(x) ( (x) & 0xff) 97 98/* L1 Data Cache */ 99#define AMD_L1_ECX_DC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) 100#define AMD_L1_ECX_DC_ASSOC(x) (((x) >> 16) & 0xff) 101#define AMD_L1_ECX_DC_LPT(x) (((x) >> 8) & 0xff) 102#define AMD_L1_ECX_DC_LS(x) ( (x) & 0xff) 103 104/* L1 Instruction Cache */ 105#define AMD_L1_EDX_IC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) 106#define AMD_L1_EDX_IC_ASSOC(x) (((x) >> 16) & 0xff) 107#define AMD_L1_EDX_IC_LPT(x) (((x) >> 8) & 0xff) 108#define AMD_L1_EDX_IC_LS(x) ( (x) & 0xff) 109 110/* Note for L2 TLB -- if the upper 16 bits are 0, it is a unified TLB */ 111 112/* L2 TLB 2/4MB pages */ 113#define AMD_L2_EAX_DTLB_ASSOC(x) (((x) >> 28) & 0xf) 114#define AMD_L2_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff) 115#define AMD_L2_EAX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf) 116#define AMD_L2_EAX_IUTLB_ENTRIES(x) ( (x) & 0xfff) 117 118/* L2 TLB 4K pages */ 119#define AMD_L2_EBX_DTLB_ASSOC(x) (((x) >> 28) & 0xf) 120#define AMD_L2_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff) 121#define AMD_L2_EBX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf) 122#define AMD_L2_EBX_IUTLB_ENTRIES(x) ( (x) & 0xfff) 123 124/* L2 Cache */ 125#define AMD_L2_ECX_C_SIZE(x) ((((x) >> 16) & 0xffff) * 1024) 126#define AMD_L2_ECX_C_ASSOC(x) (((x) >> 12) & 0xf) 127#define AMD_L2_ECX_C_LPT(x) (((x) >> 8) & 0xf) 128#define AMD_L2_ECX_C_LS(x) ( (x) & 0xff) 129 130/* L3 Cache */ 131#define AMD_L3_EDX_C_SIZE(x) ((((x) >> 18) & 0xffff) * 1024 * 512) 132#define AMD_L3_EDX_C_ASSOC(x) (((x) >> 12) & 0xff) 133#define AMD_L3_EDX_C_LPT(x) (((x) >> 8) & 0xf) 134#define AMD_L3_EDX_C_LS(x) ( (x) & 0xff) 135 136/* L1 TLB 1GB pages */ 137#define AMD_L1_1GB_EAX_DTLB_ASSOC(x) (((x) >> 28) & 0xf) 138#define AMD_L1_1GB_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff) 139#define AMD_L1_1GB_EAX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf) 140#define AMD_L1_1GB_EAX_IUTLB_ENTRIES(x) ( (x) & 0xfff) 141 142/* L2 TLB 1GB pages */ 143#define AMD_L2_1GB_EBX_DUTLB_ASSOC(x) (((x) >> 28) & 0xf) 144#define AMD_L2_1GB_EBX_DUTLB_ENTRIES(x) (((x) >> 16) & 0xfff) 145#define AMD_L2_1GB_EBX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf) 146#define AMD_L2_1GB_EBX_IUTLB_ENTRIES(x) ( (x) & 0xfff) 147 148/* 149 * VIA Cache Info: 150 * 151 * Nehemiah (at least) 152 * 153 * Function 8000.0005 L1 TLB/Cache Information 154 * EAX -- reserved 155 * EBX -- L1 TLB 4K pages 156 * ECX -- L1 D-cache 157 * EDX -- L1 I-cache 158 * 159 * Function 8000.0006 L2 Cache Information 160 * EAX -- reserved 161 * EBX -- reserved 162 * ECX -- L2 Unified cache 163 * EDX -- reserved 164 */ 165 166/* L1 TLB 4K pages */ 167#define VIA_L1_EBX_DTLB_ASSOC(x) (((x) >> 24) & 0xff) 168#define VIA_L1_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff) 169#define VIA_L1_EBX_ITLB_ASSOC(x) (((x) >> 8) & 0xff) 170#define VIA_L1_EBX_ITLB_ENTRIES(x) ( (x) & 0xff) 171 172/* L1 Data Cache */ 173#define VIA_L1_ECX_DC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) 174#define VIA_L1_ECX_DC_ASSOC(x) (((x) >> 16) & 0xff) 175#define VIA_L1_ECX_DC_LPT(x) (((x) >> 8) & 0xff) 176#define VIA_L1_ECX_DC_LS(x) ( (x) & 0xff) 177 178/* L1 Instruction Cache */ 179#define VIA_L1_EDX_IC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) 180#define VIA_L1_EDX_IC_ASSOC(x) (((x) >> 16) & 0xff) 181#define VIA_L1_EDX_IC_LPT(x) (((x) >> 8) & 0xff) 182#define VIA_L1_EDX_IC_LS(x) ( (x) & 0xff) 183 184/* L2 Cache (pre-Nehemiah) */ 185#define VIA_L2_ECX_C_SIZE(x) ((((x) >> 24) & 0xff) * 1024) 186#define VIA_L2_ECX_C_ASSOC(x) (((x) >> 16) & 0xff) 187#define VIA_L2_ECX_C_LPT(x) (((x) >> 8) & 0xff) 188#define VIA_L2_ECX_C_LS(x) ( (x) & 0xff) 189 190/* L2 Cache (Nehemiah and newer) */ 191#define VIA_L2N_ECX_C_SIZE(x) ((((x) >> 16) & 0xffff) * 1024) 192#define VIA_L2N_ECX_C_ASSOC(x) (((x) >> 12) & 0xf) 193#define VIA_L2N_ECX_C_LPT(x) (((x) >> 8) & 0xf) 194#define VIA_L2N_ECX_C_LS(x) ( (x) & 0xff) 195 196#ifdef _KERNEL 197#define __CI_TBL(a,b,c,d,e,f) { a, b, c, d, e } 198#else 199#define __CI_TBL(a,b,c,d,e,f) { a, b, c, d, e, f } 200#endif 201 202/* 203 * XXX Currently organized mostly by cache type, but would be 204 * XXX easier to maintain if it were in descriptor type order. 205 */ 206#define INTEL_CACHE_INFO { \ 207__CI_TBL(CAI_ITLB, 0x01, 4, 32, 4 * 1024, NULL), \ 208__CI_TBL(CAI_ITLB, 0xb0, 4,128, 4 * 1024, NULL), \ 209__CI_TBL(CAI_ITLB2, 0x02, 0xff, 2, 4 * 1024 * 1024, NULL), \ 210__CI_TBL(CAI_DTLB, 0x03, 4, 64, 4 * 1024, NULL), \ 211__CI_TBL(CAI_DTLB, 0xb3, 4,128, 4 * 1024, NULL), \ 212__CI_TBL(CAI_DTLB, 0xb4, 4,256, 4 * 1024, NULL), \ 213__CI_TBL(CAI_DTLB2, 0x04, 4, 8, 4 * 1024 * 1024, NULL), \ 214__CI_TBL(CAI_DTLB2, 0x05, 4, 32, 4 * 1024 * 1024, NULL), \ 215__CI_TBL(CAI_ITLB, 0x50, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \ 216__CI_TBL(CAI_ITLB, 0x51, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\ 217__CI_TBL(CAI_ITLB, 0x52, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\ 218__CI_TBL(CAI_ITLB, 0x55, 0xff, 64, 4 * 1024, "2M/4M: 7 entries"), \ 219__CI_TBL(CAI_DTLB2, 0x56, 4, 16, 4 * 1024 * 1024, NULL), \ 220__CI_TBL(CAI_DTLB2, 0x57, 4, 16, 4 * 1024, NULL), \ 221__CI_TBL(CAI_DTLB, 0x5a, 0xff, 64, 4 * 1024, "2M/4M: 32 entries (L0)"), \ 222__CI_TBL(CAI_DTLB, 0x5b, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \ 223__CI_TBL(CAI_DTLB, 0x5c, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\ 224__CI_TBL(CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\ 225__CI_TBL(CAI_ITLB, 0xb1, 4, 64, 0, "8 2M/4 4M entries"), \ 226__CI_TBL(CAI_ITLB, 0xb2, 4, 64, 4 * 1024, NULL), \ 227__CI_TBL(CAI_ICACHE, 0x06, 4, 8 * 1024, 32, NULL), \ 228__CI_TBL(CAI_ICACHE, 0x08, 4, 16 * 1024, 32, NULL), \ 229__CI_TBL(CAI_ICACHE, 0x09, 4, 32 * 1024, 64, NULL), \ 230__CI_TBL(CAI_ICACHE, 0x30, 8, 32 * 1024, 64, NULL), \ 231__CI_TBL(CAI_DCACHE, 0x0a, 2, 8 * 1024, 32, NULL), \ 232__CI_TBL(CAI_DCACHE, 0x0c, 4, 16 * 1024, 32, NULL), \ 233__CI_TBL(CAI_DCACHE, 0x0d, 4, 16 * 1024, 32, NULL), \ 234__CI_TBL(CAI_L2CACHE, 0x21, 8, 256 * 1024, 64, NULL), /* L2 (MLC) */ \ 235__CI_TBL(CAI_L2CACHE, 0x39, 4, 128 * 1024, 64, NULL), \ 236__CI_TBL(CAI_L2CACHE, 0x3a, 6, 192 * 1024, 64, NULL), \ 237__CI_TBL(CAI_L2CACHE, 0x3b, 2, 128 * 1024, 64, NULL), \ 238__CI_TBL(CAI_L2CACHE, 0x3c, 4, 256 * 1024, 64, NULL), \ 239__CI_TBL(CAI_L2CACHE, 0x3d, 6, 384 * 1024, 64, NULL), \ 240__CI_TBL(CAI_L2CACHE, 0x3e, 4, 512 * 1024, 64, NULL), \ 241__CI_TBL(CAI_L2CACHE, 0x40, 0, 0, 0, "not present"), \ 242__CI_TBL(CAI_L2CACHE, 0x41, 4, 128 * 1024, 32, NULL), \ 243__CI_TBL(CAI_L2CACHE, 0x42, 4, 256 * 1024, 32, NULL), \ 244__CI_TBL(CAI_L2CACHE, 0x43, 4, 512 * 1024, 32, NULL), \ 245__CI_TBL(CAI_L2CACHE, 0x44, 4, 1 * 1024 * 1024, 32, NULL), \ 246__CI_TBL(CAI_L2CACHE, 0x45, 4, 2 * 1024 * 1024, 32, NULL), \ 247__CI_TBL(CAI_L2CACHE, 0x48, 12, 3 * 1024 * 1024, 64, NULL), \ 248 \ 249/* 0x49 Is L2 on Xeon MP (Family 0f, Model 06), L3 otherwise */ \ 250__CI_TBL(CAI_L2CACHE, 0x49, 16, 4 * 1024 * 1024, 64, NULL), \ 251__CI_TBL(CAI_L2CACHE, 0x4e, 24, 6 * 1024 * 1024, 64, NULL), \ 252__CI_TBL(CAI_DCACHE, 0x60, 8, 16 * 1024, 64, NULL), \ 253__CI_TBL(CAI_DCACHE, 0x66, 4, 8 * 1024, 64, NULL), \ 254__CI_TBL(CAI_DCACHE, 0x67, 4, 16 * 1024, 64, NULL), \ 255__CI_TBL(CAI_DCACHE, 0x2c, 8, 32 * 1024, 64, NULL), \ 256__CI_TBL(CAI_DCACHE, 0x68, 4, 32 * 1024, 64, NULL), \ 257__CI_TBL(CAI_ICACHE, 0x70, 8, 12 * 1024, 64, "12K uOp cache"), \ 258__CI_TBL(CAI_ICACHE, 0x71, 8, 16 * 1024, 64, "16K uOp cache"), \ 259__CI_TBL(CAI_ICACHE, 0x72, 8, 32 * 1024, 64, "32K uOp cache"), \ 260__CI_TBL(CAI_ICACHE, 0x73, 8, 64 * 1024, 64, "64K uOp cache"), \ 261__CI_TBL(CAI_L2CACHE, 0x78, 4, 1 * 1024 * 1024, 64, NULL), \ 262__CI_TBL(CAI_L2CACHE, 0x79, 8, 128 * 1024, 64, NULL), \ 263__CI_TBL(CAI_L2CACHE, 0x7a, 8, 256 * 1024, 64, NULL), \ 264__CI_TBL(CAI_L2CACHE, 0x7b, 8, 512 * 1024, 64, NULL), \ 265__CI_TBL(CAI_L2CACHE, 0x7c, 8, 1 * 1024 * 1024, 64, NULL), \ 266__CI_TBL(CAI_L2CACHE, 0x7d, 8, 2 * 1024 * 1024, 64, NULL), \ 267__CI_TBL(CAI_L2CACHE, 0x7f, 2, 512 * 1024, 64, NULL), \ 268__CI_TBL(CAI_L2CACHE, 0x82, 8, 256 * 1024, 32, NULL), \ 269__CI_TBL(CAI_L2CACHE, 0x83, 8, 512 * 1024, 32, NULL), \ 270__CI_TBL(CAI_L2CACHE, 0x84, 8, 1 * 1024 * 1024, 32, NULL), \ 271__CI_TBL(CAI_L2CACHE, 0x85, 8, 2 * 1024 * 1024, 32, NULL), \ 272__CI_TBL(CAI_L2CACHE, 0x86, 4, 512 * 1024, 64, NULL), \ 273__CI_TBL(CAI_L2CACHE, 0x87, 8, 1 * 1024 * 1024, 64, NULL), \ 274__CI_TBL(CAI_L3CACHE, 0x22, 0xff, 512 * 1024, 64, "sectored, 4-way "), \ 275__CI_TBL(CAI_L3CACHE, 0x23, 0xff, 1 * 1024 * 1024, 64, "sectored, 8-way "), \ 276__CI_TBL(CAI_L3CACHE, 0x25, 0xff, 2 * 1024 * 1024, 64, "sectored, 8-way "), \ 277__CI_TBL(CAI_L3CACHE, 0x29, 0xff, 4 * 1024 * 1024, 64, "sectored, 8-way "), \ 278__CI_TBL(CAI_L3CACHE, 0x46, 4, 4 * 1024 * 1024, 64, NULL), \ 279__CI_TBL(CAI_L3CACHE, 0x47, 8, 8 * 1024 * 1024, 64, NULL), \ 280__CI_TBL(CAI_L3CACHE, 0x49, 16, 4 * 1024 * 1024, 64, NULL), \ 281__CI_TBL(CAI_L3CACHE, 0x4a, 12, 6 * 1024 * 1024, 64, NULL), \ 282__CI_TBL(CAI_L3CACHE, 0x4b, 16, 8 * 1024 * 1024, 64, NULL), \ 283__CI_TBL(CAI_L3CACHE, 0x4c, 12,12 * 1024 * 1024, 64, NULL), \ 284__CI_TBL(CAI_L3CACHE, 0x4d, 16,16 * 1024 * 1024, 64, NULL), \ 285__CI_TBL(CAI_L3CACHE, 0xd0, 4, 512 * 1024, 64, NULL), \ 286__CI_TBL(CAI_L3CACHE, 0xd1, 4, 1 * 1024 * 1024, 64, NULL), \ 287__CI_TBL(CAI_L3CACHE, 0xd2, 4, 2 * 1024 * 1024, 64, NULL), \ 288__CI_TBL(CAI_L3CACHE, 0xd6, 8, 1 * 1024 * 1024, 64, NULL), \ 289__CI_TBL(CAI_L3CACHE, 0xd7, 8, 2 * 1024 * 1024, 64, NULL), \ 290__CI_TBL(CAI_L3CACHE, 0xd8, 8, 4 * 1024 * 1024, 64, NULL), \ 291__CI_TBL(CAI_L3CACHE, 0xdc, 12, 3 * 512 * 1024, 64, NULL), \ 292__CI_TBL(CAI_L3CACHE, 0xdd, 12, 3 * 1024 * 1024, 64, NULL), \ 293__CI_TBL(CAI_L3CACHE, 0xde, 12, 6 * 1024 * 1024, 64, NULL), \ 294__CI_TBL(CAI_L3CACHE, 0xe2, 16, 2 * 1024 * 1024, 64, NULL), \ 295__CI_TBL(CAI_L3CACHE, 0xe3, 16, 4 * 1024 * 1024, 64, NULL), \ 296__CI_TBL(CAI_L3CACHE, 0xe4, 16, 8 * 1024 * 1024, 64, NULL), \ 297__CI_TBL(CAI_L3CACHE, 0xea, 24,12 * 1024 * 1024, 64, NULL), \ 298__CI_TBL(CAI_L3CACHE, 0xeb, 24,24 * 1024 * 1024, 64, NULL), \ 299__CI_TBL(CAI_L3CACHE, 0xec, 24,24 * 1024 * 1024, 64, NULL), \ 300__CI_TBL(0, 0, 0, 0, 0, NULL) \ 301} 302 303#define AMD_L2CACHE_INFO { \ 304__CI_TBL(0, 0x01, 1, 0, 0, NULL), \ 305__CI_TBL(0, 0x02, 2, 0, 0, NULL), \ 306__CI_TBL(0, 0x04, 4, 0, 0, NULL), \ 307__CI_TBL(0, 0x06, 8, 0, 0, NULL), \ 308__CI_TBL(0, 0x08, 16, 0, 0, NULL), \ 309__CI_TBL(0, 0x0a, 32, 0, 0, NULL), \ 310__CI_TBL(0, 0x0b, 48, 0, 0, NULL), \ 311__CI_TBL(0, 0x0c, 64, 0, 0, NULL), \ 312__CI_TBL(0, 0x0d, 96, 0, 0, NULL), \ 313__CI_TBL(0, 0x0e, 128, 0, 0, NULL), \ 314__CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \ 315__CI_TBL(0, 0x00, 0, 0, 0, NULL) \ 316} 317 318#define AMD_L3CACHE_INFO { \ 319__CI_TBL(0, 0x01, 1, 0, 0, NULL), \ 320__CI_TBL(0, 0x02, 2, 0, 0, NULL), \ 321__CI_TBL(0, 0x04, 4, 0, 0, NULL), \ 322__CI_TBL(0, 0x06, 8, 0, 0, NULL), \ 323__CI_TBL(0, 0x08, 16, 0, 0, NULL), \ 324__CI_TBL(0, 0x0a, 32, 0, 0, NULL), \ 325__CI_TBL(0, 0x0b, 48, 0, 0, NULL), \ 326__CI_TBL(0, 0x0c, 64, 0, 0, NULL), \ 327__CI_TBL(0, 0x0d, 96, 0, 0, NULL), \ 328__CI_TBL(0, 0x0e, 128, 0, 0, NULL), \ 329__CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \ 330__CI_TBL(0, 0x00, 0, 0, 0, NULL) \ 331} 332 333#endif /* _X86_CACHEINFO_H_ */ 334