The Alpha AXP Architecture Reference Manual is explcit that the only
valid bits in the PSL are the IPL and USER bits, the latter of which
will always be clear when in the kernel, and that all other bits MBZ.
So, when reading the PSL to get the current IPL, don't bother masking
with ALPHA_PSL_IPL_MASK.

Reduce code duplication when setting up the interrupt handler data
structures:
- alpha_shared_intr_alloc() no longer takes a "string length" argument,
and just uses kmem_asprintf() to create an "irq %u" string by default.
This is suitable for nearly every caller.
- Add a alpha_shared_intr_set_string() that allows callers to override
the default IRQ description string.
- Related: make alpha_shared_intr_string() return a const char *, since
no callers should need to modify the string directly now.
- Re-factor PCI shared interrupt structure allocation / initialization
into a new alpha_pci_intr_alloc(), which is suitable for nearly every
Alpha PCI platform. Callers are expected to first have initialized
the interrupt hardware to the quiescent state.

Adjust various call sites of above functions to account for changes,
even if they are not able to use the newly re-factored code.

Fix cycle counter-based time keeping on Alpha in MP environments by using
a simpler calibration algorithm for the CC timecounter. Proposed in 2018
by Naruaki Etomi:

https://mail-index.netbsd.org/tech-kern/2018/01/14/msg022940.html

This patch is largely based on the proposed change, but avoids changing
any other timecounter logic, and re-factors things a bit to keep them
as MI as possible.

Implement cpu_intr_redistribute() for Tusnami/Titan systems.

Changes to make interrupt {,dis}establish MP-safe on Alpha:
- Protect all of the system interrupt linkage with the cpu_lock mutex.
- Re-order some of the stores to the SCB vector table to make it safe
in the face of lockless interrupt dispatch.
- Add a framework for routing interrupts to specific CPUs. Interrupts
are still funneled only to the primary CPU, but that will change for
some systems soon. Ensure that interrupt handler lists are manipulated
only on the CPUs that handle that specific interrupt source. This required
a re-factor of the alpha_shared_intr_*() family of functions.
- Enable __HAVE_INTR_CONTROL, although interrupt redistribution is still
a no-op.
- Reduce code duplication in the Jenson direct-SCB interrupt handlers.

Use a wrapper to acquire the kernel lock for non-MPSAFE interrupts,
rather than doing it in alpha_shared_intr_establish() directly.

Changes to make MPSAFE interrupts work on Alpha:

- Remove the ipl argument to scb_set() and the associated array of
"mpsafe" booleans initialized based on the ipl. It was bogus
anyway; all IPL_{BIO,NET,TTY}, etc. values are aliases of IPL_VM,
and for all practical purposes, there is really only one device
interrrupt level on Alpha anyway. Intead, we now treat all dispatches
from the SCB vector table as MP-safe, and it is now the handler for
that vector who is responsible for acquiring the KERNEL_LOCK if needed.

- Update the direct interrupt vector handlers in jensenio and TURBOchannel
to acquire the KERNEL_LOCK.

- Introduce a new ALPHA_INTR_MPSAFE flag, and add a flags argument to
alpha_shared_intr_establish(). When it is set, indicate that the
handler is MP-safe. Update alpha_shared_intr_dispatch() to pay
attention and acquire the KERNEL_LOCK (or not) as indicated.

- Re-factor all of the PCI interrupt handling, providing "generic PCI"
"PCI interrupts through ISA IRQs" implementations to significantly
reduce code duplication. Supplement the PCI chipset tag with more
info to facilitate this, and make the PCI interrupt-related routines
take a pci_chipset_tag_t argument rather than a void * argument.

- Because PCI interrupts on KN8AE are dispatched directly from the
SCB, provide a wrapper for non-MPSAFE interrupt handlers that
acquires the KERNEL_LOCK.

- Change the pci_intr_handle_t type to be a struct rather than an
integer type in order to catch any direct use of it as a value.
Add a set of functions to interact with pci_intr_handle_t, including
setting interrupt flags.

- Implement pci_intr_setattr() so that the PCI_INTR_MPSAFE attribute
can be set on a pci_intr_handle_t.

- While I'm here, make all of the MI PCI back-end operations call
through real functions rather than hopping directly through function
pointers in the chipset tag.

This change looks a lot bigger than it really is because of the re-factor
in the plethora of model-specific PCI interrupt back-ends. The KN8AE,
KN300, and T2/T3/T4 (Sable) are largely un-changed.

Move softintr bits into <machine/intr.h> and define ALPHA_ALL_SOFTINTS
for locore.s

Reduce the __HAVE_FAST_SOFTINTS #ifdef perimeter.

Implement fast soft interrupts for Alpha. It's not yet enabled, because
there is a bug lurking that causes problems when user space starts up,
so we'll stick with the slow path for now.

Track the SSIR per-cpu, rather than globally.

- Document all of the various interrupt levels in the Processor Stataus
register, and provide symbolic names for them as well.
- Use ALPHA_PSL_IPL_* values directly for IPL_*.

- Centralize per-CPU pmap initialization into a new pmap_init_cpu()
function. Call in from pmap_bootstrap() for the boot CPU, and
from cpu_hatch() for secondaary CPUs.
- Eliminiate the dedicated I-stream memory barrier IPI; handle it all from
the TLB shootdown IPI. Const poison, and add some additional memory
barriers and a TBIA to the PAUSE IPI.
- Completly rewrite TLB management in the alpha pmap module, borrowing
somoe ideas from the x86 pmap and adapting them to the alpha environment.
See the comments for theory of operation. Add a bunch of stats that
can be reported (disabled by default).
- Add some additional symbol decorations to improve cache behavior on
MP systems. Ensure coherency unit alignment for several structures
in the pmap module. Use hashed locks for pmap structures.
- Start out all new processes on the kernel page tables until their
first trip though pmap_activate() to avoid the potential of polluting
the current ASN in TLB with cross-process mappings.

fix types.

branches: 1.71.4; 1.71.8;
Implement MI IPI interface with cross-call support.

branches: 1.70.6; 1.70.20;
Do a minor cleanup of alpha (this will make applying pullups post branching
easier).
u_int{8,16,32,64}_t -> uint{*}_t
Change all old-style definitions to C89 prototypes.
Whitespace cleanup.
Constification in db_disasm.c

branches: 1.69.2; 1.69.6;
Switch alpha to use PCU to manage the FPU.
Tested by mhitch and review by rmind.

branches: 1.68.6;
Implement high priority (XC_HIGHPRI) xcall(9) mechanism - a facility
to execute functions from software interrupt context, at SOFTINT_CLOCK.
Functions must be lightweight. Will be used for passive serialization.

OK ad@.

branches: 1.67.2; 1.67.4;
Garbage-collect pmap_do_reactivate() and the associated IPI -- nothing has
used them for a long time.

Remove clause 3 and 4 from TNF licenses

branches: 1.65.2;
This file needs <machine/cpu.h> included, for the ALPHA_PSL_IPL_*
constants it uses.

branches: 1.64.2;
Finish moving alpha over to the MI atomic ops.

branches: 1.63.2; 1.63.6;
More header file cleanup.

branches: 1.62.6;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

branches: 1.61.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.60.8; 1.60.10;
Fix alpha build after idlelwp merge. I don't know why machine/cpu.h was
added here, but it does not seem to be needed now, and was resulting in a
circular dependency when sys/sched.h was changed in the yamt-idlelpw branch.

branches: 1.59.6; 1.59.8; 1.59.12; 1.59.14;
Remove spllowersoftclock() and CLKF_BASEPRI(), and always dispatch callouts
via a soft interrupt. In the near future, softclock will be run from process
context.

Merge newlock2 to head.

Define ipl_cookie_t._psl as uint8_t so that it can be packed into a
word with other seldomly written fields.

merge yamt-splraiseipl branch.

- finish implementing splraiseipl (and makeiplcookie).
http://mail-index.NetBSD.org/tech-kern/2006/07/01/0000.html
- complete workqueue(9) and fix its ipl problem, which is reported
to cause audio skipping.
- fix netbt (at least compilation problems) for some ports.
- fix PR/33218.

branches: 1.55.14; 1.55.16;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

branches: 1.54.2; 1.54.4; 1.54.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

- use sys/spl.h.
- add some IPL_ definitions.

pull splraiseipl() from newlock branch.

branches: 1.50.2; 1.50.4;
- Add a alpha_shared_intr_reset_strays() function that resets the stray
interrupt counter for a given shared interrupt descriptor.
- When an interrupt is successfully handled, reset the strays counter,
thus preventing a "slow leak" from eventually shutting off the interrupt
vector. Idea taken from pci_kn300.c (which was changed to use the new
alpha_shared_intr_reset_strays() function).

branches: 1.49.2; 1.49.10; 1.49.22; 1.49.28; 1.49.30; 1.49.36;
Rework the interrupt code, shaving some cycles off in the process.
Rather than an "iointr" routine that decomposes a vector into an
IRQ, we maintain a vector table directly, hooking up each "iointr"
routine at the correct vector. This also allows us to hook device
interrupts up to specific vectors (c.f. Jensen).

We can shave even more cycles off, here, and I will, but it requires
some changes to the alpha_shared_intr stuff.

- Tweak the pmap locking protocol slightly -- require that a pmap must
be locked before it can be marked as `active' on a processor.
- Require that pmaps other than the kernel pmap be locked when they
are passed to pmap_tlb_shootdown(). This, combined with the locking
protocol tweak, allow us to get a consistent view of `activeness' of
a pmap, which means we can optmize away a lot of TLB shootdown traffic
for user pmaps.
- Borrow an idea from the i386mp branch; use the normal SHOOTDOWN IPI
to deal with hitting the entire TLB, and garbage-collect the TBIA
and TBIAP IPIs.

branches: 1.47.2;
Add a microtime() implementation that interpolates between ticks
using the cycle counter. MP-safeness is achieved by giving each
CPU its own PCC frequency variables, and kicking the non-primary
processors via an IPI once per second.

Based on the sample code from David Mills' "A Kernel Model for
Precision Timekeeping".

Add splipi() to block interprocessor interrupts (which come in at IPL 5).

pmap_asn_alloc(): In a multiprocessor configuration, it's possible
to arrive here referencing the kernel_lev1map without having the
RESERVED ASN -- another CPU may have caused pmap_lev1map_destroy()
to be called, and that routine only invalidates the ASN for the
CPU that called it. So, in the MULTIPROCESSOR case, simply assign
the RESERVED ASN if we reference the kernel_lev1map rather than
asserting that we already have the RESERVED ASN. Thanks to Bill
Sommerfeld for helping me track down the problem.

Also add a new IPI that causes a CPU to re-activate its address
space if the pmap it's using changes level 1 maps (this probably
won't happen very often, but it's correct to have it).

This makes Alpha MP kernels boot multiuser. In fact, this commit
is being made from my dual-CPU AlphaServer 1200 running an MP kernel.

In splx(), don't call spl0() unless the ssir != 0.

Clean up soft interrupt related stuff a bit.

Change the softintr implementation to be a bit more cache friendly
(though, sigh, slightly more expensive at softintr_schedule() time).

Remove the use of splimp() from the NetBSD kernel. splnet()
and only splnet() is allowed for the protection of data structures
used by network devices.

branches: 1.40.2;
Make softclock a generic soft interrupt of the API is available,
adding the requisite void * argument to softclock().

Rename __GENERIC_SOFT_INTERRUPTS to __HAVE_GENERIC_SOFT_INTERRUPTS,
and place the definition in <machine/types.h>. This can now be used
as a flag to indicate whether or not <machine/intr.h> can be included
to get the generic soft interrupt API.

Make sure everybody has an splvm() and equate it with splimp() (splimp()
is the historical name for this interrupt level, and the historical name
is going to go away in the near future).

Several changes, which get us generally further along with
multiprocessor support:
- Implement MP-safe halt.
- Make the FPU saving code more like Bill's on the i386 MP branch.
XXX This code will no doubt be revisited again.
- Pass the cpu_info and trapframe to IPI handlers, saving some work
in the handlers themselves, and also making it possible for the
"pause" handler to reference register state for DDB.
- Add "machine cpu" to DDB, making it possible to reference other
CPUs registers (and thus get e.g. a traceback) from whichever
CPU is actually running the debugger.
- Garbage-collect "machine halt" and "machine reboot" DDB commands.
They don't have a prayer of working properly in multiprocessor
kernels, and didn't really work all that well in uniprocessor kernels.

Move IPI processing into a separate function.

Count individual interprocessor interrupts -- it's good to know where
they all come from.

Add spllock(). See spl(9) for details.

Add experimental code for pausing other CPUs upon a CPU's
entry into the debugger. While I'm here, add splsched()
as per spl(9).

Implement MP-safe lazy FP context switching, modeled on the
way Bill Sommerfeld implemented it for x86 (and bug fixes
fed back to Bill :-)

Add alpha_multicast_ipi().

Whitespace police.

make spl0() and spllowersoftclock() return void. Also, move spl0()
prototype from param.h to intr.h. (there were some big XXXs in param.h
that said to do that, and intr.h is included by param.h, so...)

Switch to the new `evcnt' mechanism for counting interrupts. Maintain
a per-CPU interrupt counter for clock, device, and interprocessor
interrupts.

Un-__P'ify kernel prototypes.

- Clean up clock interrupt code a bit, and provide a CPU_IS_PRIMARY()
macro in the MULTIPROCESSOR case (hardclock() wants it).
- Implement __GENERIC_SOFT_INTERRUPTS, and redefine the legacy
software interrupts in terms of it. Garbage-collect setsoftserial().

branches: 1.25.2;
Rename the atomic operations to have generic machine-independent
names, and define __HAVE_ATOMIC_OPERATIONS to indicate their
existence.

Point back to the alpha_shared_intr in the intrhand structure. This
allows platform-specific code to access the `intr_private' data via
the intrhand structure.

Move atomic operations into <machine/atomic.h>, and make them in-line
assembly, rather than function calls.

...except alpha_atomic_testset_l(), which will go away completely once
I commit the new <machine/lock.h>.

- Fix a botch in the IPI bitmasks (they were right-shifted by 1), and
add an IPI which causes the target CPU to perform AST processing when
it returns to userspace.
- Add a way to get/set a private pointer in the shared interrupt header.

branches: 1.21.2; 1.21.8;
Use atomic operations to manipulate the SSIR, and fix a problem introduced
with the spllowersoftclock() changes where more interrupts than necessary
were blocked while software interrupts were being processed.

Change the semantics of splsoftclock() to be like other spl*() functions,
that is priority is rasied. Add a new spllowersoftclock() to provide the
atomic drop-to-softclock semantics that the old splsoftclock() provided,
and update calls accordingly.

This fixes a problem with using the "rnd" pseudo-device from within
interrupt context to extract random data (e.g. from within the softnet
interrupt) where doing so would incorrectly unblock interrupts (causing
all sorts of lossage).

XXX 4 platforms do not have priority-raising capability: newsmips, sparc,
XXX sparc64, and VAX. This platforms still have this bug until their
XXX spl*() functions are fixed.

Restructure the IPI code a little, allowing multiple IPIs to be sent at
once. Add a way to broadcast an IPI to all processors (except the sender,
obviously). Add an IPI for TLB shootdown.

Add basic interprocessor interrupt sending and receiving code. Current
IPI functions: HALT, IMB, TBIA, TBIAP.

XXX HALT is not yet implemented, it's just a stub.

Minor style tweaks.

Add softserial to the alpha port. This significantly improved PPP
throughput on com ports.

Implement alpha_shared_intr_disestablish(). Simply removes the handler
fromthe list, allowing the caller to manipulate the sharing type,
if appropriate.

Switching dev/ic/lpt.c to use spllpt() instead of spltty(). It doesn't use
tty structures, and on some machines (namely the DraCo internal lpt, and some
multi-i/o boards for Amigas and DraCos), tying spltty to the pretty high printer
interupt level would hurt serial performance.

On all affected ports but Amiga, spllpt() has been defined in machine/intr.h
to be spltty(), thus preserving old behaviour. Portmasters are encouraged to
change is, if they feel something else is better (e.g., one of its own were
possible).

On second thought, call that like the rest of the shared intr functions.

Define a macro to test if a shared interrupt should be disabled after
a stray has occurred.

Protect userland applications from the inline splraise function.

branches: 1.10.6;
mark prototypes for static inline functions as possibly unused
(with __attribute__ ((unused))), to avoid generating warnings when
compiling without optimization but with the default warning flags.

two more slight bogons

actually, declare _splraise() as an inline function, because:
(1) it was using 'max', and some functions use a variable
of that name (*sigh*), and
(2) that makes it easier to be a bit trickier, and only call
swpipl if changing the IPL.

parens around macro arg (this is an old one)

make sure that splnet(), splbio(), splimp(), spltty(), splclock(),
splstatclock(), and splhigh() all _raise_ the IPL. (splhigh() is _not_
the highest possible IPL; mcheck is...)

clean up NetBSD RCS ID strings

branches: 1.4.2;
kill siroff() and resturcture do_sir() to be cleaner and more correct.

implement a (hack-ish) set of routines to do common chained-interrupt
handler management. It's nasty, but three slightly different copies of
the code is worse.

various cleanup, move setsoft* and spl* into intr.h.

the Alpha implementation of <machine/intr.h>

Reduce code duplication when setting up the interrupt handler data
structures:
- alpha_shared_intr_alloc() no longer takes a "string length" argument,
and just uses kmem_asprintf() to create an "irq %u" string by default.
This is suitable for nearly every caller.
- Add a alpha_shared_intr_set_string() that allows callers to override
the default IRQ description string.
- Related: make alpha_shared_intr_string() return a const char *, since
no callers should need to modify the string directly now.
- Re-factor PCI shared interrupt structure allocation / initialization
into a new alpha_pci_intr_alloc(), which is suitable for nearly every
Alpha PCI platform. Callers are expected to first have initialized
the interrupt hardware to the quiescent state.

Adjust various call sites of above functions to account for changes,
even if they are not able to use the newly re-factored code.

Fix cycle counter-based time keeping on Alpha in MP environments by using
a simpler calibration algorithm for the CC timecounter. Proposed in 2018
by Naruaki Etomi:

https://mail-index.netbsd.org/tech-kern/2018/01/14/msg022940.html

This patch is largely based on the proposed change, but avoids changing
any other timecounter logic, and re-factors things a bit to keep them
as MI as possible.

Implement cpu_intr_redistribute() for Tusnami/Titan systems.

Changes to make interrupt {,dis}establish MP-safe on Alpha:
- Protect all of the system interrupt linkage with the cpu_lock mutex.
- Re-order some of the stores to the SCB vector table to make it safe
in the face of lockless interrupt dispatch.
- Add a framework for routing interrupts to specific CPUs. Interrupts
are still funneled only to the primary CPU, but that will change for
some systems soon. Ensure that interrupt handler lists are manipulated
only on the CPUs that handle that specific interrupt source. This required
a re-factor of the alpha_shared_intr_*() family of functions.
- Enable __HAVE_INTR_CONTROL, although interrupt redistribution is still
a no-op.
- Reduce code duplication in the Jenson direct-SCB interrupt handlers.

Use a wrapper to acquire the kernel lock for non-MPSAFE interrupts,
rather than doing it in alpha_shared_intr_establish() directly.

Changes to make MPSAFE interrupts work on Alpha:

- Remove the ipl argument to scb_set() and the associated array of
"mpsafe" booleans initialized based on the ipl. It was bogus
anyway; all IPL_{BIO,NET,TTY}, etc. values are aliases of IPL_VM,
and for all practical purposes, there is really only one device
interrrupt level on Alpha anyway. Intead, we now treat all dispatches
from the SCB vector table as MP-safe, and it is now the handler for
that vector who is responsible for acquiring the KERNEL_LOCK if needed.

- Update the direct interrupt vector handlers in jensenio and TURBOchannel
to acquire the KERNEL_LOCK.

- Introduce a new ALPHA_INTR_MPSAFE flag, and add a flags argument to
alpha_shared_intr_establish(). When it is set, indicate that the
handler is MP-safe. Update alpha_shared_intr_dispatch() to pay
attention and acquire the KERNEL_LOCK (or not) as indicated.

- Re-factor all of the PCI interrupt handling, providing "generic PCI"
"PCI interrupts through ISA IRQs" implementations to significantly
reduce code duplication. Supplement the PCI chipset tag with more
info to facilitate this, and make the PCI interrupt-related routines
take a pci_chipset_tag_t argument rather than a void * argument.

- Because PCI interrupts on KN8AE are dispatched directly from the
SCB, provide a wrapper for non-MPSAFE interrupt handlers that
acquires the KERNEL_LOCK.

- Change the pci_intr_handle_t type to be a struct rather than an
integer type in order to catch any direct use of it as a value.
Add a set of functions to interact with pci_intr_handle_t, including
setting interrupt flags.

- Implement pci_intr_setattr() so that the PCI_INTR_MPSAFE attribute
can be set on a pci_intr_handle_t.

- While I'm here, make all of the MI PCI back-end operations call
through real functions rather than hopping directly through function
pointers in the chipset tag.

This change looks a lot bigger than it really is because of the re-factor
in the plethora of model-specific PCI interrupt back-ends. The KN8AE,
KN300, and T2/T3/T4 (Sable) are largely un-changed.

Move softintr bits into <machine/intr.h> and define ALPHA_ALL_SOFTINTS
for locore.s

Reduce the __HAVE_FAST_SOFTINTS #ifdef perimeter.

Implement fast soft interrupts for Alpha. It's not yet enabled, because
there is a bug lurking that causes problems when user space starts up,
so we'll stick with the slow path for now.

Track the SSIR per-cpu, rather than globally.

- Document all of the various interrupt levels in the Processor Stataus
register, and provide symbolic names for them as well.
- Use ALPHA_PSL_IPL_* values directly for IPL_*.

- Centralize per-CPU pmap initialization into a new pmap_init_cpu()
function. Call in from pmap_bootstrap() for the boot CPU, and
from cpu_hatch() for secondaary CPUs.
- Eliminiate the dedicated I-stream memory barrier IPI; handle it all from
the TLB shootdown IPI. Const poison, and add some additional memory
barriers and a TBIA to the PAUSE IPI.
- Completly rewrite TLB management in the alpha pmap module, borrowing
somoe ideas from the x86 pmap and adapting them to the alpha environment.
See the comments for theory of operation. Add a bunch of stats that
can be reported (disabled by default).
- Add some additional symbol decorations to improve cache behavior on
MP systems. Ensure coherency unit alignment for several structures
in the pmap module. Use hashed locks for pmap structures.
- Start out all new processes on the kernel page tables until their
first trip though pmap_activate() to avoid the potential of polluting
the current ASN in TLB with cross-process mappings.

fix types.

branches: 1.71.4; 1.71.8;
Implement MI IPI interface with cross-call support.

branches: 1.70.6; 1.70.20;
Do a minor cleanup of alpha (this will make applying pullups post branching
easier).
u_int{8,16,32,64}_t -> uint{*}_t
Change all old-style definitions to C89 prototypes.
Whitespace cleanup.
Constification in db_disasm.c

branches: 1.69.2; 1.69.6;
Switch alpha to use PCU to manage the FPU.
Tested by mhitch and review by rmind.

branches: 1.68.6;
Implement high priority (XC_HIGHPRI) xcall(9) mechanism - a facility
to execute functions from software interrupt context, at SOFTINT_CLOCK.
Functions must be lightweight. Will be used for passive serialization.

OK ad@.

branches: 1.67.2; 1.67.4;
Garbage-collect pmap_do_reactivate() and the associated IPI -- nothing has
used them for a long time.

Remove clause 3 and 4 from TNF licenses

branches: 1.65.2;
This file needs <machine/cpu.h> included, for the ALPHA_PSL_IPL_*
constants it uses.

branches: 1.64.2;
Finish moving alpha over to the MI atomic ops.

branches: 1.63.2; 1.63.6;
More header file cleanup.

branches: 1.62.6;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

branches: 1.61.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.60.8; 1.60.10;
Fix alpha build after idlelwp merge. I don't know why machine/cpu.h was
added here, but it does not seem to be needed now, and was resulting in a
circular dependency when sys/sched.h was changed in the yamt-idlelpw branch.

branches: 1.59.6; 1.59.8; 1.59.12; 1.59.14;
Remove spllowersoftclock() and CLKF_BASEPRI(), and always dispatch callouts
via a soft interrupt. In the near future, softclock will be run from process
context.

Merge newlock2 to head.

Define ipl_cookie_t._psl as uint8_t so that it can be packed into a
word with other seldomly written fields.

merge yamt-splraiseipl branch.

- finish implementing splraiseipl (and makeiplcookie).
http://mail-index.NetBSD.org/tech-kern/2006/07/01/0000.html
- complete workqueue(9) and fix its ipl problem, which is reported
to cause audio skipping.
- fix netbt (at least compilation problems) for some ports.
- fix PR/33218.

branches: 1.55.14; 1.55.16;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

branches: 1.54.2; 1.54.4; 1.54.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

- use sys/spl.h.
- add some IPL_ definitions.

pull splraiseipl() from newlock branch.

branches: 1.50.2; 1.50.4;
- Add a alpha_shared_intr_reset_strays() function that resets the stray
interrupt counter for a given shared interrupt descriptor.
- When an interrupt is successfully handled, reset the strays counter,
thus preventing a "slow leak" from eventually shutting off the interrupt
vector. Idea taken from pci_kn300.c (which was changed to use the new
alpha_shared_intr_reset_strays() function).

branches: 1.49.2; 1.49.10; 1.49.22; 1.49.28; 1.49.30; 1.49.36;
Rework the interrupt code, shaving some cycles off in the process.
Rather than an "iointr" routine that decomposes a vector into an
IRQ, we maintain a vector table directly, hooking up each "iointr"
routine at the correct vector. This also allows us to hook device
interrupts up to specific vectors (c.f. Jensen).

We can shave even more cycles off, here, and I will, but it requires
some changes to the alpha_shared_intr stuff.

- Tweak the pmap locking protocol slightly -- require that a pmap must
be locked before it can be marked as `active' on a processor.
- Require that pmaps other than the kernel pmap be locked when they
are passed to pmap_tlb_shootdown(). This, combined with the locking
protocol tweak, allow us to get a consistent view of `activeness' of
a pmap, which means we can optmize away a lot of TLB shootdown traffic
for user pmaps.
- Borrow an idea from the i386mp branch; use the normal SHOOTDOWN IPI
to deal with hitting the entire TLB, and garbage-collect the TBIA
and TBIAP IPIs.

branches: 1.47.2;
Add a microtime() implementation that interpolates between ticks
using the cycle counter. MP-safeness is achieved by giving each
CPU its own PCC frequency variables, and kicking the non-primary
processors via an IPI once per second.

Based on the sample code from David Mills' "A Kernel Model for
Precision Timekeeping".

Add splipi() to block interprocessor interrupts (which come in at IPL 5).

pmap_asn_alloc(): In a multiprocessor configuration, it's possible
to arrive here referencing the kernel_lev1map without having the
RESERVED ASN -- another CPU may have caused pmap_lev1map_destroy()
to be called, and that routine only invalidates the ASN for the
CPU that called it. So, in the MULTIPROCESSOR case, simply assign
the RESERVED ASN if we reference the kernel_lev1map rather than
asserting that we already have the RESERVED ASN. Thanks to Bill
Sommerfeld for helping me track down the problem.

Also add a new IPI that causes a CPU to re-activate its address
space if the pmap it's using changes level 1 maps (this probably
won't happen very often, but it's correct to have it).

This makes Alpha MP kernels boot multiuser. In fact, this commit
is being made from my dual-CPU AlphaServer 1200 running an MP kernel.

In splx(), don't call spl0() unless the ssir != 0.

Clean up soft interrupt related stuff a bit.

Change the softintr implementation to be a bit more cache friendly
(though, sigh, slightly more expensive at softintr_schedule() time).

Remove the use of splimp() from the NetBSD kernel. splnet()
and only splnet() is allowed for the protection of data structures
used by network devices.

branches: 1.40.2;
Make softclock a generic soft interrupt of the API is available,
adding the requisite void * argument to softclock().

Rename __GENERIC_SOFT_INTERRUPTS to __HAVE_GENERIC_SOFT_INTERRUPTS,
and place the definition in <machine/types.h>. This can now be used
as a flag to indicate whether or not <machine/intr.h> can be included
to get the generic soft interrupt API.

Make sure everybody has an splvm() and equate it with splimp() (splimp()
is the historical name for this interrupt level, and the historical name
is going to go away in the near future).

Several changes, which get us generally further along with
multiprocessor support:
- Implement MP-safe halt.
- Make the FPU saving code more like Bill's on the i386 MP branch.
XXX This code will no doubt be revisited again.
- Pass the cpu_info and trapframe to IPI handlers, saving some work
in the handlers themselves, and also making it possible for the
"pause" handler to reference register state for DDB.
- Add "machine cpu" to DDB, making it possible to reference other
CPUs registers (and thus get e.g. a traceback) from whichever
CPU is actually running the debugger.
- Garbage-collect "machine halt" and "machine reboot" DDB commands.
They don't have a prayer of working properly in multiprocessor
kernels, and didn't really work all that well in uniprocessor kernels.

Move IPI processing into a separate function.

Count individual interprocessor interrupts -- it's good to know where
they all come from.

Add spllock(). See spl(9) for details.

Add experimental code for pausing other CPUs upon a CPU's
entry into the debugger. While I'm here, add splsched()
as per spl(9).

Implement MP-safe lazy FP context switching, modeled on the
way Bill Sommerfeld implemented it for x86 (and bug fixes
fed back to Bill :-)

Add alpha_multicast_ipi().

Whitespace police.

make spl0() and spllowersoftclock() return void. Also, move spl0()
prototype from param.h to intr.h. (there were some big XXXs in param.h
that said to do that, and intr.h is included by param.h, so...)

Switch to the new `evcnt' mechanism for counting interrupts. Maintain
a per-CPU interrupt counter for clock, device, and interprocessor
interrupts.

Un-__P'ify kernel prototypes.

- Clean up clock interrupt code a bit, and provide a CPU_IS_PRIMARY()
macro in the MULTIPROCESSOR case (hardclock() wants it).
- Implement __GENERIC_SOFT_INTERRUPTS, and redefine the legacy
software interrupts in terms of it. Garbage-collect setsoftserial().

branches: 1.25.2;
Rename the atomic operations to have generic machine-independent
names, and define __HAVE_ATOMIC_OPERATIONS to indicate their
existence.

Point back to the alpha_shared_intr in the intrhand structure. This
allows platform-specific code to access the `intr_private' data via
the intrhand structure.

Move atomic operations into <machine/atomic.h>, and make them in-line
assembly, rather than function calls.

...except alpha_atomic_testset_l(), which will go away completely once
I commit the new <machine/lock.h>.

- Fix a botch in the IPI bitmasks (they were right-shifted by 1), and
add an IPI which causes the target CPU to perform AST processing when
it returns to userspace.
- Add a way to get/set a private pointer in the shared interrupt header.

branches: 1.21.2; 1.21.8;
Use atomic operations to manipulate the SSIR, and fix a problem introduced
with the spllowersoftclock() changes where more interrupts than necessary
were blocked while software interrupts were being processed.

Change the semantics of splsoftclock() to be like other spl*() functions,
that is priority is rasied. Add a new spllowersoftclock() to provide the
atomic drop-to-softclock semantics that the old splsoftclock() provided,
and update calls accordingly.

This fixes a problem with using the "rnd" pseudo-device from within
interrupt context to extract random data (e.g. from within the softnet
interrupt) where doing so would incorrectly unblock interrupts (causing
all sorts of lossage).

XXX 4 platforms do not have priority-raising capability: newsmips, sparc,
XXX sparc64, and VAX. This platforms still have this bug until their
XXX spl*() functions are fixed.

Restructure the IPI code a little, allowing multiple IPIs to be sent at
once. Add a way to broadcast an IPI to all processors (except the sender,
obviously). Add an IPI for TLB shootdown.

Add basic interprocessor interrupt sending and receiving code. Current
IPI functions: HALT, IMB, TBIA, TBIAP.

XXX HALT is not yet implemented, it's just a stub.

Minor style tweaks.

Add softserial to the alpha port. This significantly improved PPP
throughput on com ports.

Implement alpha_shared_intr_disestablish(). Simply removes the handler
fromthe list, allowing the caller to manipulate the sharing type,
if appropriate.

Switching dev/ic/lpt.c to use spllpt() instead of spltty(). It doesn't use
tty structures, and on some machines (namely the DraCo internal lpt, and some
multi-i/o boards for Amigas and DraCos), tying spltty to the pretty high printer
interupt level would hurt serial performance.

On all affected ports but Amiga, spllpt() has been defined in machine/intr.h
to be spltty(), thus preserving old behaviour. Portmasters are encouraged to
change is, if they feel something else is better (e.g., one of its own were
possible).

On second thought, call that like the rest of the shared intr functions.

Define a macro to test if a shared interrupt should be disabled after
a stray has occurred.

Protect userland applications from the inline splraise function.

branches: 1.10.6;
mark prototypes for static inline functions as possibly unused
(with __attribute__ ((unused))), to avoid generating warnings when
compiling without optimization but with the default warning flags.

two more slight bogons

actually, declare _splraise() as an inline function, because:
(1) it was using 'max', and some functions use a variable
of that name (*sigh*), and
(2) that makes it easier to be a bit trickier, and only call
swpipl if changing the IPL.

parens around macro arg (this is an old one)

make sure that splnet(), splbio(), splimp(), spltty(), splclock(),
splstatclock(), and splhigh() all _raise_ the IPL. (splhigh() is _not_
the highest possible IPL; mcheck is...)

clean up NetBSD RCS ID strings

branches: 1.4.2;
kill siroff() and resturcture do_sir() to be cleaner and more correct.

implement a (hack-ish) set of routines to do common chained-interrupt
handler management. It's nasty, but three slightly different copies of
the code is worse.

various cleanup, move setsoft* and spl* into intr.h.

the Alpha implementation of <machine/intr.h>

Fix cycle counter-based time keeping on Alpha in MP environments by using
a simpler calibration algorithm for the CC timecounter. Proposed in 2018
by Naruaki Etomi:

https://mail-index.netbsd.org/tech-kern/2018/01/14/msg022940.html

This patch is largely based on the proposed change, but avoids changing
any other timecounter logic, and re-factors things a bit to keep them
as MI as possible.

Implement cpu_intr_redistribute() for Tusnami/Titan systems.

Changes to make interrupt {,dis}establish MP-safe on Alpha:
- Protect all of the system interrupt linkage with the cpu_lock mutex.
- Re-order some of the stores to the SCB vector table to make it safe
in the face of lockless interrupt dispatch.
- Add a framework for routing interrupts to specific CPUs. Interrupts
are still funneled only to the primary CPU, but that will change for
some systems soon. Ensure that interrupt handler lists are manipulated
only on the CPUs that handle that specific interrupt source. This required
a re-factor of the alpha_shared_intr_*() family of functions.
- Enable __HAVE_INTR_CONTROL, although interrupt redistribution is still
a no-op.
- Reduce code duplication in the Jenson direct-SCB interrupt handlers.

Use a wrapper to acquire the kernel lock for non-MPSAFE interrupts,
rather than doing it in alpha_shared_intr_establish() directly.

Changes to make MPSAFE interrupts work on Alpha:

- Remove the ipl argument to scb_set() and the associated array of
"mpsafe" booleans initialized based on the ipl. It was bogus
anyway; all IPL_{BIO,NET,TTY}, etc. values are aliases of IPL_VM,
and for all practical purposes, there is really only one device
interrrupt level on Alpha anyway. Intead, we now treat all dispatches
from the SCB vector table as MP-safe, and it is now the handler for
that vector who is responsible for acquiring the KERNEL_LOCK if needed.

- Update the direct interrupt vector handlers in jensenio and TURBOchannel
to acquire the KERNEL_LOCK.

- Introduce a new ALPHA_INTR_MPSAFE flag, and add a flags argument to
alpha_shared_intr_establish(). When it is set, indicate that the
handler is MP-safe. Update alpha_shared_intr_dispatch() to pay
attention and acquire the KERNEL_LOCK (or not) as indicated.

- Re-factor all of the PCI interrupt handling, providing "generic PCI"
"PCI interrupts through ISA IRQs" implementations to significantly
reduce code duplication. Supplement the PCI chipset tag with more
info to facilitate this, and make the PCI interrupt-related routines
take a pci_chipset_tag_t argument rather than a void * argument.

- Because PCI interrupts on KN8AE are dispatched directly from the
SCB, provide a wrapper for non-MPSAFE interrupt handlers that
acquires the KERNEL_LOCK.

- Change the pci_intr_handle_t type to be a struct rather than an
integer type in order to catch any direct use of it as a value.
Add a set of functions to interact with pci_intr_handle_t, including
setting interrupt flags.

- Implement pci_intr_setattr() so that the PCI_INTR_MPSAFE attribute
can be set on a pci_intr_handle_t.

- While I'm here, make all of the MI PCI back-end operations call
through real functions rather than hopping directly through function
pointers in the chipset tag.

This change looks a lot bigger than it really is because of the re-factor
in the plethora of model-specific PCI interrupt back-ends. The KN8AE,
KN300, and T2/T3/T4 (Sable) are largely un-changed.

Move softintr bits into <machine/intr.h> and define ALPHA_ALL_SOFTINTS
for locore.s

Reduce the __HAVE_FAST_SOFTINTS #ifdef perimeter.

Implement fast soft interrupts for Alpha. It's not yet enabled, because
there is a bug lurking that causes problems when user space starts up,
so we'll stick with the slow path for now.

Track the SSIR per-cpu, rather than globally.

- Document all of the various interrupt levels in the Processor Stataus
register, and provide symbolic names for them as well.
- Use ALPHA_PSL_IPL_* values directly for IPL_*.

- Centralize per-CPU pmap initialization into a new pmap_init_cpu()
function. Call in from pmap_bootstrap() for the boot CPU, and
from cpu_hatch() for secondaary CPUs.
- Eliminiate the dedicated I-stream memory barrier IPI; handle it all from
the TLB shootdown IPI. Const poison, and add some additional memory
barriers and a TBIA to the PAUSE IPI.
- Completly rewrite TLB management in the alpha pmap module, borrowing
somoe ideas from the x86 pmap and adapting them to the alpha environment.
See the comments for theory of operation. Add a bunch of stats that
can be reported (disabled by default).
- Add some additional symbol decorations to improve cache behavior on
MP systems. Ensure coherency unit alignment for several structures
in the pmap module. Use hashed locks for pmap structures.
- Start out all new processes on the kernel page tables until their
first trip though pmap_activate() to avoid the potential of polluting
the current ASN in TLB with cross-process mappings.

fix types.

branches: 1.71.4; 1.71.8;
Implement MI IPI interface with cross-call support.

branches: 1.70.6; 1.70.20;
Do a minor cleanup of alpha (this will make applying pullups post branching
easier).
u_int{8,16,32,64}_t -> uint{*}_t
Change all old-style definitions to C89 prototypes.
Whitespace cleanup.
Constification in db_disasm.c

branches: 1.69.2; 1.69.6;
Switch alpha to use PCU to manage the FPU.
Tested by mhitch and review by rmind.

branches: 1.68.6;
Implement high priority (XC_HIGHPRI) xcall(9) mechanism - a facility
to execute functions from software interrupt context, at SOFTINT_CLOCK.
Functions must be lightweight. Will be used for passive serialization.

OK ad@.

branches: 1.67.2; 1.67.4;
Garbage-collect pmap_do_reactivate() and the associated IPI -- nothing has
used them for a long time.

Remove clause 3 and 4 from TNF licenses

branches: 1.65.2;
This file needs <machine/cpu.h> included, for the ALPHA_PSL_IPL_*
constants it uses.

branches: 1.64.2;
Finish moving alpha over to the MI atomic ops.

branches: 1.63.2; 1.63.6;
More header file cleanup.

branches: 1.62.6;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

branches: 1.61.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.60.8; 1.60.10;
Fix alpha build after idlelwp merge. I don't know why machine/cpu.h was
added here, but it does not seem to be needed now, and was resulting in a
circular dependency when sys/sched.h was changed in the yamt-idlelpw branch.

branches: 1.59.6; 1.59.8; 1.59.12; 1.59.14;
Remove spllowersoftclock() and CLKF_BASEPRI(), and always dispatch callouts
via a soft interrupt. In the near future, softclock will be run from process
context.

Merge newlock2 to head.

Define ipl_cookie_t._psl as uint8_t so that it can be packed into a
word with other seldomly written fields.

merge yamt-splraiseipl branch.

- finish implementing splraiseipl (and makeiplcookie).
http://mail-index.NetBSD.org/tech-kern/2006/07/01/0000.html
- complete workqueue(9) and fix its ipl problem, which is reported
to cause audio skipping.
- fix netbt (at least compilation problems) for some ports.
- fix PR/33218.

branches: 1.55.14; 1.55.16;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

branches: 1.54.2; 1.54.4; 1.54.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

- use sys/spl.h.
- add some IPL_ definitions.

pull splraiseipl() from newlock branch.

branches: 1.50.2; 1.50.4;
- Add a alpha_shared_intr_reset_strays() function that resets the stray
interrupt counter for a given shared interrupt descriptor.
- When an interrupt is successfully handled, reset the strays counter,
thus preventing a "slow leak" from eventually shutting off the interrupt
vector. Idea taken from pci_kn300.c (which was changed to use the new
alpha_shared_intr_reset_strays() function).

branches: 1.49.2; 1.49.10; 1.49.22; 1.49.28; 1.49.30; 1.49.36;
Rework the interrupt code, shaving some cycles off in the process.
Rather than an "iointr" routine that decomposes a vector into an
IRQ, we maintain a vector table directly, hooking up each "iointr"
routine at the correct vector. This also allows us to hook device
interrupts up to specific vectors (c.f. Jensen).

We can shave even more cycles off, here, and I will, but it requires
some changes to the alpha_shared_intr stuff.

- Tweak the pmap locking protocol slightly -- require that a pmap must
be locked before it can be marked as `active' on a processor.
- Require that pmaps other than the kernel pmap be locked when they
are passed to pmap_tlb_shootdown(). This, combined with the locking
protocol tweak, allow us to get a consistent view of `activeness' of
a pmap, which means we can optmize away a lot of TLB shootdown traffic
for user pmaps.
- Borrow an idea from the i386mp branch; use the normal SHOOTDOWN IPI
to deal with hitting the entire TLB, and garbage-collect the TBIA
and TBIAP IPIs.

branches: 1.47.2;
Add a microtime() implementation that interpolates between ticks
using the cycle counter. MP-safeness is achieved by giving each
CPU its own PCC frequency variables, and kicking the non-primary
processors via an IPI once per second.

Based on the sample code from David Mills' "A Kernel Model for
Precision Timekeeping".

Add splipi() to block interprocessor interrupts (which come in at IPL 5).

pmap_asn_alloc(): In a multiprocessor configuration, it's possible
to arrive here referencing the kernel_lev1map without having the
RESERVED ASN -- another CPU may have caused pmap_lev1map_destroy()
to be called, and that routine only invalidates the ASN for the
CPU that called it. So, in the MULTIPROCESSOR case, simply assign
the RESERVED ASN if we reference the kernel_lev1map rather than
asserting that we already have the RESERVED ASN. Thanks to Bill
Sommerfeld for helping me track down the problem.

Also add a new IPI that causes a CPU to re-activate its address
space if the pmap it's using changes level 1 maps (this probably
won't happen very often, but it's correct to have it).

This makes Alpha MP kernels boot multiuser. In fact, this commit
is being made from my dual-CPU AlphaServer 1200 running an MP kernel.

In splx(), don't call spl0() unless the ssir != 0.

Clean up soft interrupt related stuff a bit.

Change the softintr implementation to be a bit more cache friendly
(though, sigh, slightly more expensive at softintr_schedule() time).

Remove the use of splimp() from the NetBSD kernel. splnet()
and only splnet() is allowed for the protection of data structures
used by network devices.

branches: 1.40.2;
Make softclock a generic soft interrupt of the API is available,
adding the requisite void * argument to softclock().

Rename __GENERIC_SOFT_INTERRUPTS to __HAVE_GENERIC_SOFT_INTERRUPTS,
and place the definition in <machine/types.h>. This can now be used
as a flag to indicate whether or not <machine/intr.h> can be included
to get the generic soft interrupt API.

Make sure everybody has an splvm() and equate it with splimp() (splimp()
is the historical name for this interrupt level, and the historical name
is going to go away in the near future).

Several changes, which get us generally further along with
multiprocessor support:
- Implement MP-safe halt.
- Make the FPU saving code more like Bill's on the i386 MP branch.
XXX This code will no doubt be revisited again.
- Pass the cpu_info and trapframe to IPI handlers, saving some work
in the handlers themselves, and also making it possible for the
"pause" handler to reference register state for DDB.
- Add "machine cpu" to DDB, making it possible to reference other
CPUs registers (and thus get e.g. a traceback) from whichever
CPU is actually running the debugger.
- Garbage-collect "machine halt" and "machine reboot" DDB commands.
They don't have a prayer of working properly in multiprocessor
kernels, and didn't really work all that well in uniprocessor kernels.

Move IPI processing into a separate function.

Count individual interprocessor interrupts -- it's good to know where
they all come from.

Add spllock(). See spl(9) for details.

Add experimental code for pausing other CPUs upon a CPU's
entry into the debugger. While I'm here, add splsched()
as per spl(9).

Implement MP-safe lazy FP context switching, modeled on the
way Bill Sommerfeld implemented it for x86 (and bug fixes
fed back to Bill :-)

Add alpha_multicast_ipi().

Whitespace police.

make spl0() and spllowersoftclock() return void. Also, move spl0()
prototype from param.h to intr.h. (there were some big XXXs in param.h
that said to do that, and intr.h is included by param.h, so...)

Switch to the new `evcnt' mechanism for counting interrupts. Maintain
a per-CPU interrupt counter for clock, device, and interprocessor
interrupts.

Un-__P'ify kernel prototypes.

- Clean up clock interrupt code a bit, and provide a CPU_IS_PRIMARY()
macro in the MULTIPROCESSOR case (hardclock() wants it).
- Implement __GENERIC_SOFT_INTERRUPTS, and redefine the legacy
software interrupts in terms of it. Garbage-collect setsoftserial().

branches: 1.25.2;
Rename the atomic operations to have generic machine-independent
names, and define __HAVE_ATOMIC_OPERATIONS to indicate their
existence.

Point back to the alpha_shared_intr in the intrhand structure. This
allows platform-specific code to access the `intr_private' data via
the intrhand structure.

Move atomic operations into <machine/atomic.h>, and make them in-line
assembly, rather than function calls.

...except alpha_atomic_testset_l(), which will go away completely once
I commit the new <machine/lock.h>.

- Fix a botch in the IPI bitmasks (they were right-shifted by 1), and
add an IPI which causes the target CPU to perform AST processing when
it returns to userspace.
- Add a way to get/set a private pointer in the shared interrupt header.

branches: 1.21.2; 1.21.8;
Use atomic operations to manipulate the SSIR, and fix a problem introduced
with the spllowersoftclock() changes where more interrupts than necessary
were blocked while software interrupts were being processed.

Change the semantics of splsoftclock() to be like other spl*() functions,
that is priority is rasied. Add a new spllowersoftclock() to provide the
atomic drop-to-softclock semantics that the old splsoftclock() provided,
and update calls accordingly.

This fixes a problem with using the "rnd" pseudo-device from within
interrupt context to extract random data (e.g. from within the softnet
interrupt) where doing so would incorrectly unblock interrupts (causing
all sorts of lossage).

XXX 4 platforms do not have priority-raising capability: newsmips, sparc,
XXX sparc64, and VAX. This platforms still have this bug until their
XXX spl*() functions are fixed.

Restructure the IPI code a little, allowing multiple IPIs to be sent at
once. Add a way to broadcast an IPI to all processors (except the sender,
obviously). Add an IPI for TLB shootdown.

Add basic interprocessor interrupt sending and receiving code. Current
IPI functions: HALT, IMB, TBIA, TBIAP.

XXX HALT is not yet implemented, it's just a stub.

Minor style tweaks.

Add softserial to the alpha port. This significantly improved PPP
throughput on com ports.

Implement alpha_shared_intr_disestablish(). Simply removes the handler
fromthe list, allowing the caller to manipulate the sharing type,
if appropriate.

Switching dev/ic/lpt.c to use spllpt() instead of spltty(). It doesn't use
tty structures, and on some machines (namely the DraCo internal lpt, and some
multi-i/o boards for Amigas and DraCos), tying spltty to the pretty high printer
interupt level would hurt serial performance.

On all affected ports but Amiga, spllpt() has been defined in machine/intr.h
to be spltty(), thus preserving old behaviour. Portmasters are encouraged to
change is, if they feel something else is better (e.g., one of its own were
possible).

On second thought, call that like the rest of the shared intr functions.

Define a macro to test if a shared interrupt should be disabled after
a stray has occurred.

Protect userland applications from the inline splraise function.

branches: 1.10.6;
mark prototypes for static inline functions as possibly unused
(with __attribute__ ((unused))), to avoid generating warnings when
compiling without optimization but with the default warning flags.

two more slight bogons

actually, declare _splraise() as an inline function, because:
(1) it was using 'max', and some functions use a variable
of that name (*sigh*), and
(2) that makes it easier to be a bit trickier, and only call
swpipl if changing the IPL.

parens around macro arg (this is an old one)

make sure that splnet(), splbio(), splimp(), spltty(), splclock(),
splstatclock(), and splhigh() all _raise_ the IPL. (splhigh() is _not_
the highest possible IPL; mcheck is...)

clean up NetBSD RCS ID strings

branches: 1.4.2;
kill siroff() and resturcture do_sir() to be cleaner and more correct.

implement a (hack-ish) set of routines to do common chained-interrupt
handler management. It's nasty, but three slightly different copies of
the code is worse.

various cleanup, move setsoft* and spl* into intr.h.

the Alpha implementation of <machine/intr.h>

Implement cpu_intr_redistribute() for Tusnami/Titan systems.

Changes to make interrupt {,dis}establish MP-safe on Alpha:
- Protect all of the system interrupt linkage with the cpu_lock mutex.
- Re-order some of the stores to the SCB vector table to make it safe
in the face of lockless interrupt dispatch.
- Add a framework for routing interrupts to specific CPUs. Interrupts
are still funneled only to the primary CPU, but that will change for
some systems soon. Ensure that interrupt handler lists are manipulated
only on the CPUs that handle that specific interrupt source. This required
a re-factor of the alpha_shared_intr_*() family of functions.
- Enable __HAVE_INTR_CONTROL, although interrupt redistribution is still
a no-op.
- Reduce code duplication in the Jenson direct-SCB interrupt handlers.

Use a wrapper to acquire the kernel lock for non-MPSAFE interrupts,
rather than doing it in alpha_shared_intr_establish() directly.

Changes to make MPSAFE interrupts work on Alpha:

- Remove the ipl argument to scb_set() and the associated array of
"mpsafe" booleans initialized based on the ipl. It was bogus
anyway; all IPL_{BIO,NET,TTY}, etc. values are aliases of IPL_VM,
and for all practical purposes, there is really only one device
interrrupt level on Alpha anyway. Intead, we now treat all dispatches
from the SCB vector table as MP-safe, and it is now the handler for
that vector who is responsible for acquiring the KERNEL_LOCK if needed.

- Update the direct interrupt vector handlers in jensenio and TURBOchannel
to acquire the KERNEL_LOCK.

- Introduce a new ALPHA_INTR_MPSAFE flag, and add a flags argument to
alpha_shared_intr_establish(). When it is set, indicate that the
handler is MP-safe. Update alpha_shared_intr_dispatch() to pay
attention and acquire the KERNEL_LOCK (or not) as indicated.

- Re-factor all of the PCI interrupt handling, providing "generic PCI"
"PCI interrupts through ISA IRQs" implementations to significantly
reduce code duplication. Supplement the PCI chipset tag with more
info to facilitate this, and make the PCI interrupt-related routines
take a pci_chipset_tag_t argument rather than a void * argument.

- Because PCI interrupts on KN8AE are dispatched directly from the
SCB, provide a wrapper for non-MPSAFE interrupt handlers that
acquires the KERNEL_LOCK.

- Change the pci_intr_handle_t type to be a struct rather than an
integer type in order to catch any direct use of it as a value.
Add a set of functions to interact with pci_intr_handle_t, including
setting interrupt flags.

- Implement pci_intr_setattr() so that the PCI_INTR_MPSAFE attribute
can be set on a pci_intr_handle_t.

- While I'm here, make all of the MI PCI back-end operations call
through real functions rather than hopping directly through function
pointers in the chipset tag.

This change looks a lot bigger than it really is because of the re-factor
in the plethora of model-specific PCI interrupt back-ends. The KN8AE,
KN300, and T2/T3/T4 (Sable) are largely un-changed.

Move softintr bits into <machine/intr.h> and define ALPHA_ALL_SOFTINTS
for locore.s

Reduce the __HAVE_FAST_SOFTINTS #ifdef perimeter.

Implement fast soft interrupts for Alpha. It's not yet enabled, because
there is a bug lurking that causes problems when user space starts up,
so we'll stick with the slow path for now.

Track the SSIR per-cpu, rather than globally.

- Document all of the various interrupt levels in the Processor Stataus
register, and provide symbolic names for them as well.
- Use ALPHA_PSL_IPL_* values directly for IPL_*.

- Centralize per-CPU pmap initialization into a new pmap_init_cpu()
function. Call in from pmap_bootstrap() for the boot CPU, and
from cpu_hatch() for secondaary CPUs.
- Eliminiate the dedicated I-stream memory barrier IPI; handle it all from
the TLB shootdown IPI. Const poison, and add some additional memory
barriers and a TBIA to the PAUSE IPI.
- Completly rewrite TLB management in the alpha pmap module, borrowing
somoe ideas from the x86 pmap and adapting them to the alpha environment.
See the comments for theory of operation. Add a bunch of stats that
can be reported (disabled by default).
- Add some additional symbol decorations to improve cache behavior on
MP systems. Ensure coherency unit alignment for several structures
in the pmap module. Use hashed locks for pmap structures.
- Start out all new processes on the kernel page tables until their
first trip though pmap_activate() to avoid the potential of polluting
the current ASN in TLB with cross-process mappings.

fix types.

branches: 1.71.4; 1.71.8;
Implement MI IPI interface with cross-call support.

branches: 1.70.6; 1.70.20;
Do a minor cleanup of alpha (this will make applying pullups post branching
easier).
u_int{8,16,32,64}_t -> uint{*}_t
Change all old-style definitions to C89 prototypes.
Whitespace cleanup.
Constification in db_disasm.c

branches: 1.69.2; 1.69.6;
Switch alpha to use PCU to manage the FPU.
Tested by mhitch and review by rmind.

branches: 1.68.6;
Implement high priority (XC_HIGHPRI) xcall(9) mechanism - a facility
to execute functions from software interrupt context, at SOFTINT_CLOCK.
Functions must be lightweight. Will be used for passive serialization.

OK ad@.

branches: 1.67.2; 1.67.4;
Garbage-collect pmap_do_reactivate() and the associated IPI -- nothing has
used them for a long time.

Remove clause 3 and 4 from TNF licenses

branches: 1.65.2;
This file needs <machine/cpu.h> included, for the ALPHA_PSL_IPL_*
constants it uses.

branches: 1.64.2;
Finish moving alpha over to the MI atomic ops.

branches: 1.63.2; 1.63.6;
More header file cleanup.

branches: 1.62.6;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

branches: 1.61.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.60.8; 1.60.10;
Fix alpha build after idlelwp merge. I don't know why machine/cpu.h was
added here, but it does not seem to be needed now, and was resulting in a
circular dependency when sys/sched.h was changed in the yamt-idlelpw branch.

branches: 1.59.6; 1.59.8; 1.59.12; 1.59.14;
Remove spllowersoftclock() and CLKF_BASEPRI(), and always dispatch callouts
via a soft interrupt. In the near future, softclock will be run from process
context.

Merge newlock2 to head.

Define ipl_cookie_t._psl as uint8_t so that it can be packed into a
word with other seldomly written fields.

merge yamt-splraiseipl branch.

- finish implementing splraiseipl (and makeiplcookie).
http://mail-index.NetBSD.org/tech-kern/2006/07/01/0000.html
- complete workqueue(9) and fix its ipl problem, which is reported
to cause audio skipping.
- fix netbt (at least compilation problems) for some ports.
- fix PR/33218.

branches: 1.55.14; 1.55.16;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

branches: 1.54.2; 1.54.4; 1.54.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

- use sys/spl.h.
- add some IPL_ definitions.

pull splraiseipl() from newlock branch.

branches: 1.50.2; 1.50.4;
- Add a alpha_shared_intr_reset_strays() function that resets the stray
interrupt counter for a given shared interrupt descriptor.
- When an interrupt is successfully handled, reset the strays counter,
thus preventing a "slow leak" from eventually shutting off the interrupt
vector. Idea taken from pci_kn300.c (which was changed to use the new
alpha_shared_intr_reset_strays() function).

branches: 1.49.2; 1.49.10; 1.49.22; 1.49.28; 1.49.30; 1.49.36;
Rework the interrupt code, shaving some cycles off in the process.
Rather than an "iointr" routine that decomposes a vector into an
IRQ, we maintain a vector table directly, hooking up each "iointr"
routine at the correct vector. This also allows us to hook device
interrupts up to specific vectors (c.f. Jensen).

We can shave even more cycles off, here, and I will, but it requires
some changes to the alpha_shared_intr stuff.

- Tweak the pmap locking protocol slightly -- require that a pmap must
be locked before it can be marked as `active' on a processor.
- Require that pmaps other than the kernel pmap be locked when they
are passed to pmap_tlb_shootdown(). This, combined with the locking
protocol tweak, allow us to get a consistent view of `activeness' of
a pmap, which means we can optmize away a lot of TLB shootdown traffic
for user pmaps.
- Borrow an idea from the i386mp branch; use the normal SHOOTDOWN IPI
to deal with hitting the entire TLB, and garbage-collect the TBIA
and TBIAP IPIs.

branches: 1.47.2;
Add a microtime() implementation that interpolates between ticks
using the cycle counter. MP-safeness is achieved by giving each
CPU its own PCC frequency variables, and kicking the non-primary
processors via an IPI once per second.

Based on the sample code from David Mills' "A Kernel Model for
Precision Timekeeping".

Add splipi() to block interprocessor interrupts (which come in at IPL 5).

pmap_asn_alloc(): In a multiprocessor configuration, it's possible
to arrive here referencing the kernel_lev1map without having the
RESERVED ASN -- another CPU may have caused pmap_lev1map_destroy()
to be called, and that routine only invalidates the ASN for the
CPU that called it. So, in the MULTIPROCESSOR case, simply assign
the RESERVED ASN if we reference the kernel_lev1map rather than
asserting that we already have the RESERVED ASN. Thanks to Bill
Sommerfeld for helping me track down the problem.

Also add a new IPI that causes a CPU to re-activate its address
space if the pmap it's using changes level 1 maps (this probably
won't happen very often, but it's correct to have it).

This makes Alpha MP kernels boot multiuser. In fact, this commit
is being made from my dual-CPU AlphaServer 1200 running an MP kernel.

In splx(), don't call spl0() unless the ssir != 0.

Clean up soft interrupt related stuff a bit.

Change the softintr implementation to be a bit more cache friendly
(though, sigh, slightly more expensive at softintr_schedule() time).

Remove the use of splimp() from the NetBSD kernel. splnet()
and only splnet() is allowed for the protection of data structures
used by network devices.

branches: 1.40.2;
Make softclock a generic soft interrupt of the API is available,
adding the requisite void * argument to softclock().

Rename __GENERIC_SOFT_INTERRUPTS to __HAVE_GENERIC_SOFT_INTERRUPTS,
and place the definition in <machine/types.h>. This can now be used
as a flag to indicate whether or not <machine/intr.h> can be included
to get the generic soft interrupt API.

Make sure everybody has an splvm() and equate it with splimp() (splimp()
is the historical name for this interrupt level, and the historical name
is going to go away in the near future).

Several changes, which get us generally further along with
multiprocessor support:
- Implement MP-safe halt.
- Make the FPU saving code more like Bill's on the i386 MP branch.
XXX This code will no doubt be revisited again.
- Pass the cpu_info and trapframe to IPI handlers, saving some work
in the handlers themselves, and also making it possible for the
"pause" handler to reference register state for DDB.
- Add "machine cpu" to DDB, making it possible to reference other
CPUs registers (and thus get e.g. a traceback) from whichever
CPU is actually running the debugger.
- Garbage-collect "machine halt" and "machine reboot" DDB commands.
They don't have a prayer of working properly in multiprocessor
kernels, and didn't really work all that well in uniprocessor kernels.

Move IPI processing into a separate function.

Count individual interprocessor interrupts -- it's good to know where
they all come from.

Add spllock(). See spl(9) for details.

Add experimental code for pausing other CPUs upon a CPU's
entry into the debugger. While I'm here, add splsched()
as per spl(9).

Implement MP-safe lazy FP context switching, modeled on the
way Bill Sommerfeld implemented it for x86 (and bug fixes
fed back to Bill :-)

Add alpha_multicast_ipi().

Whitespace police.

make spl0() and spllowersoftclock() return void. Also, move spl0()
prototype from param.h to intr.h. (there were some big XXXs in param.h
that said to do that, and intr.h is included by param.h, so...)

Switch to the new `evcnt' mechanism for counting interrupts. Maintain
a per-CPU interrupt counter for clock, device, and interprocessor
interrupts.

Un-__P'ify kernel prototypes.

- Clean up clock interrupt code a bit, and provide a CPU_IS_PRIMARY()
macro in the MULTIPROCESSOR case (hardclock() wants it).
- Implement __GENERIC_SOFT_INTERRUPTS, and redefine the legacy
software interrupts in terms of it. Garbage-collect setsoftserial().

branches: 1.25.2;
Rename the atomic operations to have generic machine-independent
names, and define __HAVE_ATOMIC_OPERATIONS to indicate their
existence.

Point back to the alpha_shared_intr in the intrhand structure. This
allows platform-specific code to access the `intr_private' data via
the intrhand structure.

Move atomic operations into <machine/atomic.h>, and make them in-line
assembly, rather than function calls.

...except alpha_atomic_testset_l(), which will go away completely once
I commit the new <machine/lock.h>.

- Fix a botch in the IPI bitmasks (they were right-shifted by 1), and
add an IPI which causes the target CPU to perform AST processing when
it returns to userspace.
- Add a way to get/set a private pointer in the shared interrupt header.

branches: 1.21.2; 1.21.8;
Use atomic operations to manipulate the SSIR, and fix a problem introduced
with the spllowersoftclock() changes where more interrupts than necessary
were blocked while software interrupts were being processed.

Change the semantics of splsoftclock() to be like other spl*() functions,
that is priority is rasied. Add a new spllowersoftclock() to provide the
atomic drop-to-softclock semantics that the old splsoftclock() provided,
and update calls accordingly.

This fixes a problem with using the "rnd" pseudo-device from within
interrupt context to extract random data (e.g. from within the softnet
interrupt) where doing so would incorrectly unblock interrupts (causing
all sorts of lossage).

XXX 4 platforms do not have priority-raising capability: newsmips, sparc,
XXX sparc64, and VAX. This platforms still have this bug until their
XXX spl*() functions are fixed.

Restructure the IPI code a little, allowing multiple IPIs to be sent at
once. Add a way to broadcast an IPI to all processors (except the sender,
obviously). Add an IPI for TLB shootdown.

Add basic interprocessor interrupt sending and receiving code. Current
IPI functions: HALT, IMB, TBIA, TBIAP.

XXX HALT is not yet implemented, it's just a stub.

Minor style tweaks.

Add softserial to the alpha port. This significantly improved PPP
throughput on com ports.

Implement alpha_shared_intr_disestablish(). Simply removes the handler
fromthe list, allowing the caller to manipulate the sharing type,
if appropriate.

Switching dev/ic/lpt.c to use spllpt() instead of spltty(). It doesn't use
tty structures, and on some machines (namely the DraCo internal lpt, and some
multi-i/o boards for Amigas and DraCos), tying spltty to the pretty high printer
interupt level would hurt serial performance.

On all affected ports but Amiga, spllpt() has been defined in machine/intr.h
to be spltty(), thus preserving old behaviour. Portmasters are encouraged to
change is, if they feel something else is better (e.g., one of its own were
possible).

On second thought, call that like the rest of the shared intr functions.

Define a macro to test if a shared interrupt should be disabled after
a stray has occurred.

Protect userland applications from the inline splraise function.

branches: 1.10.6;
mark prototypes for static inline functions as possibly unused
(with __attribute__ ((unused))), to avoid generating warnings when
compiling without optimization but with the default warning flags.

two more slight bogons

actually, declare _splraise() as an inline function, because:
(1) it was using 'max', and some functions use a variable
of that name (*sigh*), and
(2) that makes it easier to be a bit trickier, and only call
swpipl if changing the IPL.

parens around macro arg (this is an old one)

make sure that splnet(), splbio(), splimp(), spltty(), splclock(),
splstatclock(), and splhigh() all _raise_ the IPL. (splhigh() is _not_
the highest possible IPL; mcheck is...)

clean up NetBSD RCS ID strings

branches: 1.4.2;
kill siroff() and resturcture do_sir() to be cleaner and more correct.

implement a (hack-ish) set of routines to do common chained-interrupt
handler management. It's nasty, but three slightly different copies of
the code is worse.

various cleanup, move setsoft* and spl* into intr.h.

the Alpha implementation of <machine/intr.h>

Track the SSIR per-cpu, rather than globally.

- Document all of the various interrupt levels in the Processor Stataus
register, and provide symbolic names for them as well.
- Use ALPHA_PSL_IPL_* values directly for IPL_*.

- Centralize per-CPU pmap initialization into a new pmap_init_cpu()
function. Call in from pmap_bootstrap() for the boot CPU, and
from cpu_hatch() for secondaary CPUs.
- Eliminiate the dedicated I-stream memory barrier IPI; handle it all from
the TLB shootdown IPI. Const poison, and add some additional memory
barriers and a TBIA to the PAUSE IPI.
- Completly rewrite TLB management in the alpha pmap module, borrowing
somoe ideas from the x86 pmap and adapting them to the alpha environment.
See the comments for theory of operation. Add a bunch of stats that
can be reported (disabled by default).
- Add some additional symbol decorations to improve cache behavior on
MP systems. Ensure coherency unit alignment for several structures
in the pmap module. Use hashed locks for pmap structures.
- Start out all new processes on the kernel page tables until their
first trip though pmap_activate() to avoid the potential of polluting
the current ASN in TLB with cross-process mappings.

fix types.

branches: 1.71.4; 1.71.8;
Implement MI IPI interface with cross-call support.

branches: 1.70.6; 1.70.20;
Do a minor cleanup of alpha (this will make applying pullups post branching
easier).
u_int{8,16,32,64}_t -> uint{*}_t
Change all old-style definitions to C89 prototypes.
Whitespace cleanup.
Constification in db_disasm.c

branches: 1.69.2; 1.69.6;
Switch alpha to use PCU to manage the FPU.
Tested by mhitch and review by rmind.

branches: 1.68.6;
Implement high priority (XC_HIGHPRI) xcall(9) mechanism - a facility
to execute functions from software interrupt context, at SOFTINT_CLOCK.
Functions must be lightweight. Will be used for passive serialization.

OK ad@.

branches: 1.67.2; 1.67.4;
Garbage-collect pmap_do_reactivate() and the associated IPI -- nothing has
used them for a long time.

Remove clause 3 and 4 from TNF licenses

branches: 1.65.2;
This file needs <machine/cpu.h> included, for the ALPHA_PSL_IPL_*
constants it uses.

branches: 1.64.2;
Finish moving alpha over to the MI atomic ops.

branches: 1.63.2; 1.63.6;
More header file cleanup.

branches: 1.62.6;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

branches: 1.61.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.60.8; 1.60.10;
Fix alpha build after idlelwp merge. I don't know why machine/cpu.h was
added here, but it does not seem to be needed now, and was resulting in a
circular dependency when sys/sched.h was changed in the yamt-idlelpw branch.

branches: 1.59.6; 1.59.8; 1.59.12; 1.59.14;
Remove spllowersoftclock() and CLKF_BASEPRI(), and always dispatch callouts
via a soft interrupt. In the near future, softclock will be run from process
context.

Merge newlock2 to head.

Define ipl_cookie_t._psl as uint8_t so that it can be packed into a
word with other seldomly written fields.

merge yamt-splraiseipl branch.

- finish implementing splraiseipl (and makeiplcookie).
http://mail-index.NetBSD.org/tech-kern/2006/07/01/0000.html
- complete workqueue(9) and fix its ipl problem, which is reported
to cause audio skipping.
- fix netbt (at least compilation problems) for some ports.
- fix PR/33218.

branches: 1.55.14; 1.55.16;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

branches: 1.54.2; 1.54.4; 1.54.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

- use sys/spl.h.
- add some IPL_ definitions.

pull splraiseipl() from newlock branch.

branches: 1.50.2; 1.50.4;
- Add a alpha_shared_intr_reset_strays() function that resets the stray
interrupt counter for a given shared interrupt descriptor.
- When an interrupt is successfully handled, reset the strays counter,
thus preventing a "slow leak" from eventually shutting off the interrupt
vector. Idea taken from pci_kn300.c (which was changed to use the new
alpha_shared_intr_reset_strays() function).

branches: 1.49.2; 1.49.10; 1.49.22; 1.49.28; 1.49.30; 1.49.36;
Rework the interrupt code, shaving some cycles off in the process.
Rather than an "iointr" routine that decomposes a vector into an
IRQ, we maintain a vector table directly, hooking up each "iointr"
routine at the correct vector. This also allows us to hook device
interrupts up to specific vectors (c.f. Jensen).

We can shave even more cycles off, here, and I will, but it requires
some changes to the alpha_shared_intr stuff.

- Tweak the pmap locking protocol slightly -- require that a pmap must
be locked before it can be marked as `active' on a processor.
- Require that pmaps other than the kernel pmap be locked when they
are passed to pmap_tlb_shootdown(). This, combined with the locking
protocol tweak, allow us to get a consistent view of `activeness' of
a pmap, which means we can optmize away a lot of TLB shootdown traffic
for user pmaps.
- Borrow an idea from the i386mp branch; use the normal SHOOTDOWN IPI
to deal with hitting the entire TLB, and garbage-collect the TBIA
and TBIAP IPIs.

branches: 1.47.2;
Add a microtime() implementation that interpolates between ticks
using the cycle counter. MP-safeness is achieved by giving each
CPU its own PCC frequency variables, and kicking the non-primary
processors via an IPI once per second.

Based on the sample code from David Mills' "A Kernel Model for
Precision Timekeeping".

Add splipi() to block interprocessor interrupts (which come in at IPL 5).

pmap_asn_alloc(): In a multiprocessor configuration, it's possible
to arrive here referencing the kernel_lev1map without having the
RESERVED ASN -- another CPU may have caused pmap_lev1map_destroy()
to be called, and that routine only invalidates the ASN for the
CPU that called it. So, in the MULTIPROCESSOR case, simply assign
the RESERVED ASN if we reference the kernel_lev1map rather than
asserting that we already have the RESERVED ASN. Thanks to Bill
Sommerfeld for helping me track down the problem.

Also add a new IPI that causes a CPU to re-activate its address
space if the pmap it's using changes level 1 maps (this probably
won't happen very often, but it's correct to have it).

This makes Alpha MP kernels boot multiuser. In fact, this commit
is being made from my dual-CPU AlphaServer 1200 running an MP kernel.

In splx(), don't call spl0() unless the ssir != 0.

Clean up soft interrupt related stuff a bit.

Change the softintr implementation to be a bit more cache friendly
(though, sigh, slightly more expensive at softintr_schedule() time).

Remove the use of splimp() from the NetBSD kernel. splnet()
and only splnet() is allowed for the protection of data structures
used by network devices.

branches: 1.40.2;
Make softclock a generic soft interrupt of the API is available,
adding the requisite void * argument to softclock().

Rename __GENERIC_SOFT_INTERRUPTS to __HAVE_GENERIC_SOFT_INTERRUPTS,
and place the definition in <machine/types.h>. This can now be used
as a flag to indicate whether or not <machine/intr.h> can be included
to get the generic soft interrupt API.

Make sure everybody has an splvm() and equate it with splimp() (splimp()
is the historical name for this interrupt level, and the historical name
is going to go away in the near future).

Several changes, which get us generally further along with
multiprocessor support:
- Implement MP-safe halt.
- Make the FPU saving code more like Bill's on the i386 MP branch.
XXX This code will no doubt be revisited again.
- Pass the cpu_info and trapframe to IPI handlers, saving some work
in the handlers themselves, and also making it possible for the
"pause" handler to reference register state for DDB.
- Add "machine cpu" to DDB, making it possible to reference other
CPUs registers (and thus get e.g. a traceback) from whichever
CPU is actually running the debugger.
- Garbage-collect "machine halt" and "machine reboot" DDB commands.
They don't have a prayer of working properly in multiprocessor
kernels, and didn't really work all that well in uniprocessor kernels.

Move IPI processing into a separate function.

Count individual interprocessor interrupts -- it's good to know where
they all come from.

Add spllock(). See spl(9) for details.

Add experimental code for pausing other CPUs upon a CPU's
entry into the debugger. While I'm here, add splsched()
as per spl(9).

Implement MP-safe lazy FP context switching, modeled on the
way Bill Sommerfeld implemented it for x86 (and bug fixes
fed back to Bill :-)

Add alpha_multicast_ipi().

Whitespace police.

make spl0() and spllowersoftclock() return void. Also, move spl0()
prototype from param.h to intr.h. (there were some big XXXs in param.h
that said to do that, and intr.h is included by param.h, so...)

Switch to the new `evcnt' mechanism for counting interrupts. Maintain
a per-CPU interrupt counter for clock, device, and interprocessor
interrupts.

Un-__P'ify kernel prototypes.

- Clean up clock interrupt code a bit, and provide a CPU_IS_PRIMARY()
macro in the MULTIPROCESSOR case (hardclock() wants it).
- Implement __GENERIC_SOFT_INTERRUPTS, and redefine the legacy
software interrupts in terms of it. Garbage-collect setsoftserial().

branches: 1.25.2;
Rename the atomic operations to have generic machine-independent
names, and define __HAVE_ATOMIC_OPERATIONS to indicate their
existence.

Point back to the alpha_shared_intr in the intrhand structure. This
allows platform-specific code to access the `intr_private' data via
the intrhand structure.

Move atomic operations into <machine/atomic.h>, and make them in-line
assembly, rather than function calls.

...except alpha_atomic_testset_l(), which will go away completely once
I commit the new <machine/lock.h>.

- Fix a botch in the IPI bitmasks (they were right-shifted by 1), and
add an IPI which causes the target CPU to perform AST processing when
it returns to userspace.
- Add a way to get/set a private pointer in the shared interrupt header.

branches: 1.21.2; 1.21.8;
Use atomic operations to manipulate the SSIR, and fix a problem introduced
with the spllowersoftclock() changes where more interrupts than necessary
were blocked while software interrupts were being processed.

Change the semantics of splsoftclock() to be like other spl*() functions,
that is priority is rasied. Add a new spllowersoftclock() to provide the
atomic drop-to-softclock semantics that the old splsoftclock() provided,
and update calls accordingly.

This fixes a problem with using the "rnd" pseudo-device from within
interrupt context to extract random data (e.g. from within the softnet
interrupt) where doing so would incorrectly unblock interrupts (causing
all sorts of lossage).

XXX 4 platforms do not have priority-raising capability: newsmips, sparc,
XXX sparc64, and VAX. This platforms still have this bug until their
XXX spl*() functions are fixed.

Restructure the IPI code a little, allowing multiple IPIs to be sent at
once. Add a way to broadcast an IPI to all processors (except the sender,
obviously). Add an IPI for TLB shootdown.

Add basic interprocessor interrupt sending and receiving code. Current
IPI functions: HALT, IMB, TBIA, TBIAP.

XXX HALT is not yet implemented, it's just a stub.

Minor style tweaks.

Add softserial to the alpha port. This significantly improved PPP
throughput on com ports.

Implement alpha_shared_intr_disestablish(). Simply removes the handler
fromthe list, allowing the caller to manipulate the sharing type,
if appropriate.

Switching dev/ic/lpt.c to use spllpt() instead of spltty(). It doesn't use
tty structures, and on some machines (namely the DraCo internal lpt, and some
multi-i/o boards for Amigas and DraCos), tying spltty to the pretty high printer
interupt level would hurt serial performance.

On all affected ports but Amiga, spllpt() has been defined in machine/intr.h
to be spltty(), thus preserving old behaviour. Portmasters are encouraged to
change is, if they feel something else is better (e.g., one of its own were
possible).

On second thought, call that like the rest of the shared intr functions.