intr.h revision 1.61
1/* $NetBSD: intr.h,v 1.61 2007/10/17 19:52:58 garbled Exp $ */ 2 3/*- 4 * Copyright (c) 2000, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39/* 40 * Copyright (c) 1997 Christopher G. Demetriou. All rights reserved. 41 * Copyright (c) 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67#ifndef _ALPHA_INTR_H_ 68#define _ALPHA_INTR_H_ 69 70#include <sys/device.h> 71#include <sys/lock.h> 72#include <sys/queue.h> 73 74#include <machine/atomic.h> 75 76/* 77 * The Alpha System Control Block. This is 8k long, and you get 78 * 16 bytes per vector (i.e. the vector numbers are spaced 16 79 * apart). 80 * 81 * This is sort of a "shadow" SCB -- rather than the CPU jumping 82 * to (SCBaddr + (16 * vector)), like it does on the VAX, we get 83 * a vector number in a1. We use the SCB to look up a routine/arg 84 * and jump to it. 85 * 86 * Since we use the SCB only for I/O interrupts, we make it shorter 87 * than normal, starting it at vector 0x800 (the start of the I/O 88 * interrupt vectors). 89 */ 90#define SCB_IOVECBASE 0x0800 91#define SCB_VECSIZE 0x0010 92#define SCB_SIZE 0x2000 93 94#define SCB_VECTOIDX(x) ((x) >> 4) 95#define SCB_IDXTOVEC(x) ((x) << 4) 96 97#define SCB_NIOVECS SCB_VECTOIDX(SCB_SIZE - SCB_IOVECBASE) 98 99struct scbvec { 100 void (*scb_func)(void *, u_long); 101 void *scb_arg; 102}; 103 104/* 105 * Alpha interrupts come in at one of 4 levels: 106 * 107 * software interrupt level 108 * i/o level 1 109 * i/o level 2 110 * clock level 111 * 112 * However, since we do not have any way to know which hardware 113 * level a particular i/o interrupt comes in on, we have to 114 * whittle it down to 3. 115 */ 116 117#define IPL_NONE 0 /* no interrupt level */ 118#define IPL_SOFT 1 /* generic software interrupts */ 119#define IPL_SOFTCLOCK 2 /* clock software interrupts */ 120#define IPL_SOFTNET 3 /* network software interrupts */ 121#define IPL_SOFTSERIAL 4 /* serial software interrupts */ 122#define IPL_BIO 5 /* block I/O interrupts */ 123#define IPL_NET 6 /* network interrupts */ 124#define IPL_TTY 7 /* terminal interrupts */ 125#define IPL_LPT IPL_TTY 126#define IPL_VM 8 /* interrupts that can alloc mem */ 127#define IPL_CLOCK 9 /* clock interrupts */ 128#define IPL_IPI IPL_CLOCK /* AARM, 5-2, II-B */ 129#define IPL_STATCLOCK IPL_CLOCK 130#define IPL_HIGH 10 /* all interrupts */ 131#define IPL_SCHED IPL_HIGH 132#define IPL_LOCK IPL_HIGH 133#define IPL_SERIAL 11 /* serial interrupts */ 134 135typedef int ipl_t; 136typedef struct { 137 uint8_t _psl; 138} ipl_cookie_t; 139 140ipl_cookie_t makeiplcookie(ipl_t); 141 142#define SI_SOFTSERIAL 0 143#define SI_SOFTNET 1 144#define SI_SOFTCLOCK 2 145#define SI_SOFT 3 146 147#define SI_NQUEUES 4 148 149#define SI_QUEUENAMES { \ 150 "serial", \ 151 "net", \ 152 "clock", \ 153 "misc", \ 154} 155 156#define IST_UNUSABLE -1 /* interrupt cannot be used */ 157#define IST_NONE 0 /* none (dummy) */ 158#define IST_PULSE 1 /* pulsed */ 159#define IST_EDGE 2 /* edge-triggered */ 160#define IST_LEVEL 3 /* level-triggered */ 161 162#ifdef _KERNEL 163 164/* Simulated software interrupt register. */ 165extern volatile unsigned long ssir; 166 167/* IPL-lowering/restoring macros */ 168void spl0(void); 169 170static __inline void 171splx(int s) 172{ 173 if (s == ALPHA_PSL_IPL_0 && ssir != 0) 174 spl0(); 175 else 176 alpha_pal_swpipl(s); 177} 178/* IPL-raising functions/macros */ 179static __inline int 180_splraise(int s) 181{ 182 int cur = alpha_pal_rdps() & ALPHA_PSL_IPL_MASK; 183 return (s > cur ? alpha_pal_swpipl(s) : cur); 184} 185 186#define splraiseipl(icookie) _splraise((icookie)._psl) 187 188#include <sys/spl.h> 189 190/* 191 * Interprocessor interrupts. In order how we want them processed. 192 */ 193#define ALPHA_IPI_HALT (1UL << 0) 194#define ALPHA_IPI_MICROSET (1UL << 1) 195#define ALPHA_IPI_SHOOTDOWN (1UL << 2) 196#define ALPHA_IPI_IMB (1UL << 3) 197#define ALPHA_IPI_AST (1UL << 4) 198#define ALPHA_IPI_SYNCH_FPU (1UL << 5) 199#define ALPHA_IPI_DISCARD_FPU (1UL << 6) 200#define ALPHA_IPI_PAUSE (1UL << 7) 201#define ALPHA_IPI_PMAP_REACTIVATE (1UL << 8) 202 203#define ALPHA_NIPIS 9 /* must not exceed 64 */ 204 205struct cpu_info; 206struct trapframe; 207 208void alpha_ipi_init(struct cpu_info *); 209void alpha_ipi_process(struct cpu_info *, struct trapframe *); 210void alpha_send_ipi(unsigned long, unsigned long); 211void alpha_broadcast_ipi(unsigned long); 212void alpha_multicast_ipi(unsigned long, unsigned long); 213 214/* 215 * Alpha shared-interrupt-line common code. 216 */ 217 218struct alpha_shared_intrhand { 219 TAILQ_ENTRY(alpha_shared_intrhand) 220 ih_q; 221 struct alpha_shared_intr *ih_intrhead; 222 int (*ih_fn)(void *); 223 void *ih_arg; 224 int ih_level; 225 unsigned int ih_num; 226}; 227 228struct alpha_shared_intr { 229 TAILQ_HEAD(,alpha_shared_intrhand) 230 intr_q; 231 struct evcnt intr_evcnt; 232 char *intr_string; 233 void *intr_private; 234 int intr_sharetype; 235 int intr_dfltsharetype; 236 int intr_nstrays; 237 int intr_maxstrays; 238}; 239 240#define ALPHA_SHARED_INTR_DISABLE(asi, num) \ 241 ((asi)[num].intr_maxstrays != 0 && \ 242 (asi)[num].intr_nstrays == (asi)[num].intr_maxstrays) 243 244#define setsoft(x) atomic_setbits_ulong(&ssir, 1 << (x)) 245 246struct alpha_soft_intrhand { 247 TAILQ_ENTRY(alpha_soft_intrhand) 248 sih_q; 249 struct alpha_soft_intr *sih_intrhead; 250 void (*sih_fn)(void *); 251 void *sih_arg; 252 int sih_pending; 253}; 254 255struct alpha_soft_intr { 256 TAILQ_HEAD(, alpha_soft_intrhand) 257 softintr_q; 258 struct evcnt softintr_evcnt; 259 struct simplelock softintr_slock; 260 unsigned long softintr_siq; 261}; 262 263void *softintr_establish(int, void (*)(void *), void *); 264void softintr_disestablish(void *); 265void softintr_init(void); 266void softintr_dispatch(void); 267 268#define softintr_schedule(arg) \ 269do { \ 270 struct alpha_soft_intrhand *__sih = (arg); \ 271 struct alpha_soft_intr *__si = __sih->sih_intrhead; \ 272 int __s; \ 273 \ 274 __s = splhigh(); \ 275 simple_lock(&__si->softintr_slock); \ 276 if (__sih->sih_pending == 0) { \ 277 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 278 __sih->sih_pending = 1; \ 279 setsoft(__si->softintr_siq); \ 280 } \ 281 simple_unlock(&__si->softintr_slock); \ 282 splx(__s); \ 283} while (0) 284 285/* XXX For legacy software interrupts. */ 286extern struct alpha_soft_intrhand *softnet_intrhand; 287 288#define setsoftnet() softintr_schedule(softnet_intrhand) 289 290struct alpha_shared_intr *alpha_shared_intr_alloc(unsigned int, unsigned int); 291int alpha_shared_intr_dispatch(struct alpha_shared_intr *, 292 unsigned int); 293void *alpha_shared_intr_establish(struct alpha_shared_intr *, 294 unsigned int, int, int, int (*)(void *), void *, const char *); 295void alpha_shared_intr_disestablish(struct alpha_shared_intr *, 296 void *, const char *); 297int alpha_shared_intr_get_sharetype(struct alpha_shared_intr *, 298 unsigned int); 299int alpha_shared_intr_isactive(struct alpha_shared_intr *, 300 unsigned int); 301int alpha_shared_intr_firstactive(struct alpha_shared_intr *, 302 unsigned int); 303void alpha_shared_intr_set_dfltsharetype(struct alpha_shared_intr *, 304 unsigned int, int); 305void alpha_shared_intr_set_maxstrays(struct alpha_shared_intr *, 306 unsigned int, int); 307void alpha_shared_intr_reset_strays(struct alpha_shared_intr *, 308 unsigned int); 309void alpha_shared_intr_stray(struct alpha_shared_intr *, unsigned int, 310 const char *); 311void alpha_shared_intr_set_private(struct alpha_shared_intr *, 312 unsigned int, void *); 313void *alpha_shared_intr_get_private(struct alpha_shared_intr *, 314 unsigned int); 315char *alpha_shared_intr_string(struct alpha_shared_intr *, 316 unsigned int); 317struct evcnt *alpha_shared_intr_evcnt(struct alpha_shared_intr *, 318 unsigned int); 319 320extern struct scbvec scb_iovectab[]; 321 322void scb_init(void); 323void scb_set(u_long, void (*)(void *, u_long), void *); 324u_long scb_alloc(void (*)(void *, u_long), void *); 325void scb_free(u_long); 326 327#define SCB_ALLOC_FAILED ((u_long) -1) 328 329#endif /* _KERNEL */ 330#endif /* ! _ALPHA_INTR_H_ */ 331