intr.h revision 1.45
1/* $NetBSD: intr.h,v 1.45 2001/04/20 16:22:34 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39/* 40 * Copyright (c) 1997 Christopher G. Demetriou. All rights reserved. 41 * Copyright (c) 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67#ifndef _ALPHA_INTR_H_ 68#define _ALPHA_INTR_H_ 69 70#include <sys/device.h> 71#include <sys/lock.h> 72#include <sys/queue.h> 73#include <machine/atomic.h> 74 75/* 76 * Alpha interrupts come in at one of 4 levels: 77 * 78 * software interrupt level 79 * i/o level 1 80 * i/o level 2 81 * clock level 82 * 83 * However, since we do not have any way to know which hardware 84 * level a particular i/o interrupt comes in on, we have to 85 * whittle it down to 3. 86 */ 87 88#define IPL_NONE 1 /* disable only this interrupt */ 89#define IPL_BIO 1 /* disable block I/O interrupts */ 90#define IPL_NET 1 /* disable network interrupts */ 91#define IPL_TTY 1 /* disable terminal interrupts */ 92#define IPL_CLOCK 2 /* disable clock interrupts */ 93#define IPL_HIGH 3 /* disable all interrupts */ 94#define IPL_SERIAL 1 /* disable serial interrupts */ 95 96#define IPL_SOFTSERIAL 0 /* serial software interrupts */ 97#define IPL_SOFTNET 1 /* network software interrupts */ 98#define IPL_SOFTCLOCK 2 /* clock software interrupts */ 99#define IPL_SOFT 3 /* other software interrupts */ 100#define IPL_NSOFT 4 101 102#define IPL_SOFTNAMES { \ 103 "serial", \ 104 "net", \ 105 "clock", \ 106 "misc", \ 107} 108 109#define IST_UNUSABLE -1 /* interrupt cannot be used */ 110#define IST_NONE 0 /* none (dummy) */ 111#define IST_PULSE 1 /* pulsed */ 112#define IST_EDGE 2 /* edge-triggered */ 113#define IST_LEVEL 3 /* level-triggered */ 114 115#ifdef _KERNEL 116 117/* Simulated software interrupt register. */ 118extern __volatile unsigned long ssir; 119 120/* IPL-lowering/restoring macros */ 121void spl0(void); 122 123static __inline void 124splx(int s) 125{ 126 if (s == ALPHA_PSL_IPL_0 && ssir != 0) 127 spl0(); 128 else 129 alpha_pal_swpipl(s); 130} 131#define spllowersoftclock() ((void)alpha_pal_swpipl(ALPHA_PSL_IPL_SOFT)) 132 133/* IPL-raising functions/macros */ 134static __inline int 135_splraise(int s) 136{ 137 int cur = alpha_pal_rdps() & ALPHA_PSL_IPL_MASK; 138 return (s > cur ? alpha_pal_swpipl(s) : cur); 139} 140#define splsoft() _splraise(ALPHA_PSL_IPL_SOFT) 141#define splsoftserial() splsoft() 142#define splsoftclock() splsoft() 143#define splsoftnet() splsoft() 144#define splnet() _splraise(ALPHA_PSL_IPL_IO) 145#define splbio() _splraise(ALPHA_PSL_IPL_IO) 146#define splvm() _splraise(ALPHA_PSL_IPL_IO) 147#define spltty() _splraise(ALPHA_PSL_IPL_IO) 148#define splserial() _splraise(ALPHA_PSL_IPL_IO) 149#define splclock() _splraise(ALPHA_PSL_IPL_CLOCK) 150#define splstatclock() _splraise(ALPHA_PSL_IPL_CLOCK) 151#define splhigh() _splraise(ALPHA_PSL_IPL_HIGH) 152 153#define splsched() splhigh() 154#define spllock() splhigh() 155#define spllpt() spltty() 156 157/* 158 * Interprocessor interrupts. In order how we want them processed. 159 */ 160#define ALPHA_IPI_HALT 0x0000000000000001UL 161#define ALPHA_IPI_TBIA 0x0000000000000002UL 162#define ALPHA_IPI_TBIAP 0x0000000000000004UL 163#define ALPHA_IPI_SHOOTDOWN 0x0000000000000008UL 164#define ALPHA_IPI_IMB 0x0000000000000010UL 165#define ALPHA_IPI_AST 0x0000000000000020UL 166#define ALPHA_IPI_SYNCH_FPU 0x0000000000000040UL 167#define ALPHA_IPI_DISCARD_FPU 0x0000000000000080UL 168#define ALPHA_IPI_PAUSE 0x0000000000000100UL 169#define ALPHA_IPI_PMAP_REACTIVATE 0x0000000000000200UL 170 171#define ALPHA_NIPIS 10 /* must not exceed 64 */ 172 173struct cpu_info; 174struct trapframe; 175 176void alpha_ipi_init(struct cpu_info *); 177void alpha_ipi_process(struct cpu_info *, struct trapframe *); 178void alpha_send_ipi(unsigned long, unsigned long); 179void alpha_broadcast_ipi(unsigned long); 180void alpha_multicast_ipi(unsigned long, unsigned long); 181 182/* 183 * Alpha shared-interrupt-line common code. 184 */ 185 186struct alpha_shared_intrhand { 187 TAILQ_ENTRY(alpha_shared_intrhand) 188 ih_q; 189 struct alpha_shared_intr *ih_intrhead; 190 int (*ih_fn)(void *); 191 void *ih_arg; 192 int ih_level; 193 unsigned int ih_num; 194}; 195 196struct alpha_shared_intr { 197 TAILQ_HEAD(,alpha_shared_intrhand) 198 intr_q; 199 struct evcnt intr_evcnt; 200 char *intr_string; 201 void *intr_private; 202 int intr_sharetype; 203 int intr_dfltsharetype; 204 int intr_nstrays; 205 int intr_maxstrays; 206}; 207 208#define ALPHA_SHARED_INTR_DISABLE(asi, num) \ 209 ((asi)[num].intr_maxstrays != 0 && \ 210 (asi)[num].intr_nstrays == (asi)[num].intr_maxstrays) 211 212#define setsoft(x) atomic_setbits_ulong(&ssir, 1 << (x)) 213 214struct alpha_soft_intrhand { 215 TAILQ_ENTRY(alpha_soft_intrhand) 216 sih_q; 217 struct alpha_soft_intr *sih_intrhead; 218 void (*sih_fn)(void *); 219 void *sih_arg; 220 int sih_pending; 221}; 222 223struct alpha_soft_intr { 224 TAILQ_HEAD(, alpha_soft_intrhand) 225 softintr_q; 226 struct evcnt softintr_evcnt; 227 struct simplelock softintr_slock; 228 unsigned long softintr_ipl; 229}; 230 231void *softintr_establish(int, void (*)(void *), void *); 232void softintr_disestablish(void *); 233void softintr_init(void); 234void softintr_dispatch(void); 235 236#define softintr_schedule(arg) \ 237do { \ 238 struct alpha_soft_intrhand *__sih = (arg); \ 239 struct alpha_soft_intr *__si = __sih->sih_intrhead; \ 240 int __s; \ 241 \ 242 __s = splhigh(); \ 243 simple_lock(&__si->softintr_slock); \ 244 if (__sih->sih_pending == 0) { \ 245 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 246 __sih->sih_pending = 1; \ 247 setsoft(__si->softintr_ipl); \ 248 } \ 249 simple_unlock(&__si->softintr_slock); \ 250 splx(__s); \ 251} while (0) 252 253/* XXX For legacy software interrupts. */ 254extern struct alpha_soft_intrhand *softnet_intrhand; 255 256#define setsoftnet() softintr_schedule(softnet_intrhand) 257 258struct alpha_shared_intr *alpha_shared_intr_alloc(unsigned int, unsigned int); 259int alpha_shared_intr_dispatch(struct alpha_shared_intr *, 260 unsigned int); 261void *alpha_shared_intr_establish(struct alpha_shared_intr *, 262 unsigned int, int, int, int (*)(void *), void *, const char *); 263void alpha_shared_intr_disestablish(struct alpha_shared_intr *, 264 void *, const char *); 265int alpha_shared_intr_get_sharetype(struct alpha_shared_intr *, 266 unsigned int); 267int alpha_shared_intr_isactive(struct alpha_shared_intr *, 268 unsigned int); 269void alpha_shared_intr_set_dfltsharetype(struct alpha_shared_intr *, 270 unsigned int, int); 271void alpha_shared_intr_set_maxstrays(struct alpha_shared_intr *, 272 unsigned int, int); 273void alpha_shared_intr_stray(struct alpha_shared_intr *, unsigned int, 274 const char *); 275void alpha_shared_intr_set_private(struct alpha_shared_intr *, 276 unsigned int, void *); 277void *alpha_shared_intr_get_private(struct alpha_shared_intr *, 278 unsigned int); 279char *alpha_shared_intr_string(struct alpha_shared_intr *, 280 unsigned int); 281struct evcnt *alpha_shared_intr_evcnt(struct alpha_shared_intr *, 282 unsigned int); 283 284void set_iointr(void (*)(void *, unsigned long)); 285 286#endif /* _KERNEL */ 287#endif /* ! _ALPHA_INTR_H_ */ 288