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296373 |
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04-Mar-2016 |
marius |
- Copy stable/10@296371 to releng/10.3 in preparation for 10.3-RC1 builds. - Update newvers.sh to reflect RC1. - Update __FreeBSD_version to reflect 10.3. - Update default pkg(8) configuration to use the quarterly branch.
Approved by: re (implicit) |
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260473 |
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09-Jan-2014 |
mav |
MFC r259197: Do not DELAY() for P-state transition unless we want to see the result.
Intel manual says: "If a transition is already in progress, transition to a new value will subsequently take effect. Reads of IA32_PERF_CTL determine the last targeted operating point." So seems it should be fine to just trigger wanted transition and go. Linux does the same.
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256281 |
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10-Oct-2013 |
gjb |
Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation
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241885 |
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22-Oct-2012 |
eadler |
This isn't functionally identical. In some cases a hint to disable unit 0 would in fact disable all units.
This reverts r241856
Approved by: cperciva (implicit)
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241856 |
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22-Oct-2012 |
eadler |
Now that device disabling is generic, remove extraneous code from the device drivers that used to provide this feature.
Reviewed by: des Approved by: cperciva MFC after: 1 week
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220433 |
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07-Apr-2011 |
jkim |
Use atomic load & store for TSC frequency. It may be overkill for amd64 but safer for i386 because it can be easily over 4 GHz now. More worse, it can be easily changed by user with 'machdep.tsc_freq' tunable (directly) or cpufreq(4) (indirectly). Note it is intentionally not used in performance critical paths to avoid performance regression (but we should, in theory). Alternatively, we may add "virtual TSC" with lower frequency if maximum frequency overflows 32 bits (and ignore possible incoherency as we do now).
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219046 |
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25-Feb-2011 |
jkim |
Set C1 "I/O then Halt" capability bit for Intel EIST. Some broken BIOSes refuse to load external SSDTs if this bit is unset for _PDC. It seems Linux and OpenSolaris did the same long ago.
MFC after: 1 week
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212721 |
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16-Sep-2010 |
mav |
Few whitespace cleanups and comments tunings.
Submitted by: arundel
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209339 |
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19-Jun-2010 |
mav |
Core i5, same as previously Core2Duo, found to not set P-state for single core lower then set on other cores. Do not try to test P-states on attach on SMP systems. It is hopeless now and will just pollute verbose logs. If needed, check still can be forced via loader tunable.
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204309 |
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25-Feb-2010 |
attilio |
Introduce the new kernel sub-tree x86 which should contain all the code shared and generalized between our current amd64, i386 and pc98.
This is just an initial step that should lead to a more complete effort. For the moment, a very simple porting of cpufreq modules, BIOS calls and the whole MD specific ISA bus part is added to the sub-tree but ideally a lot of code might be added and more shared support should grow.
Sponsored by: Sandvine Incorporated Reviewed by: emaste, kib, jhb, imp Discussed on: arch MFC: 3 weeks
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199273 |
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14-Nov-2009 |
mav |
Previous solution appeared to be unsufficient. After additional testing I have found that it is not only desktop CPUs problem. but mobile also. Probably AP on laptops just started initially at lower frequency, hiding the problem.
Disable frequency validation by default, for systems with more then one CPU, until we can implement it properly. It looks like making more harm now then benefits. Add 'hw.est.strict' loader tunable to control it.
Now my iXsystems Invincibook is able to run at 800MHz lowest frequency, instead of 1200MHz before, when 800MHz was incorrectly reported invalid.
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199269 |
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14-Nov-2009 |
mav |
Retry only once, if BIOS is completely broken and gives zero freqs.
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199268 |
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14-Nov-2009 |
mav |
Desktop Core2Duo/Core2Quad CPUs are unable to control frequency of single CPU core, only pair of them. As result, both cores are running on highest one of requested frequencies, and that is reported by status register. Such behavior confuses frequency validation logic, as it runs on only one core, as SMP is not yet launched, making EIST completely unusable.
To workaround this, add check for validation result. If we haven't found at least two usable frequencies, then probably we are looking bad and have to trust data provided by BIOS as-is.
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193530 |
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05-Jun-2009 |
jkim |
Import ACPICA 20090521.
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186797 |
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05-Jan-2009 |
jkim |
Add Centaur/IDT/VIA vendor ID for Nano family, which has long mode support.
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185341 |
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26-Nov-2008 |
jkim |
Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").
Reviewed by: jhb, peter (early amd64 version)
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182908 |
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10-Sep-2008 |
jhb |
Add a proper detach method to the est(4) driver using cpufreq_unregister().
MFC after: 1 week
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182201 |
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26-Aug-2008 |
jhb |
Disable the code to generate a simple table from the status MSR by default. This can be enabled by setting the 'hw.est.msr_info' tunable to 1.
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182048 |
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23-Aug-2008 |
jhb |
If we are unable to obtain a frequency list from either ACPI or the static tables, then attempt to build a simple list containing just the high and low frequencies based on the current CPU frequency calculated during boot and the contents of the MSR.
MFC after: 1 month
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181691 |
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13-Aug-2008 |
jhb |
Attach the cpufreq child devices with specific orders to enforce relative priority of some of the drivers that manage the same state (e.g. ichss0 vs est0). Specifically, powernow, est, and p4tcc are added at order 10, ichss at order 20, and smist at order 30. Previously, some laptops were seeing both ichss0 and est0 attaching and stomping on each other.
XXX: This isn't quite ideal, but works with the existing hacks, I think what we really want instead is a single "speedstep0" device for CPUs that the ichss, est, and smist drivers probe (but with differing priorities).
MFC after: 1 week
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179445 |
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30-May-2008 |
jhb |
After probing the available frequency settings, restore the CPU to run at whatever frequency it started at instead of always picking the highest frequency. The first version of this driver attempted to do this, but it set the speed to the first frequency in the list rather than the value it had saved.
MFC after: 1 week Discussed with: rpaulo, phk
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178719 |
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02-May-2008 |
rpaulo |
Remove unused variable saved_id16.
Pointy hat to: me Pointed out by: jhb MFC after: 1 week
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177296 |
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17-Mar-2008 |
phk |
Increase time we wait for things to settle to 1 millisecond, 10 microseconds is too short.
Always set the cpu to the highest frequency so that we get through boot and don't handicap cpus where powerd(8) is not used.
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177040 |
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10-Mar-2008 |
jhb |
- Don't execute cpuid to fetch the features. We already have the features present in cpu_feature2. Also, use CPUID2_EST rather than a magic number. - Don't free the ACPI settings list in detach if we are going to fail the request. Otherwise an attempt to kldunload est would free the array but the driver would keep trying to use it.
MFC after: 1 week
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176714 |
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01-Mar-2008 |
gibbs |
In est_acpi_info(), initialize count before passing its pointer to CPUFREQ_DRV_SETTINGS(). The value of count on input is used to prefent overflow of the settings buffer passed into CPUFREQ_DRV_SETTINGS().
This corrects the "est: CPU supports Enhanced Speedstep, but is not recognized." error on my system.
MFC after: 1 week
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176649 |
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28-Feb-2008 |
rpaulo |
Validate the id16 values gathered from ACPI (previously a TODO item). Style changes by me and njl.
Approved by: njl (mentor) Reviewed by: njl (mentor) Submitted by: Takeharu KATO <takeharu1219 at ybb.ne.jp> PR: 119350 MFC after: 1 week
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158446 |
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11-May-2006 |
njl |
Add support for the VIA C7-M processor family.
Remove an unnecessary check of the table's bus clock. CPUs that support this feature export only the high/low settings via the MSR, packed into 32 bits.
Hardware from: Centaur Technologies MFC after: 1 week
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155996 |
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25-Feb-2006 |
cperciva |
Add frequency-voltage tables for Intel 778, 758, 773, 753, and 733J processors.
Obtained from: Intel Datasheet 302189-008
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148583 |
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31-Jul-2005 |
cperciva |
Print cpu_vendor and the MSR value if we don't support this processor even though we're not asking people to contact us.
Requested by: njl
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148578 |
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31-Jul-2005 |
cperciva |
Remove the instruction to "contact the maintainer" for unrecognized CPUs. Intel refuses to give me the information I need, and getting more emails about this doesn't help.
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144881 |
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10-Apr-2005 |
njl |
Properly terminate the table generated from ACPI info. The cpufreq settings are length-counted while the EST table is null-terminated. This fixes extra garbage states being reported with ACPI probing.
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144630 |
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04-Apr-2005 |
njl |
Add support for _PDC/_OSC by advertising that we support direct access to the PERF_CTL/STS MSRs via the new acpi_get_features() method. This should allow newer systems to use SpeedStep.
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143902 |
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21-Mar-2005 |
njl |
Add support for probing EST settings from ACPI. This should handle more modern CPUs that have multiple VID#s that aren't detectable via public methods. We use the control value from acpi_perf as the id16 for setting a given frequency.
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142625 |
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27-Feb-2005 |
njl |
Make a pass through all drivers checking specs for desired behavior on SMP systems. It appears all drivers except ichss should attach to each CPU and that settings should be performed on each CPU. Add comments about this. Also, add a guard for p4tcc's identify method being called more than once.
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142394 |
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24-Feb-2005 |
njl |
Correct an off-by-one error in the number of settings est announces. The extraneous "0" state was not fatal but useless.
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142203 |
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22-Feb-2005 |
njl |
Support disabling individual cpufreq drivers with hints, e.g., hint.ichss.0.disabled="1"
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#
142140 |
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20-Feb-2005 |
njl |
Add the Enhanced SpeedStep driver (EST). Currently, this driver only works on the previous generation of Pentium-M processors (Banias). Support for Dothan and later processors involves working with acpi_perf(4) to extract information about supported states. This driver should work on MP systems including HTT. It is experimental and may have a few bugs but has been tested to not crash at least.
Thanks to Colin Percival for his initial work on this driver.
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