est.c revision 182048
1/*- 2 * Copyright (c) 2004 Colin Percival 3 * Copyright (c) 2005 Nate Lawson 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted providing that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/i386/cpufreq/est.c 182048 2008-08-23 12:53:42Z jhb $"); 30 31#include <sys/param.h> 32#include <sys/bus.h> 33#include <sys/cpu.h> 34#include <sys/kernel.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37#include <sys/smp.h> 38#include <sys/systm.h> 39 40#include "cpufreq_if.h" 41#include <machine/clock.h> 42#include <machine/md_var.h> 43#include <machine/specialreg.h> 44 45#include <contrib/dev/acpica/acpi.h> 46#include <dev/acpica/acpivar.h> 47#include "acpi_if.h" 48 49/* Status/control registers (from the IA-32 System Programming Guide). */ 50#define MSR_PERF_STATUS 0x198 51#define MSR_PERF_CTL 0x199 52 53/* Register and bit for enabling SpeedStep. */ 54#define MSR_MISC_ENABLE 0x1a0 55#define MSR_SS_ENABLE (1<<16) 56 57/* Frequency and MSR control values. */ 58typedef struct { 59 uint16_t freq; 60 uint16_t volts; 61 uint16_t id16; 62 int power; 63} freq_info; 64 65/* Identifying characteristics of a processor and supported frequencies. */ 66typedef struct { 67 const char *vendor; 68 uint32_t id32; 69 freq_info *freqtab; 70} cpu_info; 71 72struct est_softc { 73 device_t dev; 74 int acpi_settings; 75 int msr_settings; 76 freq_info *freq_list; 77}; 78 79/* Convert MHz and mV into IDs for passing to the MSR. */ 80#define ID16(MHz, mV, bus_clk) \ 81 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4)) 82#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \ 83 ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk))) 84 85/* Format for storing IDs in our table. */ 86#define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \ 87 { MHz, mV, ID16(MHz, mV, bus_clk), mW } 88#define FREQ_INFO(MHz, mV, bus_clk) \ 89 FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN) 90#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \ 91 { intel_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 92#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \ 93 { centaur_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 94 95const char intel_id[] = "GenuineIntel"; 96const char centaur_id[] = "CentaurHauls"; 97 98/* Default bus clock value for Centrino processors. */ 99#define INTEL_BUS_CLK 100 100 101/* XXX Update this if new CPUs have more settings. */ 102#define EST_MAX_SETTINGS 10 103CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS); 104 105/* Estimate in microseconds of latency for performing a transition. */ 106#define EST_TRANS_LAT 1000 107 108/* 109 * Frequency (MHz) and voltage (mV) settings. Data from the 110 * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5. 111 * 112 * Dothan processors have multiple VID#s with different settings for 113 * each VID#. Since we can't uniquely identify this info 114 * without undisclosed methods from Intel, we can't support newer 115 * processors with this table method. If ACPI Px states are supported, 116 * we get info from them. 117 */ 118static freq_info PM17_130[] = { 119 /* 130nm 1.70GHz Pentium M */ 120 FREQ_INFO(1700, 1484, INTEL_BUS_CLK), 121 FREQ_INFO(1400, 1308, INTEL_BUS_CLK), 122 FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 123 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 124 FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 125 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 126 FREQ_INFO( 0, 0, 1), 127}; 128static freq_info PM16_130[] = { 129 /* 130nm 1.60GHz Pentium M */ 130 FREQ_INFO(1600, 1484, INTEL_BUS_CLK), 131 FREQ_INFO(1400, 1420, INTEL_BUS_CLK), 132 FREQ_INFO(1200, 1276, INTEL_BUS_CLK), 133 FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 134 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 135 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 136 FREQ_INFO( 0, 0, 1), 137}; 138static freq_info PM15_130[] = { 139 /* 130nm 1.50GHz Pentium M */ 140 FREQ_INFO(1500, 1484, INTEL_BUS_CLK), 141 FREQ_INFO(1400, 1452, INTEL_BUS_CLK), 142 FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 143 FREQ_INFO(1000, 1228, INTEL_BUS_CLK), 144 FREQ_INFO( 800, 1116, INTEL_BUS_CLK), 145 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 146 FREQ_INFO( 0, 0, 1), 147}; 148static freq_info PM14_130[] = { 149 /* 130nm 1.40GHz Pentium M */ 150 FREQ_INFO(1400, 1484, INTEL_BUS_CLK), 151 FREQ_INFO(1200, 1436, INTEL_BUS_CLK), 152 FREQ_INFO(1000, 1308, INTEL_BUS_CLK), 153 FREQ_INFO( 800, 1180, INTEL_BUS_CLK), 154 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 155 FREQ_INFO( 0, 0, 1), 156}; 157static freq_info PM13_130[] = { 158 /* 130nm 1.30GHz Pentium M */ 159 FREQ_INFO(1300, 1388, INTEL_BUS_CLK), 160 FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 161 FREQ_INFO(1000, 1292, INTEL_BUS_CLK), 162 FREQ_INFO( 800, 1260, INTEL_BUS_CLK), 163 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 164 FREQ_INFO( 0, 0, 1), 165}; 166static freq_info PM13_LV_130[] = { 167 /* 130nm 1.30GHz Low Voltage Pentium M */ 168 FREQ_INFO(1300, 1180, INTEL_BUS_CLK), 169 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 170 FREQ_INFO(1100, 1100, INTEL_BUS_CLK), 171 FREQ_INFO(1000, 1020, INTEL_BUS_CLK), 172 FREQ_INFO( 900, 1004, INTEL_BUS_CLK), 173 FREQ_INFO( 800, 988, INTEL_BUS_CLK), 174 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 175 FREQ_INFO( 0, 0, 1), 176}; 177static freq_info PM12_LV_130[] = { 178 /* 130 nm 1.20GHz Low Voltage Pentium M */ 179 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 180 FREQ_INFO(1100, 1164, INTEL_BUS_CLK), 181 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 182 FREQ_INFO( 900, 1020, INTEL_BUS_CLK), 183 FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 184 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 185 FREQ_INFO( 0, 0, 1), 186}; 187static freq_info PM11_LV_130[] = { 188 /* 130 nm 1.10GHz Low Voltage Pentium M */ 189 FREQ_INFO(1100, 1180, INTEL_BUS_CLK), 190 FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 191 FREQ_INFO( 900, 1100, INTEL_BUS_CLK), 192 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 193 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 194 FREQ_INFO( 0, 0, 1), 195}; 196static freq_info PM11_ULV_130[] = { 197 /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */ 198 FREQ_INFO(1100, 1004, INTEL_BUS_CLK), 199 FREQ_INFO(1000, 988, INTEL_BUS_CLK), 200 FREQ_INFO( 900, 972, INTEL_BUS_CLK), 201 FREQ_INFO( 800, 956, INTEL_BUS_CLK), 202 FREQ_INFO( 600, 844, INTEL_BUS_CLK), 203 FREQ_INFO( 0, 0, 1), 204}; 205static freq_info PM10_ULV_130[] = { 206 /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */ 207 FREQ_INFO(1000, 1004, INTEL_BUS_CLK), 208 FREQ_INFO( 900, 988, INTEL_BUS_CLK), 209 FREQ_INFO( 800, 972, INTEL_BUS_CLK), 210 FREQ_INFO( 600, 844, INTEL_BUS_CLK), 211 FREQ_INFO( 0, 0, 1), 212}; 213 214/* 215 * Data from "Intel Pentium M Processor on 90nm Process with 216 * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5. 217 */ 218static freq_info PM_765A_90[] = { 219 /* 90 nm 2.10GHz Pentium M, VID #A */ 220 FREQ_INFO(2100, 1340, INTEL_BUS_CLK), 221 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 222 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 223 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 224 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 225 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 226 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 227 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 228 FREQ_INFO( 0, 0, 1), 229}; 230static freq_info PM_765B_90[] = { 231 /* 90 nm 2.10GHz Pentium M, VID #B */ 232 FREQ_INFO(2100, 1324, INTEL_BUS_CLK), 233 FREQ_INFO(1800, 1260, INTEL_BUS_CLK), 234 FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 235 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 236 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 237 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 238 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 239 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 240 FREQ_INFO( 0, 0, 1), 241}; 242static freq_info PM_765C_90[] = { 243 /* 90 nm 2.10GHz Pentium M, VID #C */ 244 FREQ_INFO(2100, 1308, INTEL_BUS_CLK), 245 FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 246 FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 247 FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 248 FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 249 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 250 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 251 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 252 FREQ_INFO( 0, 0, 1), 253}; 254static freq_info PM_765E_90[] = { 255 /* 90 nm 2.10GHz Pentium M, VID #E */ 256 FREQ_INFO(2100, 1356, INTEL_BUS_CLK), 257 FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 258 FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 259 FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 260 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 261 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 262 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 263 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 264 FREQ_INFO( 0, 0, 1), 265}; 266static freq_info PM_755A_90[] = { 267 /* 90 nm 2.00GHz Pentium M, VID #A */ 268 FREQ_INFO(2000, 1340, INTEL_BUS_CLK), 269 FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 270 FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 271 FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 272 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 273 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 274 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 275 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 276 FREQ_INFO( 0, 0, 1), 277}; 278static freq_info PM_755B_90[] = { 279 /* 90 nm 2.00GHz Pentium M, VID #B */ 280 FREQ_INFO(2000, 1324, INTEL_BUS_CLK), 281 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 282 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 283 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 284 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 285 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 286 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 287 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 288 FREQ_INFO( 0, 0, 1), 289}; 290static freq_info PM_755C_90[] = { 291 /* 90 nm 2.00GHz Pentium M, VID #C */ 292 FREQ_INFO(2000, 1308, INTEL_BUS_CLK), 293 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 294 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 295 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 296 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 297 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 298 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 299 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 300 FREQ_INFO( 0, 0, 1), 301}; 302static freq_info PM_755D_90[] = { 303 /* 90 nm 2.00GHz Pentium M, VID #D */ 304 FREQ_INFO(2000, 1276, INTEL_BUS_CLK), 305 FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 306 FREQ_INFO(1600, 1196, INTEL_BUS_CLK), 307 FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 308 FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 309 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 310 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 311 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 312 FREQ_INFO( 0, 0, 1), 313}; 314static freq_info PM_745A_90[] = { 315 /* 90 nm 1.80GHz Pentium M, VID #A */ 316 FREQ_INFO(1800, 1340, INTEL_BUS_CLK), 317 FREQ_INFO(1600, 1292, INTEL_BUS_CLK), 318 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 319 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 320 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 321 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 322 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 323 FREQ_INFO( 0, 0, 1), 324}; 325static freq_info PM_745B_90[] = { 326 /* 90 nm 1.80GHz Pentium M, VID #B */ 327 FREQ_INFO(1800, 1324, INTEL_BUS_CLK), 328 FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 329 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 330 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 331 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 332 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 333 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 334 FREQ_INFO( 0, 0, 1), 335}; 336static freq_info PM_745C_90[] = { 337 /* 90 nm 1.80GHz Pentium M, VID #C */ 338 FREQ_INFO(1800, 1308, INTEL_BUS_CLK), 339 FREQ_INFO(1600, 1260, INTEL_BUS_CLK), 340 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 341 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 342 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 343 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 344 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 345 FREQ_INFO( 0, 0, 1), 346}; 347static freq_info PM_745D_90[] = { 348 /* 90 nm 1.80GHz Pentium M, VID #D */ 349 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 350 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 351 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 352 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 353 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 354 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 355 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 356 FREQ_INFO( 0, 0, 1), 357}; 358static freq_info PM_735A_90[] = { 359 /* 90 nm 1.70GHz Pentium M, VID #A */ 360 FREQ_INFO(1700, 1340, INTEL_BUS_CLK), 361 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 362 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 363 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 364 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 365 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 366 FREQ_INFO( 0, 0, 1), 367}; 368static freq_info PM_735B_90[] = { 369 /* 90 nm 1.70GHz Pentium M, VID #B */ 370 FREQ_INFO(1700, 1324, INTEL_BUS_CLK), 371 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 372 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 373 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 374 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 375 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 376 FREQ_INFO( 0, 0, 1), 377}; 378static freq_info PM_735C_90[] = { 379 /* 90 nm 1.70GHz Pentium M, VID #C */ 380 FREQ_INFO(1700, 1308, INTEL_BUS_CLK), 381 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 382 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 383 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 384 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 385 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 386 FREQ_INFO( 0, 0, 1), 387}; 388static freq_info PM_735D_90[] = { 389 /* 90 nm 1.70GHz Pentium M, VID #D */ 390 FREQ_INFO(1700, 1276, INTEL_BUS_CLK), 391 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 392 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 393 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 394 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 395 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 396 FREQ_INFO( 0, 0, 1), 397}; 398static freq_info PM_725A_90[] = { 399 /* 90 nm 1.60GHz Pentium M, VID #A */ 400 FREQ_INFO(1600, 1340, INTEL_BUS_CLK), 401 FREQ_INFO(1400, 1276, INTEL_BUS_CLK), 402 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 403 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 404 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 405 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 406 FREQ_INFO( 0, 0, 1), 407}; 408static freq_info PM_725B_90[] = { 409 /* 90 nm 1.60GHz Pentium M, VID #B */ 410 FREQ_INFO(1600, 1324, INTEL_BUS_CLK), 411 FREQ_INFO(1400, 1260, INTEL_BUS_CLK), 412 FREQ_INFO(1200, 1196, INTEL_BUS_CLK), 413 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 414 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 415 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 416 FREQ_INFO( 0, 0, 1), 417}; 418static freq_info PM_725C_90[] = { 419 /* 90 nm 1.60GHz Pentium M, VID #C */ 420 FREQ_INFO(1600, 1308, INTEL_BUS_CLK), 421 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 422 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 423 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 424 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 425 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 426 FREQ_INFO( 0, 0, 1), 427}; 428static freq_info PM_725D_90[] = { 429 /* 90 nm 1.60GHz Pentium M, VID #D */ 430 FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 431 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 432 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 433 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 434 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 435 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 436 FREQ_INFO( 0, 0, 1), 437}; 438static freq_info PM_715A_90[] = { 439 /* 90 nm 1.50GHz Pentium M, VID #A */ 440 FREQ_INFO(1500, 1340, INTEL_BUS_CLK), 441 FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 442 FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 443 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 444 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 445 FREQ_INFO( 0, 0, 1), 446}; 447static freq_info PM_715B_90[] = { 448 /* 90 nm 1.50GHz Pentium M, VID #B */ 449 FREQ_INFO(1500, 1324, INTEL_BUS_CLK), 450 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 451 FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 452 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 453 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 454 FREQ_INFO( 0, 0, 1), 455}; 456static freq_info PM_715C_90[] = { 457 /* 90 nm 1.50GHz Pentium M, VID #C */ 458 FREQ_INFO(1500, 1308, INTEL_BUS_CLK), 459 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 460 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 461 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 462 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 463 FREQ_INFO( 0, 0, 1), 464}; 465static freq_info PM_715D_90[] = { 466 /* 90 nm 1.50GHz Pentium M, VID #D */ 467 FREQ_INFO(1500, 1276, INTEL_BUS_CLK), 468 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 469 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 470 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 471 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 472 FREQ_INFO( 0, 0, 1), 473}; 474static freq_info PM_778_90[] = { 475 /* 90 nm 1.60GHz Low Voltage Pentium M */ 476 FREQ_INFO(1600, 1116, INTEL_BUS_CLK), 477 FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 478 FREQ_INFO(1400, 1100, INTEL_BUS_CLK), 479 FREQ_INFO(1300, 1084, INTEL_BUS_CLK), 480 FREQ_INFO(1200, 1068, INTEL_BUS_CLK), 481 FREQ_INFO(1100, 1052, INTEL_BUS_CLK), 482 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 483 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 484 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 485 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 486 FREQ_INFO( 0, 0, 1), 487}; 488static freq_info PM_758_90[] = { 489 /* 90 nm 1.50GHz Low Voltage Pentium M */ 490 FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 491 FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 492 FREQ_INFO(1300, 1100, INTEL_BUS_CLK), 493 FREQ_INFO(1200, 1084, INTEL_BUS_CLK), 494 FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 495 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 496 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 497 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 498 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 499 FREQ_INFO( 0, 0, 1), 500}; 501static freq_info PM_738_90[] = { 502 /* 90 nm 1.40GHz Low Voltage Pentium M */ 503 FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 504 FREQ_INFO(1300, 1116, INTEL_BUS_CLK), 505 FREQ_INFO(1200, 1100, INTEL_BUS_CLK), 506 FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 507 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 508 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 509 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 510 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 511 FREQ_INFO( 0, 0, 1), 512}; 513static freq_info PM_773G_90[] = { 514 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */ 515 FREQ_INFO(1300, 956, INTEL_BUS_CLK), 516 FREQ_INFO(1200, 940, INTEL_BUS_CLK), 517 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 518 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 519 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 520 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 521 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 522}; 523static freq_info PM_773H_90[] = { 524 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */ 525 FREQ_INFO(1300, 940, INTEL_BUS_CLK), 526 FREQ_INFO(1200, 924, INTEL_BUS_CLK), 527 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 528 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 529 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 530 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 531 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 532}; 533static freq_info PM_773I_90[] = { 534 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */ 535 FREQ_INFO(1300, 924, INTEL_BUS_CLK), 536 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 537 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 538 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 539 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 540 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 541 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 542}; 543static freq_info PM_773J_90[] = { 544 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */ 545 FREQ_INFO(1300, 908, INTEL_BUS_CLK), 546 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 547 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 548 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 549 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 550 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 551 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 552}; 553static freq_info PM_773K_90[] = { 554 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */ 555 FREQ_INFO(1300, 892, INTEL_BUS_CLK), 556 FREQ_INFO(1200, 892, INTEL_BUS_CLK), 557 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 558 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 559 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 560 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 561 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 562}; 563static freq_info PM_773L_90[] = { 564 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */ 565 FREQ_INFO(1300, 876, INTEL_BUS_CLK), 566 FREQ_INFO(1200, 876, INTEL_BUS_CLK), 567 FREQ_INFO(1100, 860, INTEL_BUS_CLK), 568 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 569 FREQ_INFO( 900, 844, INTEL_BUS_CLK), 570 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 571 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 572}; 573static freq_info PM_753G_90[] = { 574 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */ 575 FREQ_INFO(1200, 956, INTEL_BUS_CLK), 576 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 577 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 578 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 579 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 580 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 581}; 582static freq_info PM_753H_90[] = { 583 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */ 584 FREQ_INFO(1200, 940, INTEL_BUS_CLK), 585 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 586 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 587 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 588 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 589 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 590}; 591static freq_info PM_753I_90[] = { 592 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */ 593 FREQ_INFO(1200, 924, INTEL_BUS_CLK), 594 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 595 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 596 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 597 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 598 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 599}; 600static freq_info PM_753J_90[] = { 601 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */ 602 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 603 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 604 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 605 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 606 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 607 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 608}; 609static freq_info PM_753K_90[] = { 610 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */ 611 FREQ_INFO(1200, 892, INTEL_BUS_CLK), 612 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 613 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 614 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 615 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 616 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 617}; 618static freq_info PM_753L_90[] = { 619 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */ 620 FREQ_INFO(1200, 876, INTEL_BUS_CLK), 621 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 622 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 623 FREQ_INFO( 900, 844, INTEL_BUS_CLK), 624 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 625 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 626}; 627 628static freq_info PM_733JG_90[] = { 629 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */ 630 FREQ_INFO(1100, 956, INTEL_BUS_CLK), 631 FREQ_INFO(1000, 940, INTEL_BUS_CLK), 632 FREQ_INFO( 900, 908, INTEL_BUS_CLK), 633 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 634 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 635}; 636static freq_info PM_733JH_90[] = { 637 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */ 638 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 639 FREQ_INFO(1000, 924, INTEL_BUS_CLK), 640 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 641 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 642 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 643}; 644static freq_info PM_733JI_90[] = { 645 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */ 646 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 647 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 648 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 649 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 650 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 651}; 652static freq_info PM_733JJ_90[] = { 653 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */ 654 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 655 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 656 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 657 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 658 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 659}; 660static freq_info PM_733JK_90[] = { 661 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */ 662 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 663 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 664 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 665 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 666 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 667}; 668static freq_info PM_733JL_90[] = { 669 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */ 670 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 671 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 672 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 673 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 674 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 675}; 676static freq_info PM_733_90[] = { 677 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */ 678 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 679 FREQ_INFO(1000, 924, INTEL_BUS_CLK), 680 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 681 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 682 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 683 FREQ_INFO( 0, 0, 1), 684}; 685static freq_info PM_723_90[] = { 686 /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */ 687 FREQ_INFO(1000, 940, INTEL_BUS_CLK), 688 FREQ_INFO( 900, 908, INTEL_BUS_CLK), 689 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 690 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 691 FREQ_INFO( 0, 0, 1), 692}; 693 694/* 695 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants. 696 * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet. 697 */ 698static freq_info C7M_795[] = { 699 /* 2.00GHz Centaur C7-M 533 Mhz FSB */ 700 FREQ_INFO_PWR(2000, 1148, 133, 20000), 701 FREQ_INFO_PWR(1867, 1132, 133, 18000), 702 FREQ_INFO_PWR(1600, 1100, 133, 15000), 703 FREQ_INFO_PWR(1467, 1052, 133, 13000), 704 FREQ_INFO_PWR(1200, 1004, 133, 10000), 705 FREQ_INFO_PWR( 800, 844, 133, 7000), 706 FREQ_INFO_PWR( 667, 844, 133, 6000), 707 FREQ_INFO_PWR( 533, 844, 133, 5000), 708 FREQ_INFO(0, 0, 1), 709}; 710static freq_info C7M_785[] = { 711 /* 1.80GHz Centaur C7-M 533 Mhz FSB */ 712 FREQ_INFO_PWR(1867, 1148, 133, 18000), 713 FREQ_INFO_PWR(1600, 1100, 133, 15000), 714 FREQ_INFO_PWR(1467, 1052, 133, 13000), 715 FREQ_INFO_PWR(1200, 1004, 133, 10000), 716 FREQ_INFO_PWR( 800, 844, 133, 7000), 717 FREQ_INFO_PWR( 667, 844, 133, 6000), 718 FREQ_INFO_PWR( 533, 844, 133, 5000), 719 FREQ_INFO(0, 0, 1), 720}; 721static freq_info C7M_765[] = { 722 /* 1.60GHz Centaur C7-M 533 Mhz FSB */ 723 FREQ_INFO_PWR(1600, 1084, 133, 15000), 724 FREQ_INFO_PWR(1467, 1052, 133, 13000), 725 FREQ_INFO_PWR(1200, 1004, 133, 10000), 726 FREQ_INFO_PWR( 800, 844, 133, 7000), 727 FREQ_INFO_PWR( 667, 844, 133, 6000), 728 FREQ_INFO_PWR( 533, 844, 133, 5000), 729 FREQ_INFO(0, 0, 1), 730}; 731 732static freq_info C7M_794[] = { 733 /* 2.00GHz Centaur C7-M 400 Mhz FSB */ 734 FREQ_INFO_PWR(2000, 1148, 100, 20000), 735 FREQ_INFO_PWR(1800, 1132, 100, 18000), 736 FREQ_INFO_PWR(1600, 1100, 100, 15000), 737 FREQ_INFO_PWR(1400, 1052, 100, 13000), 738 FREQ_INFO_PWR(1000, 1004, 100, 10000), 739 FREQ_INFO_PWR( 800, 844, 100, 7000), 740 FREQ_INFO_PWR( 600, 844, 100, 6000), 741 FREQ_INFO_PWR( 400, 844, 100, 5000), 742 FREQ_INFO(0, 0, 1), 743}; 744static freq_info C7M_784[] = { 745 /* 1.80GHz Centaur C7-M 400 Mhz FSB */ 746 FREQ_INFO_PWR(1800, 1148, 100, 18000), 747 FREQ_INFO_PWR(1600, 1100, 100, 15000), 748 FREQ_INFO_PWR(1400, 1052, 100, 13000), 749 FREQ_INFO_PWR(1000, 1004, 100, 10000), 750 FREQ_INFO_PWR( 800, 844, 100, 7000), 751 FREQ_INFO_PWR( 600, 844, 100, 6000), 752 FREQ_INFO_PWR( 400, 844, 100, 5000), 753 FREQ_INFO(0, 0, 1), 754}; 755static freq_info C7M_764[] = { 756 /* 1.60GHz Centaur C7-M 400 Mhz FSB */ 757 FREQ_INFO_PWR(1600, 1084, 100, 15000), 758 FREQ_INFO_PWR(1400, 1052, 100, 13000), 759 FREQ_INFO_PWR(1000, 1004, 100, 10000), 760 FREQ_INFO_PWR( 800, 844, 100, 7000), 761 FREQ_INFO_PWR( 600, 844, 100, 6000), 762 FREQ_INFO_PWR( 400, 844, 100, 5000), 763 FREQ_INFO(0, 0, 1), 764}; 765static freq_info C7M_754[] = { 766 /* 1.50GHz Centaur C7-M 400 Mhz FSB */ 767 FREQ_INFO_PWR(1500, 1004, 100, 12000), 768 FREQ_INFO_PWR(1400, 988, 100, 11000), 769 FREQ_INFO_PWR(1000, 940, 100, 9000), 770 FREQ_INFO_PWR( 800, 844, 100, 7000), 771 FREQ_INFO_PWR( 600, 844, 100, 6000), 772 FREQ_INFO_PWR( 400, 844, 100, 5000), 773 FREQ_INFO(0, 0, 1), 774}; 775static freq_info C7M_771[] = { 776 /* 1.20GHz Centaur C7-M 400 Mhz FSB */ 777 FREQ_INFO_PWR(1200, 860, 100, 7000), 778 FREQ_INFO_PWR(1000, 860, 100, 6000), 779 FREQ_INFO_PWR( 800, 844, 100, 5500), 780 FREQ_INFO_PWR( 600, 844, 100, 5000), 781 FREQ_INFO_PWR( 400, 844, 100, 4000), 782 FREQ_INFO(0, 0, 1), 783}; 784 785static freq_info C7M_775_ULV[] = { 786 /* 1.50GHz Centaur C7-M ULV */ 787 FREQ_INFO_PWR(1500, 956, 100, 7500), 788 FREQ_INFO_PWR(1400, 940, 100, 6000), 789 FREQ_INFO_PWR(1000, 860, 100, 5000), 790 FREQ_INFO_PWR( 800, 828, 100, 2800), 791 FREQ_INFO_PWR( 600, 796, 100, 2500), 792 FREQ_INFO_PWR( 400, 796, 100, 2000), 793 FREQ_INFO(0, 0, 1), 794}; 795static freq_info C7M_772_ULV[] = { 796 /* 1.20GHz Centaur C7-M ULV */ 797 FREQ_INFO_PWR(1200, 844, 100, 5000), 798 FREQ_INFO_PWR(1000, 844, 100, 4000), 799 FREQ_INFO_PWR( 800, 828, 100, 2800), 800 FREQ_INFO_PWR( 600, 796, 100, 2500), 801 FREQ_INFO_PWR( 400, 796, 100, 2000), 802 FREQ_INFO(0, 0, 1), 803}; 804static freq_info C7M_779_ULV[] = { 805 /* 1.00GHz Centaur C7-M ULV */ 806 FREQ_INFO_PWR(1000, 796, 100, 3500), 807 FREQ_INFO_PWR( 800, 796, 100, 2800), 808 FREQ_INFO_PWR( 600, 796, 100, 2500), 809 FREQ_INFO_PWR( 400, 796, 100, 2000), 810 FREQ_INFO(0, 0, 1), 811}; 812static freq_info C7M_770_ULV[] = { 813 /* 1.00GHz Centaur C7-M ULV */ 814 FREQ_INFO_PWR(1000, 844, 100, 5000), 815 FREQ_INFO_PWR( 800, 796, 100, 2800), 816 FREQ_INFO_PWR( 600, 796, 100, 2500), 817 FREQ_INFO_PWR( 400, 796, 100, 2000), 818 FREQ_INFO(0, 0, 1), 819}; 820 821static cpu_info ESTprocs[] = { 822 INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK), 823 INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK), 824 INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK), 825 INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK), 826 INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK), 827 INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK), 828 INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK), 829 INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK), 830 INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK), 831 INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK), 832 INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK), 833 INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK), 834 INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK), 835 INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK), 836 INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK), 837 INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK), 838 INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK), 839 INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK), 840 INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK), 841 INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK), 842 INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK), 843 INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK), 844 INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK), 845 INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK), 846 INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK), 847 INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK), 848 INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK), 849 INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK), 850 INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK), 851 INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK), 852 INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK), 853 INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK), 854 INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK), 855 INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK), 856 INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK), 857 INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK), 858 INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK), 859 INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK), 860 INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK), 861 INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK), 862 INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK), 863 INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK), 864 INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK), 865 INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK), 866 INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK), 867 INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK), 868 INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK), 869 INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK), 870 INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK), 871 INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK), 872 INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 873 INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK), 874 INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK), 875 INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK), 876 INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK), 877 INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 878 INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK), 879 880 CENTAUR(C7M_795, 2000, 1148, 533, 844, 133), 881 CENTAUR(C7M_794, 2000, 1148, 400, 844, 100), 882 CENTAUR(C7M_785, 1867, 1148, 533, 844, 133), 883 CENTAUR(C7M_784, 1800, 1148, 400, 844, 100), 884 CENTAUR(C7M_765, 1600, 1084, 533, 844, 133), 885 CENTAUR(C7M_764, 1600, 1084, 400, 844, 100), 886 CENTAUR(C7M_754, 1500, 1004, 400, 844, 100), 887 CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100), 888 CENTAUR(C7M_771, 1200, 860, 400, 844, 100), 889 CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100), 890 CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100), 891 CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100), 892 { NULL, 0, NULL }, 893}; 894 895static void est_identify(driver_t *driver, device_t parent); 896static int est_features(driver_t *driver, u_int *features); 897static int est_probe(device_t parent); 898static int est_attach(device_t parent); 899static int est_detach(device_t parent); 900static int est_get_info(device_t dev); 901static int est_acpi_info(device_t dev, freq_info **freqs); 902static int est_table_info(device_t dev, uint64_t msr, freq_info **freqs); 903static int est_msr_info(device_t dev, uint64_t msr, freq_info **freqs); 904static freq_info *est_get_current(freq_info *freq_list); 905static int est_settings(device_t dev, struct cf_setting *sets, int *count); 906static int est_set(device_t dev, const struct cf_setting *set); 907static int est_get(device_t dev, struct cf_setting *set); 908static int est_type(device_t dev, int *type); 909static int est_set_id16(device_t dev, uint16_t id16, int need_check); 910static void est_get_id16(uint16_t *id16_p); 911 912static device_method_t est_methods[] = { 913 /* Device interface */ 914 DEVMETHOD(device_identify, est_identify), 915 DEVMETHOD(device_probe, est_probe), 916 DEVMETHOD(device_attach, est_attach), 917 DEVMETHOD(device_detach, est_detach), 918 919 /* cpufreq interface */ 920 DEVMETHOD(cpufreq_drv_set, est_set), 921 DEVMETHOD(cpufreq_drv_get, est_get), 922 DEVMETHOD(cpufreq_drv_type, est_type), 923 DEVMETHOD(cpufreq_drv_settings, est_settings), 924 925 /* ACPI interface */ 926 DEVMETHOD(acpi_get_features, est_features), 927 928 {0, 0} 929}; 930 931static driver_t est_driver = { 932 "est", 933 est_methods, 934 sizeof(struct est_softc), 935}; 936 937static devclass_t est_devclass; 938DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0); 939 940static int 941est_features(driver_t *driver, u_int *features) 942{ 943 944 /* Notify the ACPI CPU that we support direct access to MSRs */ 945 *features = ACPI_CAP_PERF_MSRS; 946 return (0); 947} 948 949static void 950est_identify(driver_t *driver, device_t parent) 951{ 952 device_t child; 953 954 /* Make sure we're not being doubly invoked. */ 955 if (device_find_child(parent, "est", -1) != NULL) 956 return; 957 958 /* Check that CPUID is supported and the vendor is Intel.*/ 959 if (cpu_high == 0 || (strcmp(cpu_vendor, intel_id) != 0 && 960 strcmp(cpu_vendor, centaur_id) != 0)) 961 return; 962 963 /* 964 * Check if the CPU supports EST. 965 */ 966 if (!(cpu_feature2 & CPUID2_EST)) 967 return; 968 969 /* 970 * We add a child for each CPU since settings must be performed 971 * on each CPU in the SMP case. 972 */ 973 child = BUS_ADD_CHILD(parent, 10, "est", -1); 974 if (child == NULL) 975 device_printf(parent, "add est child failed\n"); 976} 977 978static int 979est_probe(device_t dev) 980{ 981 device_t perf_dev; 982 uint64_t msr; 983 int error, type; 984 985 if (resource_disabled("est", 0)) 986 return (ENXIO); 987 988 /* 989 * If the ACPI perf driver has attached and is not just offering 990 * info, let it manage things. 991 */ 992 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 993 if (perf_dev && device_is_attached(perf_dev)) { 994 error = CPUFREQ_DRV_TYPE(perf_dev, &type); 995 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 996 return (ENXIO); 997 } 998 999 /* Attempt to enable SpeedStep if not currently enabled. */ 1000 msr = rdmsr(MSR_MISC_ENABLE); 1001 if ((msr & MSR_SS_ENABLE) == 0) { 1002 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE); 1003 if (bootverbose) 1004 device_printf(dev, "enabling SpeedStep\n"); 1005 1006 /* Check if the enable failed. */ 1007 msr = rdmsr(MSR_MISC_ENABLE); 1008 if ((msr & MSR_SS_ENABLE) == 0) { 1009 device_printf(dev, "failed to enable SpeedStep\n"); 1010 return (ENXIO); 1011 } 1012 } 1013 1014 device_set_desc(dev, "Enhanced SpeedStep Frequency Control"); 1015 return (0); 1016} 1017 1018static int 1019est_attach(device_t dev) 1020{ 1021 struct est_softc *sc; 1022 1023 sc = device_get_softc(dev); 1024 sc->dev = dev; 1025 1026 /* Check CPU for supported settings. */ 1027 if (est_get_info(dev)) 1028 return (ENXIO); 1029 1030 cpufreq_register(dev); 1031 return (0); 1032} 1033 1034static int 1035est_detach(device_t dev) 1036{ 1037#if 0 1038 struct est_softc *sc; 1039 1040 sc = device_get_softc(dev); 1041 if (sc->acpi_settings || sc->msr_settings) 1042 free(sc->freq_list, M_DEVBUF); 1043#endif 1044 return (ENXIO); 1045} 1046 1047/* 1048 * Probe for supported CPU settings. First, check our static table of 1049 * settings. If no match, try using the ones offered by acpi_perf 1050 * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40 1051 * series) export both legacy SMM IO-based access and direct MSR access 1052 * but the direct access specifies invalid values for _PSS. 1053 */ 1054static int 1055est_get_info(device_t dev) 1056{ 1057 struct est_softc *sc; 1058 uint64_t msr; 1059 int error; 1060 1061 sc = device_get_softc(dev); 1062 msr = rdmsr(MSR_PERF_STATUS); 1063 error = est_table_info(dev, msr, &sc->freq_list); 1064 if (error) 1065 error = est_acpi_info(dev, &sc->freq_list); 1066 if (error) 1067 error = est_msr_info(dev, msr, &sc->freq_list); 1068 1069 if (error) { 1070 printf( 1071 "est: CPU supports Enhanced Speedstep, but is not recognized.\n" 1072 "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr); 1073 return (ENXIO); 1074 } 1075 1076 return (0); 1077} 1078 1079static int 1080est_acpi_info(device_t dev, freq_info **freqs) 1081{ 1082 struct est_softc *sc; 1083 struct cf_setting *sets; 1084 freq_info *table; 1085 device_t perf_dev; 1086 int count, error, i, j; 1087 uint16_t saved_id16; 1088 1089 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 1090 if (perf_dev == NULL || !device_is_attached(perf_dev)) 1091 return (ENXIO); 1092 1093 /* Fetch settings from acpi_perf. */ 1094 sc = device_get_softc(dev); 1095 table = NULL; 1096 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); 1097 if (sets == NULL) 1098 return (ENOMEM); 1099 count = MAX_SETTINGS; 1100 error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count); 1101 if (error) 1102 goto out; 1103 1104 /* Parse settings into our local table format. */ 1105 table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT); 1106 if (table == NULL) { 1107 error = ENOMEM; 1108 goto out; 1109 } 1110 est_get_id16(&saved_id16); 1111 for (i = 0, j = 0; i < count; i++) { 1112 /* 1113 * Confirm id16 value is correct. 1114 */ 1115 if (sets[i].freq > 0) { 1116 error = est_set_id16(dev, sets[i].spec[0], 1); 1117 if (error != 0) { 1118 if (bootverbose) 1119 device_printf(dev, "Invalid freq %u, " 1120 "ignored.\n", sets[i].freq); 1121 } else { 1122 table[j].freq = sets[i].freq; 1123 table[j].volts = sets[i].volts; 1124 table[j].id16 = sets[i].spec[0]; 1125 table[j].power = sets[i].power; 1126 ++j; 1127 } 1128 } 1129 } 1130 /* restore saved setting */ 1131 est_set_id16(dev, saved_id16, 0); 1132 1133 /* Mark end of table with a terminator. */ 1134 bzero(&table[j], sizeof(freq_info)); 1135 1136 sc->acpi_settings = TRUE; 1137 *freqs = table; 1138 error = 0; 1139 1140out: 1141 if (sets) 1142 free(sets, M_TEMP); 1143 if (error && table) 1144 free(table, M_DEVBUF); 1145 return (error); 1146} 1147 1148static int 1149est_table_info(device_t dev, uint64_t msr, freq_info **freqs) 1150{ 1151 cpu_info *p; 1152 uint32_t id; 1153 1154 /* Find a table which matches (vendor, id32). */ 1155 id = msr >> 32; 1156 for (p = ESTprocs; p->id32 != 0; p++) { 1157 if (strcmp(p->vendor, cpu_vendor) == 0 && p->id32 == id) 1158 break; 1159 } 1160 if (p->id32 == 0) 1161 return (EOPNOTSUPP); 1162 1163 /* Make sure the current setpoint is valid. */ 1164 if (est_get_current(p->freqtab) == NULL) { 1165 device_printf(dev, "current setting not found in table\n"); 1166 return (EOPNOTSUPP); 1167 } 1168 1169 *freqs = p->freqtab; 1170 return (0); 1171} 1172 1173static int 1174bus_speed_ok(int bus) 1175{ 1176 1177 switch (bus) { 1178 case 100: 1179 case 133: 1180 case 333: 1181 return (1); 1182 default: 1183 return (0); 1184 } 1185} 1186 1187/* 1188 * Flesh out a simple rate table containing the high and low frequencies 1189 * based on the current clock speed and the upper 32 bits of the MSR. 1190 */ 1191static int 1192est_msr_info(device_t dev, uint64_t msr, freq_info **freqs) 1193{ 1194 struct est_softc *sc; 1195 freq_info *fp; 1196 int bus, freq, volts; 1197 uint16_t id; 1198 1199 /* Figure out the bus clock. */ 1200 freq = tsc_freq / 1000000; 1201 id = msr >> 32; 1202 bus = freq / (id >> 8); 1203 device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus); 1204 if (!bus_speed_ok(bus)) { 1205 /* We may be running on the low frequency. */ 1206 id = msr >> 48; 1207 bus = freq / (id >> 8); 1208 device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus); 1209 if (!bus_speed_ok(bus)) 1210 return (EOPNOTSUPP); 1211 1212 /* Calculate high frequency. */ 1213 id = msr >> 32; 1214 freq = ((id >> 8) & 0xff) * bus; 1215 } 1216 1217 /* Fill out a new freq table containing just the high and low freqs. */ 1218 sc = device_get_softc(dev); 1219 fp = malloc(sizeof(freq_info) * 3, M_DEVBUF, M_WAITOK | M_ZERO); 1220 1221 /* First, the high frequency. */ 1222 volts = id & 0xff; 1223 if (volts != 0) { 1224 volts <<= 4; 1225 volts += 700; 1226 } 1227 fp[0].freq = freq; 1228 fp[0].volts = volts; 1229 fp[0].id16 = id; 1230 fp[0].power = CPUFREQ_VAL_UNKNOWN; 1231 device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq, 1232 volts); 1233 1234 /* Second, the low frequency. */ 1235 id = msr >> 48; 1236 freq = ((id >> 8) & 0xff) * bus; 1237 volts = id & 0xff; 1238 if (volts != 0) { 1239 volts <<= 4; 1240 volts += 700; 1241 } 1242 fp[1].freq = freq; 1243 fp[1].volts = volts; 1244 fp[1].id16 = id; 1245 fp[1].power = CPUFREQ_VAL_UNKNOWN; 1246 device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq, 1247 volts); 1248 1249 /* Table is already terminated due to M_ZERO. */ 1250 sc->msr_settings = TRUE; 1251 *freqs = fp; 1252 return (0); 1253} 1254 1255static void 1256est_get_id16(uint16_t *id16_p) 1257{ 1258 *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff; 1259} 1260 1261static int 1262est_set_id16(device_t dev, uint16_t id16, int need_check) 1263{ 1264 uint64_t msr; 1265 uint16_t new_id16; 1266 int ret = 0; 1267 1268 /* Read the current register, mask out the old, set the new id. */ 1269 msr = rdmsr(MSR_PERF_CTL); 1270 msr = (msr & ~0xffff) | id16; 1271 wrmsr(MSR_PERF_CTL, msr); 1272 1273 /* Wait a short while for the new setting. XXX Is this necessary? */ 1274 DELAY(EST_TRANS_LAT); 1275 1276 if (need_check) { 1277 est_get_id16(&new_id16); 1278 if (new_id16 != id16) { 1279 if (bootverbose) 1280 device_printf(dev, "Invalid id16 (set, cur) " 1281 "= (%u, %u)\n", id16, new_id16); 1282 ret = ENXIO; 1283 } 1284 } 1285 return (ret); 1286} 1287 1288static freq_info * 1289est_get_current(freq_info *freq_list) 1290{ 1291 freq_info *f; 1292 int i; 1293 uint16_t id16; 1294 1295 /* 1296 * Try a few times to get a valid value. Sometimes, if the CPU 1297 * is in the middle of an asynchronous transition (i.e., P4TCC), 1298 * we get a temporary invalid result. 1299 */ 1300 for (i = 0; i < 5; i++) { 1301 est_get_id16(&id16); 1302 for (f = freq_list; f->id16 != 0; f++) { 1303 if (f->id16 == id16) 1304 return (f); 1305 } 1306 DELAY(100); 1307 } 1308 return (NULL); 1309} 1310 1311static int 1312est_settings(device_t dev, struct cf_setting *sets, int *count) 1313{ 1314 struct est_softc *sc; 1315 freq_info *f; 1316 int i; 1317 1318 sc = device_get_softc(dev); 1319 if (*count < EST_MAX_SETTINGS) 1320 return (E2BIG); 1321 1322 i = 0; 1323 for (f = sc->freq_list; f->freq != 0; f++, i++) { 1324 sets[i].freq = f->freq; 1325 sets[i].volts = f->volts; 1326 sets[i].power = f->power; 1327 sets[i].lat = EST_TRANS_LAT; 1328 sets[i].dev = dev; 1329 } 1330 *count = i; 1331 1332 return (0); 1333} 1334 1335static int 1336est_set(device_t dev, const struct cf_setting *set) 1337{ 1338 struct est_softc *sc; 1339 freq_info *f; 1340 1341 /* Find the setting matching the requested one. */ 1342 sc = device_get_softc(dev); 1343 for (f = sc->freq_list; f->freq != 0; f++) { 1344 if (f->freq == set->freq) 1345 break; 1346 } 1347 if (f->freq == 0) 1348 return (EINVAL); 1349 1350 /* Read the current register, mask out the old, set the new id. */ 1351 est_set_id16(dev, f->id16, 0); 1352 1353 return (0); 1354} 1355 1356static int 1357est_get(device_t dev, struct cf_setting *set) 1358{ 1359 struct est_softc *sc; 1360 freq_info *f; 1361 1362 sc = device_get_softc(dev); 1363 f = est_get_current(sc->freq_list); 1364 if (f == NULL) 1365 return (ENXIO); 1366 1367 set->freq = f->freq; 1368 set->volts = f->volts; 1369 set->power = f->power; 1370 set->lat = EST_TRANS_LAT; 1371 set->dev = dev; 1372 return (0); 1373} 1374 1375static int 1376est_type(device_t dev, int *type) 1377{ 1378 1379 if (type == NULL) 1380 return (EINVAL); 1381 1382 *type = CPUFREQ_TYPE_ABSOLUTE; 1383 return (0); 1384} 1385