est.c revision 176649
1/*- 2 * Copyright (c) 2004 Colin Percival 3 * Copyright (c) 2005 Nate Lawson 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted providing that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/i386/cpufreq/est.c 176649 2008-02-28 19:10:42Z rpaulo $"); 30 31#include <sys/param.h> 32#include <sys/bus.h> 33#include <sys/cpu.h> 34#include <sys/kernel.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37#include <sys/smp.h> 38#include <sys/systm.h> 39 40#include "cpufreq_if.h" 41#include <machine/md_var.h> 42 43#include <contrib/dev/acpica/acpi.h> 44#include <dev/acpica/acpivar.h> 45#include "acpi_if.h" 46 47/* Status/control registers (from the IA-32 System Programming Guide). */ 48#define MSR_PERF_STATUS 0x198 49#define MSR_PERF_CTL 0x199 50 51/* Register and bit for enabling SpeedStep. */ 52#define MSR_MISC_ENABLE 0x1a0 53#define MSR_SS_ENABLE (1<<16) 54 55/* Frequency and MSR control values. */ 56typedef struct { 57 uint16_t freq; 58 uint16_t volts; 59 uint16_t id16; 60 int power; 61} freq_info; 62 63/* Identifying characteristics of a processor and supported frequencies. */ 64typedef struct { 65 const char *vendor; 66 uint32_t id32; 67 freq_info *freqtab; 68} cpu_info; 69 70struct est_softc { 71 device_t dev; 72 int acpi_settings; 73 freq_info *freq_list; 74}; 75 76/* Convert MHz and mV into IDs for passing to the MSR. */ 77#define ID16(MHz, mV, bus_clk) \ 78 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4)) 79#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \ 80 ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk))) 81 82/* Format for storing IDs in our table. */ 83#define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \ 84 { MHz, mV, ID16(MHz, mV, bus_clk), mW } 85#define FREQ_INFO(MHz, mV, bus_clk) \ 86 FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN) 87#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \ 88 { intel_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 89#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \ 90 { centaur_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 91 92const char intel_id[] = "GenuineIntel"; 93const char centaur_id[] = "CentaurHauls"; 94 95/* Default bus clock value for Centrino processors. */ 96#define INTEL_BUS_CLK 100 97 98/* XXX Update this if new CPUs have more settings. */ 99#define EST_MAX_SETTINGS 10 100CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS); 101 102/* Estimate in microseconds of latency for performing a transition. */ 103#define EST_TRANS_LAT 10 104 105/* 106 * Frequency (MHz) and voltage (mV) settings. Data from the 107 * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5. 108 * 109 * Dothan processors have multiple VID#s with different settings for 110 * each VID#. Since we can't uniquely identify this info 111 * without undisclosed methods from Intel, we can't support newer 112 * processors with this table method. If ACPI Px states are supported, 113 * we get info from them. 114 */ 115static freq_info PM17_130[] = { 116 /* 130nm 1.70GHz Pentium M */ 117 FREQ_INFO(1700, 1484, INTEL_BUS_CLK), 118 FREQ_INFO(1400, 1308, INTEL_BUS_CLK), 119 FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 120 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 121 FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 122 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 123 FREQ_INFO( 0, 0, 1), 124}; 125static freq_info PM16_130[] = { 126 /* 130nm 1.60GHz Pentium M */ 127 FREQ_INFO(1600, 1484, INTEL_BUS_CLK), 128 FREQ_INFO(1400, 1420, INTEL_BUS_CLK), 129 FREQ_INFO(1200, 1276, INTEL_BUS_CLK), 130 FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 131 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 132 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 133 FREQ_INFO( 0, 0, 1), 134}; 135static freq_info PM15_130[] = { 136 /* 130nm 1.50GHz Pentium M */ 137 FREQ_INFO(1500, 1484, INTEL_BUS_CLK), 138 FREQ_INFO(1400, 1452, INTEL_BUS_CLK), 139 FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 140 FREQ_INFO(1000, 1228, INTEL_BUS_CLK), 141 FREQ_INFO( 800, 1116, INTEL_BUS_CLK), 142 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 143 FREQ_INFO( 0, 0, 1), 144}; 145static freq_info PM14_130[] = { 146 /* 130nm 1.40GHz Pentium M */ 147 FREQ_INFO(1400, 1484, INTEL_BUS_CLK), 148 FREQ_INFO(1200, 1436, INTEL_BUS_CLK), 149 FREQ_INFO(1000, 1308, INTEL_BUS_CLK), 150 FREQ_INFO( 800, 1180, INTEL_BUS_CLK), 151 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 152 FREQ_INFO( 0, 0, 1), 153}; 154static freq_info PM13_130[] = { 155 /* 130nm 1.30GHz Pentium M */ 156 FREQ_INFO(1300, 1388, INTEL_BUS_CLK), 157 FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 158 FREQ_INFO(1000, 1292, INTEL_BUS_CLK), 159 FREQ_INFO( 800, 1260, INTEL_BUS_CLK), 160 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 161 FREQ_INFO( 0, 0, 1), 162}; 163static freq_info PM13_LV_130[] = { 164 /* 130nm 1.30GHz Low Voltage Pentium M */ 165 FREQ_INFO(1300, 1180, INTEL_BUS_CLK), 166 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 167 FREQ_INFO(1100, 1100, INTEL_BUS_CLK), 168 FREQ_INFO(1000, 1020, INTEL_BUS_CLK), 169 FREQ_INFO( 900, 1004, INTEL_BUS_CLK), 170 FREQ_INFO( 800, 988, INTEL_BUS_CLK), 171 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 172 FREQ_INFO( 0, 0, 1), 173}; 174static freq_info PM12_LV_130[] = { 175 /* 130 nm 1.20GHz Low Voltage Pentium M */ 176 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 177 FREQ_INFO(1100, 1164, INTEL_BUS_CLK), 178 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 179 FREQ_INFO( 900, 1020, INTEL_BUS_CLK), 180 FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 181 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 182 FREQ_INFO( 0, 0, 1), 183}; 184static freq_info PM11_LV_130[] = { 185 /* 130 nm 1.10GHz Low Voltage Pentium M */ 186 FREQ_INFO(1100, 1180, INTEL_BUS_CLK), 187 FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 188 FREQ_INFO( 900, 1100, INTEL_BUS_CLK), 189 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 190 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 191 FREQ_INFO( 0, 0, 1), 192}; 193static freq_info PM11_ULV_130[] = { 194 /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */ 195 FREQ_INFO(1100, 1004, INTEL_BUS_CLK), 196 FREQ_INFO(1000, 988, INTEL_BUS_CLK), 197 FREQ_INFO( 900, 972, INTEL_BUS_CLK), 198 FREQ_INFO( 800, 956, INTEL_BUS_CLK), 199 FREQ_INFO( 600, 844, INTEL_BUS_CLK), 200 FREQ_INFO( 0, 0, 1), 201}; 202static freq_info PM10_ULV_130[] = { 203 /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */ 204 FREQ_INFO(1000, 1004, INTEL_BUS_CLK), 205 FREQ_INFO( 900, 988, INTEL_BUS_CLK), 206 FREQ_INFO( 800, 972, INTEL_BUS_CLK), 207 FREQ_INFO( 600, 844, INTEL_BUS_CLK), 208 FREQ_INFO( 0, 0, 1), 209}; 210 211/* 212 * Data from "Intel Pentium M Processor on 90nm Process with 213 * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5. 214 */ 215static freq_info PM_765A_90[] = { 216 /* 90 nm 2.10GHz Pentium M, VID #A */ 217 FREQ_INFO(2100, 1340, INTEL_BUS_CLK), 218 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 219 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 220 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 221 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 222 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 223 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 224 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 225 FREQ_INFO( 0, 0, 1), 226}; 227static freq_info PM_765B_90[] = { 228 /* 90 nm 2.10GHz Pentium M, VID #B */ 229 FREQ_INFO(2100, 1324, INTEL_BUS_CLK), 230 FREQ_INFO(1800, 1260, INTEL_BUS_CLK), 231 FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 232 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 233 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 234 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 235 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 236 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 237 FREQ_INFO( 0, 0, 1), 238}; 239static freq_info PM_765C_90[] = { 240 /* 90 nm 2.10GHz Pentium M, VID #C */ 241 FREQ_INFO(2100, 1308, INTEL_BUS_CLK), 242 FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 243 FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 244 FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 245 FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 246 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 247 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 248 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 249 FREQ_INFO( 0, 0, 1), 250}; 251static freq_info PM_765E_90[] = { 252 /* 90 nm 2.10GHz Pentium M, VID #E */ 253 FREQ_INFO(2100, 1356, INTEL_BUS_CLK), 254 FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 255 FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 256 FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 257 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 258 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 259 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 260 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 261 FREQ_INFO( 0, 0, 1), 262}; 263static freq_info PM_755A_90[] = { 264 /* 90 nm 2.00GHz Pentium M, VID #A */ 265 FREQ_INFO(2000, 1340, INTEL_BUS_CLK), 266 FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 267 FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 268 FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 269 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 270 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 271 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 272 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 273 FREQ_INFO( 0, 0, 1), 274}; 275static freq_info PM_755B_90[] = { 276 /* 90 nm 2.00GHz Pentium M, VID #B */ 277 FREQ_INFO(2000, 1324, INTEL_BUS_CLK), 278 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 279 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 280 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 281 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 282 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 283 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 284 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 285 FREQ_INFO( 0, 0, 1), 286}; 287static freq_info PM_755C_90[] = { 288 /* 90 nm 2.00GHz Pentium M, VID #C */ 289 FREQ_INFO(2000, 1308, INTEL_BUS_CLK), 290 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 291 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 292 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 293 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 294 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 295 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 296 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 297 FREQ_INFO( 0, 0, 1), 298}; 299static freq_info PM_755D_90[] = { 300 /* 90 nm 2.00GHz Pentium M, VID #D */ 301 FREQ_INFO(2000, 1276, INTEL_BUS_CLK), 302 FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 303 FREQ_INFO(1600, 1196, INTEL_BUS_CLK), 304 FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 305 FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 306 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 307 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 308 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 309 FREQ_INFO( 0, 0, 1), 310}; 311static freq_info PM_745A_90[] = { 312 /* 90 nm 1.80GHz Pentium M, VID #A */ 313 FREQ_INFO(1800, 1340, INTEL_BUS_CLK), 314 FREQ_INFO(1600, 1292, INTEL_BUS_CLK), 315 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 316 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 317 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 318 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 319 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 320 FREQ_INFO( 0, 0, 1), 321}; 322static freq_info PM_745B_90[] = { 323 /* 90 nm 1.80GHz Pentium M, VID #B */ 324 FREQ_INFO(1800, 1324, INTEL_BUS_CLK), 325 FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 326 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 327 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 328 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 329 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 330 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 331 FREQ_INFO( 0, 0, 1), 332}; 333static freq_info PM_745C_90[] = { 334 /* 90 nm 1.80GHz Pentium M, VID #C */ 335 FREQ_INFO(1800, 1308, INTEL_BUS_CLK), 336 FREQ_INFO(1600, 1260, INTEL_BUS_CLK), 337 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 338 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 339 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 340 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 341 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 342 FREQ_INFO( 0, 0, 1), 343}; 344static freq_info PM_745D_90[] = { 345 /* 90 nm 1.80GHz Pentium M, VID #D */ 346 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 347 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 348 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 349 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 350 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 351 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 352 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 353 FREQ_INFO( 0, 0, 1), 354}; 355static freq_info PM_735A_90[] = { 356 /* 90 nm 1.70GHz Pentium M, VID #A */ 357 FREQ_INFO(1700, 1340, INTEL_BUS_CLK), 358 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 359 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 360 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 361 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 362 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 363 FREQ_INFO( 0, 0, 1), 364}; 365static freq_info PM_735B_90[] = { 366 /* 90 nm 1.70GHz Pentium M, VID #B */ 367 FREQ_INFO(1700, 1324, INTEL_BUS_CLK), 368 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 369 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 370 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 371 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 372 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 373 FREQ_INFO( 0, 0, 1), 374}; 375static freq_info PM_735C_90[] = { 376 /* 90 nm 1.70GHz Pentium M, VID #C */ 377 FREQ_INFO(1700, 1308, INTEL_BUS_CLK), 378 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 379 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 380 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 381 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 382 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 383 FREQ_INFO( 0, 0, 1), 384}; 385static freq_info PM_735D_90[] = { 386 /* 90 nm 1.70GHz Pentium M, VID #D */ 387 FREQ_INFO(1700, 1276, INTEL_BUS_CLK), 388 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 389 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 390 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 391 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 392 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 393 FREQ_INFO( 0, 0, 1), 394}; 395static freq_info PM_725A_90[] = { 396 /* 90 nm 1.60GHz Pentium M, VID #A */ 397 FREQ_INFO(1600, 1340, INTEL_BUS_CLK), 398 FREQ_INFO(1400, 1276, INTEL_BUS_CLK), 399 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 400 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 401 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 402 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 403 FREQ_INFO( 0, 0, 1), 404}; 405static freq_info PM_725B_90[] = { 406 /* 90 nm 1.60GHz Pentium M, VID #B */ 407 FREQ_INFO(1600, 1324, INTEL_BUS_CLK), 408 FREQ_INFO(1400, 1260, INTEL_BUS_CLK), 409 FREQ_INFO(1200, 1196, INTEL_BUS_CLK), 410 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 411 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 412 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 413 FREQ_INFO( 0, 0, 1), 414}; 415static freq_info PM_725C_90[] = { 416 /* 90 nm 1.60GHz Pentium M, VID #C */ 417 FREQ_INFO(1600, 1308, INTEL_BUS_CLK), 418 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 419 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 420 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 421 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 422 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 423 FREQ_INFO( 0, 0, 1), 424}; 425static freq_info PM_725D_90[] = { 426 /* 90 nm 1.60GHz Pentium M, VID #D */ 427 FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 428 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 429 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 430 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 431 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 432 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 433 FREQ_INFO( 0, 0, 1), 434}; 435static freq_info PM_715A_90[] = { 436 /* 90 nm 1.50GHz Pentium M, VID #A */ 437 FREQ_INFO(1500, 1340, INTEL_BUS_CLK), 438 FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 439 FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 440 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 441 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 442 FREQ_INFO( 0, 0, 1), 443}; 444static freq_info PM_715B_90[] = { 445 /* 90 nm 1.50GHz Pentium M, VID #B */ 446 FREQ_INFO(1500, 1324, INTEL_BUS_CLK), 447 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 448 FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 449 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 450 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 451 FREQ_INFO( 0, 0, 1), 452}; 453static freq_info PM_715C_90[] = { 454 /* 90 nm 1.50GHz Pentium M, VID #C */ 455 FREQ_INFO(1500, 1308, INTEL_BUS_CLK), 456 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 457 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 458 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 459 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 460 FREQ_INFO( 0, 0, 1), 461}; 462static freq_info PM_715D_90[] = { 463 /* 90 nm 1.50GHz Pentium M, VID #D */ 464 FREQ_INFO(1500, 1276, INTEL_BUS_CLK), 465 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 466 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 467 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 468 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 469 FREQ_INFO( 0, 0, 1), 470}; 471static freq_info PM_778_90[] = { 472 /* 90 nm 1.60GHz Low Voltage Pentium M */ 473 FREQ_INFO(1600, 1116, INTEL_BUS_CLK), 474 FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 475 FREQ_INFO(1400, 1100, INTEL_BUS_CLK), 476 FREQ_INFO(1300, 1084, INTEL_BUS_CLK), 477 FREQ_INFO(1200, 1068, INTEL_BUS_CLK), 478 FREQ_INFO(1100, 1052, INTEL_BUS_CLK), 479 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 480 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 481 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 482 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 483 FREQ_INFO( 0, 0, 1), 484}; 485static freq_info PM_758_90[] = { 486 /* 90 nm 1.50GHz Low Voltage Pentium M */ 487 FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 488 FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 489 FREQ_INFO(1300, 1100, INTEL_BUS_CLK), 490 FREQ_INFO(1200, 1084, INTEL_BUS_CLK), 491 FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 492 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 493 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 494 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 495 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 496 FREQ_INFO( 0, 0, 1), 497}; 498static freq_info PM_738_90[] = { 499 /* 90 nm 1.40GHz Low Voltage Pentium M */ 500 FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 501 FREQ_INFO(1300, 1116, INTEL_BUS_CLK), 502 FREQ_INFO(1200, 1100, INTEL_BUS_CLK), 503 FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 504 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 505 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 506 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 507 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 508 FREQ_INFO( 0, 0, 1), 509}; 510static freq_info PM_773G_90[] = { 511 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */ 512 FREQ_INFO(1300, 956, INTEL_BUS_CLK), 513 FREQ_INFO(1200, 940, INTEL_BUS_CLK), 514 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 515 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 516 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 517 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 518 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 519}; 520static freq_info PM_773H_90[] = { 521 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */ 522 FREQ_INFO(1300, 940, INTEL_BUS_CLK), 523 FREQ_INFO(1200, 924, INTEL_BUS_CLK), 524 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 525 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 526 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 527 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 528 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 529}; 530static freq_info PM_773I_90[] = { 531 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */ 532 FREQ_INFO(1300, 924, INTEL_BUS_CLK), 533 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 534 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 535 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 536 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 537 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 538 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 539}; 540static freq_info PM_773J_90[] = { 541 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */ 542 FREQ_INFO(1300, 908, INTEL_BUS_CLK), 543 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 544 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 545 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 546 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 547 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 548 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 549}; 550static freq_info PM_773K_90[] = { 551 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */ 552 FREQ_INFO(1300, 892, INTEL_BUS_CLK), 553 FREQ_INFO(1200, 892, INTEL_BUS_CLK), 554 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 555 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 556 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 557 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 558 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 559}; 560static freq_info PM_773L_90[] = { 561 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */ 562 FREQ_INFO(1300, 876, INTEL_BUS_CLK), 563 FREQ_INFO(1200, 876, INTEL_BUS_CLK), 564 FREQ_INFO(1100, 860, INTEL_BUS_CLK), 565 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 566 FREQ_INFO( 900, 844, INTEL_BUS_CLK), 567 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 568 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 569}; 570static freq_info PM_753G_90[] = { 571 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */ 572 FREQ_INFO(1200, 956, INTEL_BUS_CLK), 573 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 574 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 575 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 576 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 577 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 578}; 579static freq_info PM_753H_90[] = { 580 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */ 581 FREQ_INFO(1200, 940, INTEL_BUS_CLK), 582 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 583 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 584 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 585 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 586 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 587}; 588static freq_info PM_753I_90[] = { 589 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */ 590 FREQ_INFO(1200, 924, INTEL_BUS_CLK), 591 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 592 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 593 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 594 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 595 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 596}; 597static freq_info PM_753J_90[] = { 598 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */ 599 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 600 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 601 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 602 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 603 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 604 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 605}; 606static freq_info PM_753K_90[] = { 607 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */ 608 FREQ_INFO(1200, 892, INTEL_BUS_CLK), 609 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 610 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 611 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 612 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 613 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 614}; 615static freq_info PM_753L_90[] = { 616 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */ 617 FREQ_INFO(1200, 876, INTEL_BUS_CLK), 618 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 619 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 620 FREQ_INFO( 900, 844, INTEL_BUS_CLK), 621 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 622 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 623}; 624 625static freq_info PM_733JG_90[] = { 626 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */ 627 FREQ_INFO(1100, 956, INTEL_BUS_CLK), 628 FREQ_INFO(1000, 940, INTEL_BUS_CLK), 629 FREQ_INFO( 900, 908, INTEL_BUS_CLK), 630 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 631 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 632}; 633static freq_info PM_733JH_90[] = { 634 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */ 635 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 636 FREQ_INFO(1000, 924, INTEL_BUS_CLK), 637 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 638 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 639 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 640}; 641static freq_info PM_733JI_90[] = { 642 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */ 643 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 644 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 645 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 646 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 647 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 648}; 649static freq_info PM_733JJ_90[] = { 650 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */ 651 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 652 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 653 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 654 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 655 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 656}; 657static freq_info PM_733JK_90[] = { 658 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */ 659 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 660 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 661 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 662 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 663 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 664}; 665static freq_info PM_733JL_90[] = { 666 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */ 667 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 668 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 669 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 670 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 671 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 672}; 673static freq_info PM_733_90[] = { 674 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */ 675 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 676 FREQ_INFO(1000, 924, INTEL_BUS_CLK), 677 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 678 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 679 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 680 FREQ_INFO( 0, 0, 1), 681}; 682static freq_info PM_723_90[] = { 683 /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */ 684 FREQ_INFO(1000, 940, INTEL_BUS_CLK), 685 FREQ_INFO( 900, 908, INTEL_BUS_CLK), 686 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 687 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 688 FREQ_INFO( 0, 0, 1), 689}; 690 691/* 692 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants. 693 * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet. 694 */ 695static freq_info C7M_795[] = { 696 /* 2.00GHz Centaur C7-M 533 Mhz FSB */ 697 FREQ_INFO_PWR(2000, 1148, 133, 20000), 698 FREQ_INFO_PWR(1867, 1132, 133, 18000), 699 FREQ_INFO_PWR(1600, 1100, 133, 15000), 700 FREQ_INFO_PWR(1467, 1052, 133, 13000), 701 FREQ_INFO_PWR(1200, 1004, 133, 10000), 702 FREQ_INFO_PWR( 800, 844, 133, 7000), 703 FREQ_INFO_PWR( 667, 844, 133, 6000), 704 FREQ_INFO_PWR( 533, 844, 133, 5000), 705 FREQ_INFO(0, 0, 1), 706}; 707static freq_info C7M_785[] = { 708 /* 1.80GHz Centaur C7-M 533 Mhz FSB */ 709 FREQ_INFO_PWR(1867, 1148, 133, 18000), 710 FREQ_INFO_PWR(1600, 1100, 133, 15000), 711 FREQ_INFO_PWR(1467, 1052, 133, 13000), 712 FREQ_INFO_PWR(1200, 1004, 133, 10000), 713 FREQ_INFO_PWR( 800, 844, 133, 7000), 714 FREQ_INFO_PWR( 667, 844, 133, 6000), 715 FREQ_INFO_PWR( 533, 844, 133, 5000), 716 FREQ_INFO(0, 0, 1), 717}; 718static freq_info C7M_765[] = { 719 /* 1.60GHz Centaur C7-M 533 Mhz FSB */ 720 FREQ_INFO_PWR(1600, 1084, 133, 15000), 721 FREQ_INFO_PWR(1467, 1052, 133, 13000), 722 FREQ_INFO_PWR(1200, 1004, 133, 10000), 723 FREQ_INFO_PWR( 800, 844, 133, 7000), 724 FREQ_INFO_PWR( 667, 844, 133, 6000), 725 FREQ_INFO_PWR( 533, 844, 133, 5000), 726 FREQ_INFO(0, 0, 1), 727}; 728 729static freq_info C7M_794[] = { 730 /* 2.00GHz Centaur C7-M 400 Mhz FSB */ 731 FREQ_INFO_PWR(2000, 1148, 100, 20000), 732 FREQ_INFO_PWR(1800, 1132, 100, 18000), 733 FREQ_INFO_PWR(1600, 1100, 100, 15000), 734 FREQ_INFO_PWR(1400, 1052, 100, 13000), 735 FREQ_INFO_PWR(1000, 1004, 100, 10000), 736 FREQ_INFO_PWR( 800, 844, 100, 7000), 737 FREQ_INFO_PWR( 600, 844, 100, 6000), 738 FREQ_INFO_PWR( 400, 844, 100, 5000), 739 FREQ_INFO(0, 0, 1), 740}; 741static freq_info C7M_784[] = { 742 /* 1.80GHz Centaur C7-M 400 Mhz FSB */ 743 FREQ_INFO_PWR(1800, 1148, 100, 18000), 744 FREQ_INFO_PWR(1600, 1100, 100, 15000), 745 FREQ_INFO_PWR(1400, 1052, 100, 13000), 746 FREQ_INFO_PWR(1000, 1004, 100, 10000), 747 FREQ_INFO_PWR( 800, 844, 100, 7000), 748 FREQ_INFO_PWR( 600, 844, 100, 6000), 749 FREQ_INFO_PWR( 400, 844, 100, 5000), 750 FREQ_INFO(0, 0, 1), 751}; 752static freq_info C7M_764[] = { 753 /* 1.60GHz Centaur C7-M 400 Mhz FSB */ 754 FREQ_INFO_PWR(1600, 1084, 100, 15000), 755 FREQ_INFO_PWR(1400, 1052, 100, 13000), 756 FREQ_INFO_PWR(1000, 1004, 100, 10000), 757 FREQ_INFO_PWR( 800, 844, 100, 7000), 758 FREQ_INFO_PWR( 600, 844, 100, 6000), 759 FREQ_INFO_PWR( 400, 844, 100, 5000), 760 FREQ_INFO(0, 0, 1), 761}; 762static freq_info C7M_754[] = { 763 /* 1.50GHz Centaur C7-M 400 Mhz FSB */ 764 FREQ_INFO_PWR(1500, 1004, 100, 12000), 765 FREQ_INFO_PWR(1400, 988, 100, 11000), 766 FREQ_INFO_PWR(1000, 940, 100, 9000), 767 FREQ_INFO_PWR( 800, 844, 100, 7000), 768 FREQ_INFO_PWR( 600, 844, 100, 6000), 769 FREQ_INFO_PWR( 400, 844, 100, 5000), 770 FREQ_INFO(0, 0, 1), 771}; 772static freq_info C7M_771[] = { 773 /* 1.20GHz Centaur C7-M 400 Mhz FSB */ 774 FREQ_INFO_PWR(1200, 860, 100, 7000), 775 FREQ_INFO_PWR(1000, 860, 100, 6000), 776 FREQ_INFO_PWR( 800, 844, 100, 5500), 777 FREQ_INFO_PWR( 600, 844, 100, 5000), 778 FREQ_INFO_PWR( 400, 844, 100, 4000), 779 FREQ_INFO(0, 0, 1), 780}; 781 782static freq_info C7M_775_ULV[] = { 783 /* 1.50GHz Centaur C7-M ULV */ 784 FREQ_INFO_PWR(1500, 956, 100, 7500), 785 FREQ_INFO_PWR(1400, 940, 100, 6000), 786 FREQ_INFO_PWR(1000, 860, 100, 5000), 787 FREQ_INFO_PWR( 800, 828, 100, 2800), 788 FREQ_INFO_PWR( 600, 796, 100, 2500), 789 FREQ_INFO_PWR( 400, 796, 100, 2000), 790 FREQ_INFO(0, 0, 1), 791}; 792static freq_info C7M_772_ULV[] = { 793 /* 1.20GHz Centaur C7-M ULV */ 794 FREQ_INFO_PWR(1200, 844, 100, 5000), 795 FREQ_INFO_PWR(1000, 844, 100, 4000), 796 FREQ_INFO_PWR( 800, 828, 100, 2800), 797 FREQ_INFO_PWR( 600, 796, 100, 2500), 798 FREQ_INFO_PWR( 400, 796, 100, 2000), 799 FREQ_INFO(0, 0, 1), 800}; 801static freq_info C7M_779_ULV[] = { 802 /* 1.00GHz Centaur C7-M ULV */ 803 FREQ_INFO_PWR(1000, 796, 100, 3500), 804 FREQ_INFO_PWR( 800, 796, 100, 2800), 805 FREQ_INFO_PWR( 600, 796, 100, 2500), 806 FREQ_INFO_PWR( 400, 796, 100, 2000), 807 FREQ_INFO(0, 0, 1), 808}; 809static freq_info C7M_770_ULV[] = { 810 /* 1.00GHz Centaur C7-M ULV */ 811 FREQ_INFO_PWR(1000, 844, 100, 5000), 812 FREQ_INFO_PWR( 800, 796, 100, 2800), 813 FREQ_INFO_PWR( 600, 796, 100, 2500), 814 FREQ_INFO_PWR( 400, 796, 100, 2000), 815 FREQ_INFO(0, 0, 1), 816}; 817 818static cpu_info ESTprocs[] = { 819 INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK), 820 INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK), 821 INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK), 822 INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK), 823 INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK), 824 INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK), 825 INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK), 826 INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK), 827 INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK), 828 INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK), 829 INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK), 830 INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK), 831 INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK), 832 INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK), 833 INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK), 834 INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK), 835 INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK), 836 INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK), 837 INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK), 838 INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK), 839 INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK), 840 INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK), 841 INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK), 842 INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK), 843 INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK), 844 INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK), 845 INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK), 846 INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK), 847 INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK), 848 INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK), 849 INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK), 850 INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK), 851 INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK), 852 INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK), 853 INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK), 854 INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK), 855 INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK), 856 INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK), 857 INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK), 858 INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK), 859 INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK), 860 INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK), 861 INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK), 862 INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK), 863 INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK), 864 INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK), 865 INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK), 866 INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK), 867 INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK), 868 INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK), 869 INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 870 INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK), 871 INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK), 872 INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK), 873 INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK), 874 INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 875 INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK), 876 877 CENTAUR(C7M_795, 2000, 1148, 533, 844, 133), 878 CENTAUR(C7M_794, 2000, 1148, 400, 844, 100), 879 CENTAUR(C7M_785, 1867, 1148, 533, 844, 133), 880 CENTAUR(C7M_784, 1800, 1148, 400, 844, 100), 881 CENTAUR(C7M_765, 1600, 1084, 533, 844, 133), 882 CENTAUR(C7M_764, 1600, 1084, 400, 844, 100), 883 CENTAUR(C7M_754, 1500, 1004, 400, 844, 100), 884 CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100), 885 CENTAUR(C7M_771, 1200, 860, 400, 844, 100), 886 CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100), 887 CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100), 888 CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100), 889 { NULL, 0, NULL }, 890}; 891 892static void est_identify(driver_t *driver, device_t parent); 893static int est_features(driver_t *driver, u_int *features); 894static int est_probe(device_t parent); 895static int est_attach(device_t parent); 896static int est_detach(device_t parent); 897static int est_get_info(device_t dev); 898static int est_acpi_info(device_t dev, freq_info **freqs); 899static int est_table_info(device_t dev, uint64_t msr, freq_info **freqs); 900static freq_info *est_get_current(freq_info *freq_list); 901static int est_settings(device_t dev, struct cf_setting *sets, int *count); 902static int est_set(device_t dev, const struct cf_setting *set); 903static int est_get(device_t dev, struct cf_setting *set); 904static int est_type(device_t dev, int *type); 905static int est_set_id16(device_t dev, uint16_t id16, int need_check); 906static void est_get_id16(uint16_t *id16_p); 907 908static device_method_t est_methods[] = { 909 /* Device interface */ 910 DEVMETHOD(device_identify, est_identify), 911 DEVMETHOD(device_probe, est_probe), 912 DEVMETHOD(device_attach, est_attach), 913 DEVMETHOD(device_detach, est_detach), 914 915 /* cpufreq interface */ 916 DEVMETHOD(cpufreq_drv_set, est_set), 917 DEVMETHOD(cpufreq_drv_get, est_get), 918 DEVMETHOD(cpufreq_drv_type, est_type), 919 DEVMETHOD(cpufreq_drv_settings, est_settings), 920 921 /* ACPI interface */ 922 DEVMETHOD(acpi_get_features, est_features), 923 924 {0, 0} 925}; 926 927static driver_t est_driver = { 928 "est", 929 est_methods, 930 sizeof(struct est_softc), 931}; 932 933static devclass_t est_devclass; 934DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0); 935 936static int 937est_features(driver_t *driver, u_int *features) 938{ 939 940 /* Notify the ACPI CPU that we support direct access to MSRs */ 941 *features = ACPI_CAP_PERF_MSRS; 942 return (0); 943} 944 945static void 946est_identify(driver_t *driver, device_t parent) 947{ 948 device_t child; 949 u_int p[4]; 950 951 /* Make sure we're not being doubly invoked. */ 952 if (device_find_child(parent, "est", -1) != NULL) 953 return; 954 955 /* Check that CPUID is supported and the vendor is Intel.*/ 956 if (cpu_high == 0 || (strcmp(cpu_vendor, intel_id) != 0 && 957 strcmp(cpu_vendor, centaur_id) != 0)) 958 return; 959 960 /* 961 * Read capability bits and check if the CPU supports EST. 962 * This is indicated by bit 7 of ECX. 963 */ 964 do_cpuid(1, p); 965 if ((p[2] & 0x80) == 0) 966 return; 967 968 /* 969 * We add a child for each CPU since settings must be performed 970 * on each CPU in the SMP case. 971 */ 972 child = BUS_ADD_CHILD(parent, 0, "est", -1); 973 if (child == NULL) 974 device_printf(parent, "add est child failed\n"); 975} 976 977static int 978est_probe(device_t dev) 979{ 980 device_t perf_dev; 981 uint64_t msr; 982 int error, type; 983 984 if (resource_disabled("est", 0)) 985 return (ENXIO); 986 987 /* 988 * If the ACPI perf driver has attached and is not just offering 989 * info, let it manage things. 990 */ 991 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 992 if (perf_dev && device_is_attached(perf_dev)) { 993 error = CPUFREQ_DRV_TYPE(perf_dev, &type); 994 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 995 return (ENXIO); 996 } 997 998 /* Attempt to enable SpeedStep if not currently enabled. */ 999 msr = rdmsr(MSR_MISC_ENABLE); 1000 if ((msr & MSR_SS_ENABLE) == 0) { 1001 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE); 1002 if (bootverbose) 1003 device_printf(dev, "enabling SpeedStep\n"); 1004 1005 /* Check if the enable failed. */ 1006 msr = rdmsr(MSR_MISC_ENABLE); 1007 if ((msr & MSR_SS_ENABLE) == 0) { 1008 device_printf(dev, "failed to enable SpeedStep\n"); 1009 return (ENXIO); 1010 } 1011 } 1012 1013 device_set_desc(dev, "Enhanced SpeedStep Frequency Control"); 1014 return (0); 1015} 1016 1017static int 1018est_attach(device_t dev) 1019{ 1020 struct est_softc *sc; 1021 1022 sc = device_get_softc(dev); 1023 sc->dev = dev; 1024 1025 /* Check CPU for supported settings. */ 1026 if (est_get_info(dev)) 1027 return (ENXIO); 1028 1029 cpufreq_register(dev); 1030 return (0); 1031} 1032 1033static int 1034est_detach(device_t dev) 1035{ 1036 struct est_softc *sc; 1037 1038 sc = device_get_softc(dev); 1039 if (sc->acpi_settings) 1040 free(sc->freq_list, M_DEVBUF); 1041 return (ENXIO); 1042} 1043 1044/* 1045 * Probe for supported CPU settings. First, check our static table of 1046 * settings. If no match, try using the ones offered by acpi_perf 1047 * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40 1048 * series) export both legacy SMM IO-based access and direct MSR access 1049 * but the direct access specifies invalid values for _PSS. 1050 */ 1051static int 1052est_get_info(device_t dev) 1053{ 1054 struct est_softc *sc; 1055 uint64_t msr; 1056 int error; 1057 1058 sc = device_get_softc(dev); 1059 msr = rdmsr(MSR_PERF_STATUS); 1060 error = est_table_info(dev, msr, &sc->freq_list); 1061 if (error) 1062 error = est_acpi_info(dev, &sc->freq_list); 1063 1064 if (error) { 1065 printf( 1066 "est: CPU supports Enhanced Speedstep, but is not recognized.\n" 1067 "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr); 1068 return (ENXIO); 1069 } 1070 1071 return (0); 1072} 1073 1074static int 1075est_acpi_info(device_t dev, freq_info **freqs) 1076{ 1077 struct est_softc *sc; 1078 struct cf_setting *sets; 1079 freq_info *table; 1080 device_t perf_dev; 1081 int count, error, i, j; 1082 uint16_t saved_id16; 1083 1084 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 1085 if (perf_dev == NULL || !device_is_attached(perf_dev)) 1086 return (ENXIO); 1087 1088 /* Fetch settings from acpi_perf. */ 1089 sc = device_get_softc(dev); 1090 table = NULL; 1091 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); 1092 if (sets == NULL) 1093 return (ENOMEM); 1094 error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count); 1095 if (error) 1096 goto out; 1097 1098 /* Parse settings into our local table format. */ 1099 table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT); 1100 if (table == NULL) { 1101 error = ENOMEM; 1102 goto out; 1103 } 1104 for (i = 0, j = 0; i < count; i++) { 1105 /* 1106 * Confirm id16 value is correct. 1107 */ 1108 if (sets[i].freq > 0) { 1109 est_get_id16(&saved_id16); 1110 error = est_set_id16(dev, sets[i].spec[0], 1); 1111 if (error != 0) { 1112 if (bootverbose) 1113 device_printf(dev, "Invalid freq %u, " 1114 "ignored.\n", sets[i].freq); 1115 } else { 1116 table[j].freq = sets[i].freq; 1117 table[j].volts = sets[i].volts; 1118 table[j].id16 = sets[i].spec[0]; 1119 table[j].power = sets[i].power; 1120 ++j; 1121 } 1122 /* restore saved setting */ 1123 est_set_id16(dev, sets[i].spec[0], 0); 1124 } 1125 } 1126 1127 /* Mark end of table with a terminator. */ 1128 bzero(&table[j], sizeof(freq_info)); 1129 1130 sc->acpi_settings = TRUE; 1131 *freqs = table; 1132 error = 0; 1133 1134out: 1135 if (sets) 1136 free(sets, M_TEMP); 1137 if (error && table) 1138 free(table, M_DEVBUF); 1139 return (error); 1140} 1141 1142static int 1143est_table_info(device_t dev, uint64_t msr, freq_info **freqs) 1144{ 1145 cpu_info *p; 1146 uint32_t id; 1147 1148 /* Find a table which matches (vendor, id32). */ 1149 id = msr >> 32; 1150 for (p = ESTprocs; p->id32 != 0; p++) { 1151 if (strcmp(p->vendor, cpu_vendor) == 0 && p->id32 == id) 1152 break; 1153 } 1154 if (p->id32 == 0) 1155 return (EOPNOTSUPP); 1156 1157 /* Make sure the current setpoint is valid. */ 1158 if (est_get_current(p->freqtab) == NULL) { 1159 device_printf(dev, "current setting not found in table\n"); 1160 return (EOPNOTSUPP); 1161 } 1162 1163 *freqs = p->freqtab; 1164 return (0); 1165} 1166 1167static void 1168est_get_id16(uint16_t *id16_p) 1169{ 1170 *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff; 1171} 1172 1173static int 1174est_set_id16(device_t dev, uint16_t id16, int need_check) 1175{ 1176 uint64_t msr; 1177 uint16_t new_id16; 1178 int ret = 0; 1179 1180 /* Read the current register, mask out the old, set the new id. */ 1181 msr = rdmsr(MSR_PERF_CTL); 1182 msr = (msr & ~0xffff) | id16; 1183 wrmsr(MSR_PERF_CTL, msr); 1184 1185 /* Wait a short while for the new setting. XXX Is this necessary? */ 1186 DELAY(EST_TRANS_LAT); 1187 1188 if (need_check) { 1189 est_get_id16(&new_id16); 1190 if (new_id16 != id16) { 1191 if (bootverbose) 1192 device_printf(dev, "Invalid id16 (set, cur) " 1193 "= (%u, %u)\n", id16, new_id16); 1194 ret = ENXIO; 1195 } 1196 } 1197 return (ret); 1198} 1199 1200static freq_info * 1201est_get_current(freq_info *freq_list) 1202{ 1203 freq_info *f; 1204 int i; 1205 uint16_t id16; 1206 1207 /* 1208 * Try a few times to get a valid value. Sometimes, if the CPU 1209 * is in the middle of an asynchronous transition (i.e., P4TCC), 1210 * we get a temporary invalid result. 1211 */ 1212 for (i = 0; i < 5; i++) { 1213 est_get_id16(&id16); 1214 for (f = freq_list; f->id16 != 0; f++) { 1215 if (f->id16 == id16) 1216 return (f); 1217 } 1218 DELAY(100); 1219 } 1220 return (NULL); 1221} 1222 1223static int 1224est_settings(device_t dev, struct cf_setting *sets, int *count) 1225{ 1226 struct est_softc *sc; 1227 freq_info *f; 1228 int i; 1229 1230 sc = device_get_softc(dev); 1231 if (*count < EST_MAX_SETTINGS) 1232 return (E2BIG); 1233 1234 i = 0; 1235 for (f = sc->freq_list; f->freq != 0; f++, i++) { 1236 sets[i].freq = f->freq; 1237 sets[i].volts = f->volts; 1238 sets[i].power = f->power; 1239 sets[i].lat = EST_TRANS_LAT; 1240 sets[i].dev = dev; 1241 } 1242 *count = i; 1243 1244 return (0); 1245} 1246 1247static int 1248est_set(device_t dev, const struct cf_setting *set) 1249{ 1250 struct est_softc *sc; 1251 freq_info *f; 1252 1253 /* Find the setting matching the requested one. */ 1254 sc = device_get_softc(dev); 1255 for (f = sc->freq_list; f->freq != 0; f++) { 1256 if (f->freq == set->freq) 1257 break; 1258 } 1259 if (f->freq == 0) 1260 return (EINVAL); 1261 1262 /* Read the current register, mask out the old, set the new id. */ 1263 est_set_id16(dev, f->id16, 0); 1264 1265 return (0); 1266} 1267 1268static int 1269est_get(device_t dev, struct cf_setting *set) 1270{ 1271 struct est_softc *sc; 1272 freq_info *f; 1273 1274 sc = device_get_softc(dev); 1275 f = est_get_current(sc->freq_list); 1276 if (f == NULL) 1277 return (ENXIO); 1278 1279 set->freq = f->freq; 1280 set->volts = f->volts; 1281 set->power = f->power; 1282 set->lat = EST_TRANS_LAT; 1283 set->dev = dev; 1284 return (0); 1285} 1286 1287static int 1288est_type(device_t dev, int *type) 1289{ 1290 1291 if (type == NULL) 1292 return (EINVAL); 1293 1294 *type = CPUFREQ_TYPE_ABSOLUTE; 1295 return (0); 1296} 1297