est.c revision 178719
1251881Speter/*- 2251881Speter * Copyright (c) 2004 Colin Percival 3251881Speter * Copyright (c) 2005 Nate Lawson 4251881Speter * All rights reserved. 5251881Speter * 6251881Speter * Redistribution and use in source and binary forms, with or without 7251881Speter * modification, are permitted providing that the following conditions 8251881Speter * are met: 9251881Speter * 1. Redistributions of source code must retain the above copyright 10251881Speter * notice, this list of conditions and the following disclaimer. 11251881Speter * 2. Redistributions in binary form must reproduce the above copyright 12251881Speter * notice, this list of conditions and the following disclaimer in the 13251881Speter * documentation and/or other materials provided with the distribution. 14251881Speter * 15251881Speter * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 16251881Speter * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17251881Speter * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18251881Speter * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19251881Speter * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20251881Speter * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21251881Speter * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22251881Speter * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23251881Speter * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 24251881Speter * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25251881Speter * POSSIBILITY OF SUCH DAMAGE. 26251881Speter */ 27251881Speter 28251881Speter#include <sys/cdefs.h> 29251881Speter__FBSDID("$FreeBSD: head/sys/i386/cpufreq/est.c 178719 2008-05-02 10:16:41Z rpaulo $"); 30251881Speter 31251881Speter#include <sys/param.h> 32251881Speter#include <sys/bus.h> 33251881Speter#include <sys/cpu.h> 34251881Speter#include <sys/kernel.h> 35251881Speter#include <sys/malloc.h> 36251881Speter#include <sys/module.h> 37251881Speter#include <sys/smp.h> 38251881Speter#include <sys/systm.h> 39251881Speter 40251881Speter#include "cpufreq_if.h" 41251881Speter#include <machine/md_var.h> 42251881Speter#include <machine/specialreg.h> 43251881Speter 44251881Speter#include <contrib/dev/acpica/acpi.h> 45251881Speter#include <dev/acpica/acpivar.h> 46251881Speter#include "acpi_if.h" 47251881Speter 48251881Speter/* Status/control registers (from the IA-32 System Programming Guide). */ 49251881Speter#define MSR_PERF_STATUS 0x198 50251881Speter#define MSR_PERF_CTL 0x199 51251881Speter 52251881Speter/* Register and bit for enabling SpeedStep. */ 53251881Speter#define MSR_MISC_ENABLE 0x1a0 54251881Speter#define MSR_SS_ENABLE (1<<16) 55251881Speter 56251881Speter/* Frequency and MSR control values. */ 57251881Spetertypedef struct { 58251881Speter uint16_t freq; 59251881Speter uint16_t volts; 60251881Speter uint16_t id16; 61251881Speter int power; 62251881Speter} freq_info; 63251881Speter 64251881Speter/* Identifying characteristics of a processor and supported frequencies. */ 65251881Spetertypedef struct { 66251881Speter const char *vendor; 67251881Speter uint32_t id32; 68251881Speter freq_info *freqtab; 69251881Speter} cpu_info; 70251881Speter 71251881Speterstruct est_softc { 72251881Speter device_t dev; 73251881Speter int acpi_settings; 74251881Speter freq_info *freq_list; 75251881Speter}; 76251881Speter 77251881Speter/* Convert MHz and mV into IDs for passing to the MSR. */ 78251881Speter#define ID16(MHz, mV, bus_clk) \ 79251881Speter (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4)) 80251881Speter#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \ 81251881Speter ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk))) 82251881Speter 83251881Speter/* Format for storing IDs in our table. */ 84251881Speter#define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \ 85251881Speter { MHz, mV, ID16(MHz, mV, bus_clk), mW } 86251881Speter#define FREQ_INFO(MHz, mV, bus_clk) \ 87251881Speter FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN) 88251881Speter#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \ 89251881Speter { intel_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 90251881Speter#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \ 91251881Speter { centaur_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 92251881Speter 93251881Speterconst char intel_id[] = "GenuineIntel"; 94251881Speterconst char centaur_id[] = "CentaurHauls"; 95251881Speter 96251881Speter/* Default bus clock value for Centrino processors. */ 97251881Speter#define INTEL_BUS_CLK 100 98251881Speter 99251881Speter/* XXX Update this if new CPUs have more settings. */ 100251881Speter#define EST_MAX_SETTINGS 10 101251881SpeterCTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS); 102251881Speter 103251881Speter/* Estimate in microseconds of latency for performing a transition. */ 104251881Speter#define EST_TRANS_LAT 1000 105251881Speter 106251881Speter/* 107251881Speter * Frequency (MHz) and voltage (mV) settings. Data from the 108251881Speter * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5. 109251881Speter * 110251881Speter * Dothan processors have multiple VID#s with different settings for 111251881Speter * each VID#. Since we can't uniquely identify this info 112251881Speter * without undisclosed methods from Intel, we can't support newer 113251881Speter * processors with this table method. If ACPI Px states are supported, 114251881Speter * we get info from them. 115251881Speter */ 116251881Speterstatic freq_info PM17_130[] = { 117251881Speter /* 130nm 1.70GHz Pentium M */ 118251881Speter FREQ_INFO(1700, 1484, INTEL_BUS_CLK), 119251881Speter FREQ_INFO(1400, 1308, INTEL_BUS_CLK), 120251881Speter FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 121251881Speter FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 122251881Speter FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 123251881Speter FREQ_INFO( 600, 956, INTEL_BUS_CLK), 124251881Speter FREQ_INFO( 0, 0, 1), 125251881Speter}; 126251881Speterstatic freq_info PM16_130[] = { 127251881Speter /* 130nm 1.60GHz Pentium M */ 128251881Speter FREQ_INFO(1600, 1484, INTEL_BUS_CLK), 129251881Speter FREQ_INFO(1400, 1420, INTEL_BUS_CLK), 130251881Speter FREQ_INFO(1200, 1276, INTEL_BUS_CLK), 131251881Speter FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 132251881Speter FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 133251881Speter FREQ_INFO( 600, 956, INTEL_BUS_CLK), 134251881Speter FREQ_INFO( 0, 0, 1), 135251881Speter}; 136251881Speterstatic freq_info PM15_130[] = { 137251881Speter /* 130nm 1.50GHz Pentium M */ 138251881Speter FREQ_INFO(1500, 1484, INTEL_BUS_CLK), 139251881Speter FREQ_INFO(1400, 1452, INTEL_BUS_CLK), 140251881Speter FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 141251881Speter FREQ_INFO(1000, 1228, INTEL_BUS_CLK), 142251881Speter FREQ_INFO( 800, 1116, INTEL_BUS_CLK), 143251881Speter FREQ_INFO( 600, 956, INTEL_BUS_CLK), 144251881Speter FREQ_INFO( 0, 0, 1), 145251881Speter}; 146251881Speterstatic freq_info PM14_130[] = { 147251881Speter /* 130nm 1.40GHz Pentium M */ 148251881Speter FREQ_INFO(1400, 1484, INTEL_BUS_CLK), 149251881Speter FREQ_INFO(1200, 1436, INTEL_BUS_CLK), 150251881Speter FREQ_INFO(1000, 1308, INTEL_BUS_CLK), 151251881Speter FREQ_INFO( 800, 1180, INTEL_BUS_CLK), 152251881Speter FREQ_INFO( 600, 956, INTEL_BUS_CLK), 153251881Speter FREQ_INFO( 0, 0, 1), 154251881Speter}; 155251881Speterstatic freq_info PM13_130[] = { 156251881Speter /* 130nm 1.30GHz Pentium M */ 157251881Speter FREQ_INFO(1300, 1388, INTEL_BUS_CLK), 158251881Speter FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 159251881Speter FREQ_INFO(1000, 1292, INTEL_BUS_CLK), 160251881Speter FREQ_INFO( 800, 1260, INTEL_BUS_CLK), 161251881Speter FREQ_INFO( 600, 956, INTEL_BUS_CLK), 162251881Speter FREQ_INFO( 0, 0, 1), 163251881Speter}; 164251881Speterstatic freq_info PM13_LV_130[] = { 165251881Speter /* 130nm 1.30GHz Low Voltage Pentium M */ 166251881Speter FREQ_INFO(1300, 1180, INTEL_BUS_CLK), 167251881Speter FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 168251881Speter FREQ_INFO(1100, 1100, INTEL_BUS_CLK), 169251881Speter FREQ_INFO(1000, 1020, INTEL_BUS_CLK), 170251881Speter FREQ_INFO( 900, 1004, INTEL_BUS_CLK), 171251881Speter FREQ_INFO( 800, 988, INTEL_BUS_CLK), 172251881Speter FREQ_INFO( 600, 956, INTEL_BUS_CLK), 173251881Speter FREQ_INFO( 0, 0, 1), 174251881Speter}; 175251881Speterstatic freq_info PM12_LV_130[] = { 176251881Speter /* 130 nm 1.20GHz Low Voltage Pentium M */ 177251881Speter FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 178251881Speter FREQ_INFO(1100, 1164, INTEL_BUS_CLK), 179251881Speter FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 180251881Speter FREQ_INFO( 900, 1020, INTEL_BUS_CLK), 181251881Speter FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 182251881Speter FREQ_INFO( 600, 956, INTEL_BUS_CLK), 183251881Speter FREQ_INFO( 0, 0, 1), 184251881Speter}; 185251881Speterstatic freq_info PM11_LV_130[] = { 186251881Speter /* 130 nm 1.10GHz Low Voltage Pentium M */ 187251881Speter FREQ_INFO(1100, 1180, INTEL_BUS_CLK), 188251881Speter FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 189251881Speter FREQ_INFO( 900, 1100, INTEL_BUS_CLK), 190251881Speter FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 191251881Speter FREQ_INFO( 600, 956, INTEL_BUS_CLK), 192251881Speter FREQ_INFO( 0, 0, 1), 193251881Speter}; 194251881Speterstatic freq_info PM11_ULV_130[] = { 195251881Speter /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */ 196251881Speter FREQ_INFO(1100, 1004, INTEL_BUS_CLK), 197251881Speter FREQ_INFO(1000, 988, INTEL_BUS_CLK), 198251881Speter FREQ_INFO( 900, 972, INTEL_BUS_CLK), 199251881Speter FREQ_INFO( 800, 956, INTEL_BUS_CLK), 200251881Speter FREQ_INFO( 600, 844, INTEL_BUS_CLK), 201251881Speter FREQ_INFO( 0, 0, 1), 202251881Speter}; 203251881Speterstatic freq_info PM10_ULV_130[] = { 204251881Speter /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */ 205251881Speter FREQ_INFO(1000, 1004, INTEL_BUS_CLK), 206251881Speter FREQ_INFO( 900, 988, INTEL_BUS_CLK), 207251881Speter FREQ_INFO( 800, 972, INTEL_BUS_CLK), 208251881Speter FREQ_INFO( 600, 844, INTEL_BUS_CLK), 209251881Speter FREQ_INFO( 0, 0, 1), 210251881Speter}; 211251881Speter 212251881Speter/* 213251881Speter * Data from "Intel Pentium M Processor on 90nm Process with 214251881Speter * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5. 215251881Speter */ 216251881Speterstatic freq_info PM_765A_90[] = { 217251881Speter /* 90 nm 2.10GHz Pentium M, VID #A */ 218251881Speter FREQ_INFO(2100, 1340, INTEL_BUS_CLK), 219251881Speter FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 220251881Speter FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 221251881Speter FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 222251881Speter FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 223251881Speter FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 224251881Speter FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 225251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 226251881Speter FREQ_INFO( 0, 0, 1), 227251881Speter}; 228251881Speterstatic freq_info PM_765B_90[] = { 229251881Speter /* 90 nm 2.10GHz Pentium M, VID #B */ 230251881Speter FREQ_INFO(2100, 1324, INTEL_BUS_CLK), 231251881Speter FREQ_INFO(1800, 1260, INTEL_BUS_CLK), 232251881Speter FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 233251881Speter FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 234251881Speter FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 235251881Speter FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 236251881Speter FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 237251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 238251881Speter FREQ_INFO( 0, 0, 1), 239251881Speter}; 240251881Speterstatic freq_info PM_765C_90[] = { 241251881Speter /* 90 nm 2.10GHz Pentium M, VID #C */ 242251881Speter FREQ_INFO(2100, 1308, INTEL_BUS_CLK), 243251881Speter FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 244251881Speter FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 245251881Speter FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 246251881Speter FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 247251881Speter FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 248251881Speter FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 249251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 250251881Speter FREQ_INFO( 0, 0, 1), 251251881Speter}; 252251881Speterstatic freq_info PM_765E_90[] = { 253251881Speter /* 90 nm 2.10GHz Pentium M, VID #E */ 254251881Speter FREQ_INFO(2100, 1356, INTEL_BUS_CLK), 255251881Speter FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 256251881Speter FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 257251881Speter FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 258251881Speter FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 259251881Speter FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 260251881Speter FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 261251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 262251881Speter FREQ_INFO( 0, 0, 1), 263251881Speter}; 264251881Speterstatic freq_info PM_755A_90[] = { 265251881Speter /* 90 nm 2.00GHz Pentium M, VID #A */ 266251881Speter FREQ_INFO(2000, 1340, INTEL_BUS_CLK), 267251881Speter FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 268251881Speter FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 269251881Speter FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 270251881Speter FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 271251881Speter FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 272251881Speter FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 273251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 274251881Speter FREQ_INFO( 0, 0, 1), 275251881Speter}; 276251881Speterstatic freq_info PM_755B_90[] = { 277251881Speter /* 90 nm 2.00GHz Pentium M, VID #B */ 278251881Speter FREQ_INFO(2000, 1324, INTEL_BUS_CLK), 279251881Speter FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 280251881Speter FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 281251881Speter FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 282251881Speter FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 283251881Speter FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 284251881Speter FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 285251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 286251881Speter FREQ_INFO( 0, 0, 1), 287251881Speter}; 288251881Speterstatic freq_info PM_755C_90[] = { 289251881Speter /* 90 nm 2.00GHz Pentium M, VID #C */ 290251881Speter FREQ_INFO(2000, 1308, INTEL_BUS_CLK), 291251881Speter FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 292251881Speter FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 293251881Speter FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 294251881Speter FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 295251881Speter FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 296251881Speter FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 297251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 298251881Speter FREQ_INFO( 0, 0, 1), 299251881Speter}; 300251881Speterstatic freq_info PM_755D_90[] = { 301251881Speter /* 90 nm 2.00GHz Pentium M, VID #D */ 302251881Speter FREQ_INFO(2000, 1276, INTEL_BUS_CLK), 303251881Speter FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 304251881Speter FREQ_INFO(1600, 1196, INTEL_BUS_CLK), 305251881Speter FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 306251881Speter FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 307251881Speter FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 308251881Speter FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 309251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 310251881Speter FREQ_INFO( 0, 0, 1), 311251881Speter}; 312251881Speterstatic freq_info PM_745A_90[] = { 313251881Speter /* 90 nm 1.80GHz Pentium M, VID #A */ 314251881Speter FREQ_INFO(1800, 1340, INTEL_BUS_CLK), 315251881Speter FREQ_INFO(1600, 1292, INTEL_BUS_CLK), 316251881Speter FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 317251881Speter FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 318251881Speter FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 319251881Speter FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 320251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 321251881Speter FREQ_INFO( 0, 0, 1), 322251881Speter}; 323251881Speterstatic freq_info PM_745B_90[] = { 324251881Speter /* 90 nm 1.80GHz Pentium M, VID #B */ 325251881Speter FREQ_INFO(1800, 1324, INTEL_BUS_CLK), 326251881Speter FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 327251881Speter FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 328251881Speter FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 329251881Speter FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 330251881Speter FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 331251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 332251881Speter FREQ_INFO( 0, 0, 1), 333251881Speter}; 334251881Speterstatic freq_info PM_745C_90[] = { 335251881Speter /* 90 nm 1.80GHz Pentium M, VID #C */ 336251881Speter FREQ_INFO(1800, 1308, INTEL_BUS_CLK), 337251881Speter FREQ_INFO(1600, 1260, INTEL_BUS_CLK), 338251881Speter FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 339251881Speter FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 340251881Speter FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 341251881Speter FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 342251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 343251881Speter FREQ_INFO( 0, 0, 1), 344251881Speter}; 345251881Speterstatic freq_info PM_745D_90[] = { 346251881Speter /* 90 nm 1.80GHz Pentium M, VID #D */ 347251881Speter FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 348251881Speter FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 349251881Speter FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 350251881Speter FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 351251881Speter FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 352251881Speter FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 353251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 354251881Speter FREQ_INFO( 0, 0, 1), 355251881Speter}; 356251881Speterstatic freq_info PM_735A_90[] = { 357251881Speter /* 90 nm 1.70GHz Pentium M, VID #A */ 358251881Speter FREQ_INFO(1700, 1340, INTEL_BUS_CLK), 359251881Speter FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 360251881Speter FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 361251881Speter FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 362251881Speter FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 363251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 364251881Speter FREQ_INFO( 0, 0, 1), 365251881Speter}; 366251881Speterstatic freq_info PM_735B_90[] = { 367251881Speter /* 90 nm 1.70GHz Pentium M, VID #B */ 368251881Speter FREQ_INFO(1700, 1324, INTEL_BUS_CLK), 369251881Speter FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 370251881Speter FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 371251881Speter FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 372251881Speter FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 373251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 374251881Speter FREQ_INFO( 0, 0, 1), 375251881Speter}; 376251881Speterstatic freq_info PM_735C_90[] = { 377251881Speter /* 90 nm 1.70GHz Pentium M, VID #C */ 378251881Speter FREQ_INFO(1700, 1308, INTEL_BUS_CLK), 379251881Speter FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 380251881Speter FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 381251881Speter FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 382251881Speter FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 383251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 384251881Speter FREQ_INFO( 0, 0, 1), 385251881Speter}; 386251881Speterstatic freq_info PM_735D_90[] = { 387251881Speter /* 90 nm 1.70GHz Pentium M, VID #D */ 388251881Speter FREQ_INFO(1700, 1276, INTEL_BUS_CLK), 389251881Speter FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 390251881Speter FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 391251881Speter FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 392251881Speter FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 393251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 394251881Speter FREQ_INFO( 0, 0, 1), 395251881Speter}; 396251881Speterstatic freq_info PM_725A_90[] = { 397251881Speter /* 90 nm 1.60GHz Pentium M, VID #A */ 398251881Speter FREQ_INFO(1600, 1340, INTEL_BUS_CLK), 399251881Speter FREQ_INFO(1400, 1276, INTEL_BUS_CLK), 400251881Speter FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 401251881Speter FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 402251881Speter FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 403251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 404251881Speter FREQ_INFO( 0, 0, 1), 405251881Speter}; 406251881Speterstatic freq_info PM_725B_90[] = { 407251881Speter /* 90 nm 1.60GHz Pentium M, VID #B */ 408251881Speter FREQ_INFO(1600, 1324, INTEL_BUS_CLK), 409251881Speter FREQ_INFO(1400, 1260, INTEL_BUS_CLK), 410251881Speter FREQ_INFO(1200, 1196, INTEL_BUS_CLK), 411251881Speter FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 412251881Speter FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 413251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 414251881Speter FREQ_INFO( 0, 0, 1), 415251881Speter}; 416251881Speterstatic freq_info PM_725C_90[] = { 417251881Speter /* 90 nm 1.60GHz Pentium M, VID #C */ 418251881Speter FREQ_INFO(1600, 1308, INTEL_BUS_CLK), 419251881Speter FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 420251881Speter FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 421251881Speter FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 422251881Speter FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 423251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 424251881Speter FREQ_INFO( 0, 0, 1), 425251881Speter}; 426251881Speterstatic freq_info PM_725D_90[] = { 427251881Speter /* 90 nm 1.60GHz Pentium M, VID #D */ 428251881Speter FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 429251881Speter FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 430251881Speter FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 431251881Speter FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 432251881Speter FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 433251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 434251881Speter FREQ_INFO( 0, 0, 1), 435251881Speter}; 436251881Speterstatic freq_info PM_715A_90[] = { 437251881Speter /* 90 nm 1.50GHz Pentium M, VID #A */ 438251881Speter FREQ_INFO(1500, 1340, INTEL_BUS_CLK), 439251881Speter FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 440251881Speter FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 441251881Speter FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 442251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 443251881Speter FREQ_INFO( 0, 0, 1), 444251881Speter}; 445251881Speterstatic freq_info PM_715B_90[] = { 446251881Speter /* 90 nm 1.50GHz Pentium M, VID #B */ 447251881Speter FREQ_INFO(1500, 1324, INTEL_BUS_CLK), 448251881Speter FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 449251881Speter FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 450251881Speter FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 451251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 452251881Speter FREQ_INFO( 0, 0, 1), 453251881Speter}; 454251881Speterstatic freq_info PM_715C_90[] = { 455251881Speter /* 90 nm 1.50GHz Pentium M, VID #C */ 456251881Speter FREQ_INFO(1500, 1308, INTEL_BUS_CLK), 457251881Speter FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 458251881Speter FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 459251881Speter FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 460251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 461251881Speter FREQ_INFO( 0, 0, 1), 462251881Speter}; 463251881Speterstatic freq_info PM_715D_90[] = { 464251881Speter /* 90 nm 1.50GHz Pentium M, VID #D */ 465251881Speter FREQ_INFO(1500, 1276, INTEL_BUS_CLK), 466251881Speter FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 467251881Speter FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 468251881Speter FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 469251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 470251881Speter FREQ_INFO( 0, 0, 1), 471251881Speter}; 472251881Speterstatic freq_info PM_778_90[] = { 473251881Speter /* 90 nm 1.60GHz Low Voltage Pentium M */ 474251881Speter FREQ_INFO(1600, 1116, INTEL_BUS_CLK), 475251881Speter FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 476251881Speter FREQ_INFO(1400, 1100, INTEL_BUS_CLK), 477251881Speter FREQ_INFO(1300, 1084, INTEL_BUS_CLK), 478251881Speter FREQ_INFO(1200, 1068, INTEL_BUS_CLK), 479251881Speter FREQ_INFO(1100, 1052, INTEL_BUS_CLK), 480251881Speter FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 481251881Speter FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 482251881Speter FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 483251881Speter FREQ_INFO( 600, 988, INTEL_BUS_CLK), 484251881Speter FREQ_INFO( 0, 0, 1), 485251881Speter}; 486251881Speterstatic freq_info PM_758_90[] = { 487251881Speter /* 90 nm 1.50GHz Low Voltage Pentium M */ 488251881Speter FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 489251881Speter FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 490251881Speter FREQ_INFO(1300, 1100, INTEL_BUS_CLK), 491 FREQ_INFO(1200, 1084, INTEL_BUS_CLK), 492 FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 493 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 494 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 495 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 496 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 497 FREQ_INFO( 0, 0, 1), 498}; 499static freq_info PM_738_90[] = { 500 /* 90 nm 1.40GHz Low Voltage Pentium M */ 501 FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 502 FREQ_INFO(1300, 1116, INTEL_BUS_CLK), 503 FREQ_INFO(1200, 1100, INTEL_BUS_CLK), 504 FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 505 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 506 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 507 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 508 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 509 FREQ_INFO( 0, 0, 1), 510}; 511static freq_info PM_773G_90[] = { 512 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */ 513 FREQ_INFO(1300, 956, INTEL_BUS_CLK), 514 FREQ_INFO(1200, 940, INTEL_BUS_CLK), 515 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 516 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 517 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 518 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 519 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 520}; 521static freq_info PM_773H_90[] = { 522 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */ 523 FREQ_INFO(1300, 940, INTEL_BUS_CLK), 524 FREQ_INFO(1200, 924, INTEL_BUS_CLK), 525 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 526 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 527 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 528 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 529 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 530}; 531static freq_info PM_773I_90[] = { 532 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */ 533 FREQ_INFO(1300, 924, INTEL_BUS_CLK), 534 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 535 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 536 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 537 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 538 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 539 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 540}; 541static freq_info PM_773J_90[] = { 542 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */ 543 FREQ_INFO(1300, 908, INTEL_BUS_CLK), 544 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 545 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 546 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 547 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 548 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 549 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 550}; 551static freq_info PM_773K_90[] = { 552 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */ 553 FREQ_INFO(1300, 892, INTEL_BUS_CLK), 554 FREQ_INFO(1200, 892, INTEL_BUS_CLK), 555 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 556 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 557 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 558 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 559 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 560}; 561static freq_info PM_773L_90[] = { 562 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */ 563 FREQ_INFO(1300, 876, INTEL_BUS_CLK), 564 FREQ_INFO(1200, 876, INTEL_BUS_CLK), 565 FREQ_INFO(1100, 860, INTEL_BUS_CLK), 566 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 567 FREQ_INFO( 900, 844, INTEL_BUS_CLK), 568 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 569 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 570}; 571static freq_info PM_753G_90[] = { 572 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */ 573 FREQ_INFO(1200, 956, INTEL_BUS_CLK), 574 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 575 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 576 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 577 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 578 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 579}; 580static freq_info PM_753H_90[] = { 581 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */ 582 FREQ_INFO(1200, 940, INTEL_BUS_CLK), 583 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 584 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 585 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 586 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 587 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 588}; 589static freq_info PM_753I_90[] = { 590 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */ 591 FREQ_INFO(1200, 924, INTEL_BUS_CLK), 592 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 593 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 594 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 595 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 596 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 597}; 598static freq_info PM_753J_90[] = { 599 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */ 600 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 601 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 602 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 603 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 604 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 605 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 606}; 607static freq_info PM_753K_90[] = { 608 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */ 609 FREQ_INFO(1200, 892, INTEL_BUS_CLK), 610 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 611 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 612 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 613 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 614 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 615}; 616static freq_info PM_753L_90[] = { 617 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */ 618 FREQ_INFO(1200, 876, INTEL_BUS_CLK), 619 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 620 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 621 FREQ_INFO( 900, 844, INTEL_BUS_CLK), 622 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 623 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 624}; 625 626static freq_info PM_733JG_90[] = { 627 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */ 628 FREQ_INFO(1100, 956, INTEL_BUS_CLK), 629 FREQ_INFO(1000, 940, INTEL_BUS_CLK), 630 FREQ_INFO( 900, 908, INTEL_BUS_CLK), 631 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 632 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 633}; 634static freq_info PM_733JH_90[] = { 635 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */ 636 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 637 FREQ_INFO(1000, 924, INTEL_BUS_CLK), 638 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 639 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 640 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 641}; 642static freq_info PM_733JI_90[] = { 643 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */ 644 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 645 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 646 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 647 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 648 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 649}; 650static freq_info PM_733JJ_90[] = { 651 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */ 652 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 653 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 654 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 655 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 656 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 657}; 658static freq_info PM_733JK_90[] = { 659 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */ 660 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 661 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 662 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 663 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 664 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 665}; 666static freq_info PM_733JL_90[] = { 667 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */ 668 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 669 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 670 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 671 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 672 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 673}; 674static freq_info PM_733_90[] = { 675 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */ 676 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 677 FREQ_INFO(1000, 924, INTEL_BUS_CLK), 678 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 679 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 680 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 681 FREQ_INFO( 0, 0, 1), 682}; 683static freq_info PM_723_90[] = { 684 /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */ 685 FREQ_INFO(1000, 940, INTEL_BUS_CLK), 686 FREQ_INFO( 900, 908, INTEL_BUS_CLK), 687 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 688 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 689 FREQ_INFO( 0, 0, 1), 690}; 691 692/* 693 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants. 694 * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet. 695 */ 696static freq_info C7M_795[] = { 697 /* 2.00GHz Centaur C7-M 533 Mhz FSB */ 698 FREQ_INFO_PWR(2000, 1148, 133, 20000), 699 FREQ_INFO_PWR(1867, 1132, 133, 18000), 700 FREQ_INFO_PWR(1600, 1100, 133, 15000), 701 FREQ_INFO_PWR(1467, 1052, 133, 13000), 702 FREQ_INFO_PWR(1200, 1004, 133, 10000), 703 FREQ_INFO_PWR( 800, 844, 133, 7000), 704 FREQ_INFO_PWR( 667, 844, 133, 6000), 705 FREQ_INFO_PWR( 533, 844, 133, 5000), 706 FREQ_INFO(0, 0, 1), 707}; 708static freq_info C7M_785[] = { 709 /* 1.80GHz Centaur C7-M 533 Mhz FSB */ 710 FREQ_INFO_PWR(1867, 1148, 133, 18000), 711 FREQ_INFO_PWR(1600, 1100, 133, 15000), 712 FREQ_INFO_PWR(1467, 1052, 133, 13000), 713 FREQ_INFO_PWR(1200, 1004, 133, 10000), 714 FREQ_INFO_PWR( 800, 844, 133, 7000), 715 FREQ_INFO_PWR( 667, 844, 133, 6000), 716 FREQ_INFO_PWR( 533, 844, 133, 5000), 717 FREQ_INFO(0, 0, 1), 718}; 719static freq_info C7M_765[] = { 720 /* 1.60GHz Centaur C7-M 533 Mhz FSB */ 721 FREQ_INFO_PWR(1600, 1084, 133, 15000), 722 FREQ_INFO_PWR(1467, 1052, 133, 13000), 723 FREQ_INFO_PWR(1200, 1004, 133, 10000), 724 FREQ_INFO_PWR( 800, 844, 133, 7000), 725 FREQ_INFO_PWR( 667, 844, 133, 6000), 726 FREQ_INFO_PWR( 533, 844, 133, 5000), 727 FREQ_INFO(0, 0, 1), 728}; 729 730static freq_info C7M_794[] = { 731 /* 2.00GHz Centaur C7-M 400 Mhz FSB */ 732 FREQ_INFO_PWR(2000, 1148, 100, 20000), 733 FREQ_INFO_PWR(1800, 1132, 100, 18000), 734 FREQ_INFO_PWR(1600, 1100, 100, 15000), 735 FREQ_INFO_PWR(1400, 1052, 100, 13000), 736 FREQ_INFO_PWR(1000, 1004, 100, 10000), 737 FREQ_INFO_PWR( 800, 844, 100, 7000), 738 FREQ_INFO_PWR( 600, 844, 100, 6000), 739 FREQ_INFO_PWR( 400, 844, 100, 5000), 740 FREQ_INFO(0, 0, 1), 741}; 742static freq_info C7M_784[] = { 743 /* 1.80GHz Centaur C7-M 400 Mhz FSB */ 744 FREQ_INFO_PWR(1800, 1148, 100, 18000), 745 FREQ_INFO_PWR(1600, 1100, 100, 15000), 746 FREQ_INFO_PWR(1400, 1052, 100, 13000), 747 FREQ_INFO_PWR(1000, 1004, 100, 10000), 748 FREQ_INFO_PWR( 800, 844, 100, 7000), 749 FREQ_INFO_PWR( 600, 844, 100, 6000), 750 FREQ_INFO_PWR( 400, 844, 100, 5000), 751 FREQ_INFO(0, 0, 1), 752}; 753static freq_info C7M_764[] = { 754 /* 1.60GHz Centaur C7-M 400 Mhz FSB */ 755 FREQ_INFO_PWR(1600, 1084, 100, 15000), 756 FREQ_INFO_PWR(1400, 1052, 100, 13000), 757 FREQ_INFO_PWR(1000, 1004, 100, 10000), 758 FREQ_INFO_PWR( 800, 844, 100, 7000), 759 FREQ_INFO_PWR( 600, 844, 100, 6000), 760 FREQ_INFO_PWR( 400, 844, 100, 5000), 761 FREQ_INFO(0, 0, 1), 762}; 763static freq_info C7M_754[] = { 764 /* 1.50GHz Centaur C7-M 400 Mhz FSB */ 765 FREQ_INFO_PWR(1500, 1004, 100, 12000), 766 FREQ_INFO_PWR(1400, 988, 100, 11000), 767 FREQ_INFO_PWR(1000, 940, 100, 9000), 768 FREQ_INFO_PWR( 800, 844, 100, 7000), 769 FREQ_INFO_PWR( 600, 844, 100, 6000), 770 FREQ_INFO_PWR( 400, 844, 100, 5000), 771 FREQ_INFO(0, 0, 1), 772}; 773static freq_info C7M_771[] = { 774 /* 1.20GHz Centaur C7-M 400 Mhz FSB */ 775 FREQ_INFO_PWR(1200, 860, 100, 7000), 776 FREQ_INFO_PWR(1000, 860, 100, 6000), 777 FREQ_INFO_PWR( 800, 844, 100, 5500), 778 FREQ_INFO_PWR( 600, 844, 100, 5000), 779 FREQ_INFO_PWR( 400, 844, 100, 4000), 780 FREQ_INFO(0, 0, 1), 781}; 782 783static freq_info C7M_775_ULV[] = { 784 /* 1.50GHz Centaur C7-M ULV */ 785 FREQ_INFO_PWR(1500, 956, 100, 7500), 786 FREQ_INFO_PWR(1400, 940, 100, 6000), 787 FREQ_INFO_PWR(1000, 860, 100, 5000), 788 FREQ_INFO_PWR( 800, 828, 100, 2800), 789 FREQ_INFO_PWR( 600, 796, 100, 2500), 790 FREQ_INFO_PWR( 400, 796, 100, 2000), 791 FREQ_INFO(0, 0, 1), 792}; 793static freq_info C7M_772_ULV[] = { 794 /* 1.20GHz Centaur C7-M ULV */ 795 FREQ_INFO_PWR(1200, 844, 100, 5000), 796 FREQ_INFO_PWR(1000, 844, 100, 4000), 797 FREQ_INFO_PWR( 800, 828, 100, 2800), 798 FREQ_INFO_PWR( 600, 796, 100, 2500), 799 FREQ_INFO_PWR( 400, 796, 100, 2000), 800 FREQ_INFO(0, 0, 1), 801}; 802static freq_info C7M_779_ULV[] = { 803 /* 1.00GHz Centaur C7-M ULV */ 804 FREQ_INFO_PWR(1000, 796, 100, 3500), 805 FREQ_INFO_PWR( 800, 796, 100, 2800), 806 FREQ_INFO_PWR( 600, 796, 100, 2500), 807 FREQ_INFO_PWR( 400, 796, 100, 2000), 808 FREQ_INFO(0, 0, 1), 809}; 810static freq_info C7M_770_ULV[] = { 811 /* 1.00GHz Centaur C7-M ULV */ 812 FREQ_INFO_PWR(1000, 844, 100, 5000), 813 FREQ_INFO_PWR( 800, 796, 100, 2800), 814 FREQ_INFO_PWR( 600, 796, 100, 2500), 815 FREQ_INFO_PWR( 400, 796, 100, 2000), 816 FREQ_INFO(0, 0, 1), 817}; 818 819static cpu_info ESTprocs[] = { 820 INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK), 821 INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK), 822 INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK), 823 INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK), 824 INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK), 825 INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK), 826 INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK), 827 INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK), 828 INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK), 829 INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK), 830 INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK), 831 INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK), 832 INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK), 833 INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK), 834 INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK), 835 INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK), 836 INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK), 837 INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK), 838 INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK), 839 INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK), 840 INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK), 841 INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK), 842 INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK), 843 INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK), 844 INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK), 845 INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK), 846 INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK), 847 INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK), 848 INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK), 849 INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK), 850 INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK), 851 INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK), 852 INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK), 853 INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK), 854 INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK), 855 INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK), 856 INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK), 857 INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK), 858 INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK), 859 INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK), 860 INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK), 861 INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK), 862 INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK), 863 INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK), 864 INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK), 865 INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK), 866 INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK), 867 INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK), 868 INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK), 869 INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK), 870 INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 871 INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK), 872 INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK), 873 INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK), 874 INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK), 875 INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 876 INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK), 877 878 CENTAUR(C7M_795, 2000, 1148, 533, 844, 133), 879 CENTAUR(C7M_794, 2000, 1148, 400, 844, 100), 880 CENTAUR(C7M_785, 1867, 1148, 533, 844, 133), 881 CENTAUR(C7M_784, 1800, 1148, 400, 844, 100), 882 CENTAUR(C7M_765, 1600, 1084, 533, 844, 133), 883 CENTAUR(C7M_764, 1600, 1084, 400, 844, 100), 884 CENTAUR(C7M_754, 1500, 1004, 400, 844, 100), 885 CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100), 886 CENTAUR(C7M_771, 1200, 860, 400, 844, 100), 887 CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100), 888 CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100), 889 CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100), 890 { NULL, 0, NULL }, 891}; 892 893static void est_identify(driver_t *driver, device_t parent); 894static int est_features(driver_t *driver, u_int *features); 895static int est_probe(device_t parent); 896static int est_attach(device_t parent); 897static int est_detach(device_t parent); 898static int est_get_info(device_t dev); 899static int est_acpi_info(device_t dev, freq_info **freqs); 900static int est_table_info(device_t dev, uint64_t msr, freq_info **freqs); 901static freq_info *est_get_current(freq_info *freq_list); 902static int est_settings(device_t dev, struct cf_setting *sets, int *count); 903static int est_set(device_t dev, const struct cf_setting *set); 904static int est_get(device_t dev, struct cf_setting *set); 905static int est_type(device_t dev, int *type); 906static int est_set_id16(device_t dev, uint16_t id16, int need_check); 907static void est_get_id16(uint16_t *id16_p); 908 909static device_method_t est_methods[] = { 910 /* Device interface */ 911 DEVMETHOD(device_identify, est_identify), 912 DEVMETHOD(device_probe, est_probe), 913 DEVMETHOD(device_attach, est_attach), 914 DEVMETHOD(device_detach, est_detach), 915 916 /* cpufreq interface */ 917 DEVMETHOD(cpufreq_drv_set, est_set), 918 DEVMETHOD(cpufreq_drv_get, est_get), 919 DEVMETHOD(cpufreq_drv_type, est_type), 920 DEVMETHOD(cpufreq_drv_settings, est_settings), 921 922 /* ACPI interface */ 923 DEVMETHOD(acpi_get_features, est_features), 924 925 {0, 0} 926}; 927 928static driver_t est_driver = { 929 "est", 930 est_methods, 931 sizeof(struct est_softc), 932}; 933 934static devclass_t est_devclass; 935DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0); 936 937static int 938est_features(driver_t *driver, u_int *features) 939{ 940 941 /* Notify the ACPI CPU that we support direct access to MSRs */ 942 *features = ACPI_CAP_PERF_MSRS; 943 return (0); 944} 945 946static void 947est_identify(driver_t *driver, device_t parent) 948{ 949 device_t child; 950 951 /* Make sure we're not being doubly invoked. */ 952 if (device_find_child(parent, "est", -1) != NULL) 953 return; 954 955 /* Check that CPUID is supported and the vendor is Intel.*/ 956 if (cpu_high == 0 || (strcmp(cpu_vendor, intel_id) != 0 && 957 strcmp(cpu_vendor, centaur_id) != 0)) 958 return; 959 960 /* 961 * Check if the CPU supports EST. 962 */ 963 if (!(cpu_feature2 & CPUID2_EST)) 964 return; 965 966 /* 967 * We add a child for each CPU since settings must be performed 968 * on each CPU in the SMP case. 969 */ 970 child = BUS_ADD_CHILD(parent, 0, "est", -1); 971 if (child == NULL) 972 device_printf(parent, "add est child failed\n"); 973} 974 975static int 976est_probe(device_t dev) 977{ 978 device_t perf_dev; 979 uint64_t msr; 980 int error, type; 981 982 if (resource_disabled("est", 0)) 983 return (ENXIO); 984 985 /* 986 * If the ACPI perf driver has attached and is not just offering 987 * info, let it manage things. 988 */ 989 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 990 if (perf_dev && device_is_attached(perf_dev)) { 991 error = CPUFREQ_DRV_TYPE(perf_dev, &type); 992 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 993 return (ENXIO); 994 } 995 996 /* Attempt to enable SpeedStep if not currently enabled. */ 997 msr = rdmsr(MSR_MISC_ENABLE); 998 if ((msr & MSR_SS_ENABLE) == 0) { 999 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE); 1000 if (bootverbose) 1001 device_printf(dev, "enabling SpeedStep\n"); 1002 1003 /* Check if the enable failed. */ 1004 msr = rdmsr(MSR_MISC_ENABLE); 1005 if ((msr & MSR_SS_ENABLE) == 0) { 1006 device_printf(dev, "failed to enable SpeedStep\n"); 1007 return (ENXIO); 1008 } 1009 } 1010 1011 device_set_desc(dev, "Enhanced SpeedStep Frequency Control"); 1012 return (0); 1013} 1014 1015static int 1016est_attach(device_t dev) 1017{ 1018 struct est_softc *sc; 1019 1020 sc = device_get_softc(dev); 1021 sc->dev = dev; 1022 1023 /* Check CPU for supported settings. */ 1024 if (est_get_info(dev)) 1025 return (ENXIO); 1026 1027 cpufreq_register(dev); 1028 return (0); 1029} 1030 1031static int 1032est_detach(device_t dev) 1033{ 1034#if 0 1035 struct est_softc *sc; 1036 1037 sc = device_get_softc(dev); 1038 if (sc->acpi_settings) 1039 free(sc->freq_list, M_DEVBUF); 1040#endif 1041 return (ENXIO); 1042} 1043 1044/* 1045 * Probe for supported CPU settings. First, check our static table of 1046 * settings. If no match, try using the ones offered by acpi_perf 1047 * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40 1048 * series) export both legacy SMM IO-based access and direct MSR access 1049 * but the direct access specifies invalid values for _PSS. 1050 */ 1051static int 1052est_get_info(device_t dev) 1053{ 1054 struct est_softc *sc; 1055 uint64_t msr; 1056 int error; 1057 1058 sc = device_get_softc(dev); 1059 msr = rdmsr(MSR_PERF_STATUS); 1060 error = est_table_info(dev, msr, &sc->freq_list); 1061 if (error) 1062 error = est_acpi_info(dev, &sc->freq_list); 1063 1064 if (error) { 1065 printf( 1066 "est: CPU supports Enhanced Speedstep, but is not recognized.\n" 1067 "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr); 1068 return (ENXIO); 1069 } 1070 1071 return (0); 1072} 1073 1074static int 1075est_acpi_info(device_t dev, freq_info **freqs) 1076{ 1077 struct est_softc *sc; 1078 struct cf_setting *sets; 1079 freq_info *table; 1080 device_t perf_dev; 1081 int count, error, i, j, maxi, maxfreq; 1082 1083 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 1084 if (perf_dev == NULL || !device_is_attached(perf_dev)) 1085 return (ENXIO); 1086 1087 /* Fetch settings from acpi_perf. */ 1088 sc = device_get_softc(dev); 1089 table = NULL; 1090 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); 1091 if (sets == NULL) 1092 return (ENOMEM); 1093 count = MAX_SETTINGS; 1094 error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count); 1095 if (error) 1096 goto out; 1097 1098 /* Parse settings into our local table format. */ 1099 table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT); 1100 if (table == NULL) { 1101 error = ENOMEM; 1102 goto out; 1103 } 1104 maxi = maxfreq = 0; 1105 for (i = 0, j = 0; i < count; i++) { 1106 /* 1107 * Confirm id16 value is correct. 1108 */ 1109 if (sets[i].freq > 0) { 1110 error = est_set_id16(dev, sets[i].spec[0], 1); 1111 if (error != 0) { 1112 if (bootverbose) 1113 device_printf(dev, "Invalid freq %u, " 1114 "ignored.\n", sets[i].freq); 1115 } else { 1116 table[j].freq = sets[i].freq; 1117 table[j].volts = sets[i].volts; 1118 table[j].id16 = sets[i].spec[0]; 1119 table[j].power = sets[i].power; 1120 ++j; 1121 if (sets[i].freq > maxfreq) { 1122 maxi = i; 1123 maxfreq = sets[i].freq; 1124 } 1125 1126 } 1127 /* restore saved setting */ 1128 est_set_id16(dev, sets[i].spec[0], 0); 1129 } 1130 } 1131 /* 1132 * Set the frequency to max, so we get through boot fast, and don't 1133 * handicap systems not running powerd. 1134 */ 1135 if (maxfreq != 0) { 1136 device_printf(dev, "Setting %d MHz\n", sets[maxi].freq); 1137 est_set_id16(dev, sets[maxi].spec[0], 0); 1138 } 1139 1140 /* Mark end of table with a terminator. */ 1141 bzero(&table[j], sizeof(freq_info)); 1142 1143 sc->acpi_settings = TRUE; 1144 *freqs = table; 1145 error = 0; 1146 1147out: 1148 if (sets) 1149 free(sets, M_TEMP); 1150 if (error && table) 1151 free(table, M_DEVBUF); 1152 return (error); 1153} 1154 1155static int 1156est_table_info(device_t dev, uint64_t msr, freq_info **freqs) 1157{ 1158 cpu_info *p; 1159 uint32_t id; 1160 1161 /* Find a table which matches (vendor, id32). */ 1162 id = msr >> 32; 1163 for (p = ESTprocs; p->id32 != 0; p++) { 1164 if (strcmp(p->vendor, cpu_vendor) == 0 && p->id32 == id) 1165 break; 1166 } 1167 if (p->id32 == 0) 1168 return (EOPNOTSUPP); 1169 1170 /* Make sure the current setpoint is valid. */ 1171 if (est_get_current(p->freqtab) == NULL) { 1172 device_printf(dev, "current setting not found in table\n"); 1173 return (EOPNOTSUPP); 1174 } 1175 1176 *freqs = p->freqtab; 1177 return (0); 1178} 1179 1180static void 1181est_get_id16(uint16_t *id16_p) 1182{ 1183 *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff; 1184} 1185 1186static int 1187est_set_id16(device_t dev, uint16_t id16, int need_check) 1188{ 1189 uint64_t msr; 1190 uint16_t new_id16; 1191 int ret = 0; 1192 1193 /* Read the current register, mask out the old, set the new id. */ 1194 msr = rdmsr(MSR_PERF_CTL); 1195 msr = (msr & ~0xffff) | id16; 1196 wrmsr(MSR_PERF_CTL, msr); 1197 1198 /* Wait a short while for the new setting. XXX Is this necessary? */ 1199 DELAY(EST_TRANS_LAT); 1200 1201 if (need_check) { 1202 est_get_id16(&new_id16); 1203 if (new_id16 != id16) { 1204 if (bootverbose) 1205 device_printf(dev, "Invalid id16 (set, cur) " 1206 "= (%u, %u)\n", id16, new_id16); 1207 ret = ENXIO; 1208 } 1209 } 1210 return (ret); 1211} 1212 1213static freq_info * 1214est_get_current(freq_info *freq_list) 1215{ 1216 freq_info *f; 1217 int i; 1218 uint16_t id16; 1219 1220 /* 1221 * Try a few times to get a valid value. Sometimes, if the CPU 1222 * is in the middle of an asynchronous transition (i.e., P4TCC), 1223 * we get a temporary invalid result. 1224 */ 1225 for (i = 0; i < 5; i++) { 1226 est_get_id16(&id16); 1227 for (f = freq_list; f->id16 != 0; f++) { 1228 if (f->id16 == id16) 1229 return (f); 1230 } 1231 DELAY(100); 1232 } 1233 return (NULL); 1234} 1235 1236static int 1237est_settings(device_t dev, struct cf_setting *sets, int *count) 1238{ 1239 struct est_softc *sc; 1240 freq_info *f; 1241 int i; 1242 1243 sc = device_get_softc(dev); 1244 if (*count < EST_MAX_SETTINGS) 1245 return (E2BIG); 1246 1247 i = 0; 1248 for (f = sc->freq_list; f->freq != 0; f++, i++) { 1249 sets[i].freq = f->freq; 1250 sets[i].volts = f->volts; 1251 sets[i].power = f->power; 1252 sets[i].lat = EST_TRANS_LAT; 1253 sets[i].dev = dev; 1254 } 1255 *count = i; 1256 1257 return (0); 1258} 1259 1260static int 1261est_set(device_t dev, const struct cf_setting *set) 1262{ 1263 struct est_softc *sc; 1264 freq_info *f; 1265 1266 /* Find the setting matching the requested one. */ 1267 sc = device_get_softc(dev); 1268 for (f = sc->freq_list; f->freq != 0; f++) { 1269 if (f->freq == set->freq) 1270 break; 1271 } 1272 if (f->freq == 0) 1273 return (EINVAL); 1274 1275 /* Read the current register, mask out the old, set the new id. */ 1276 est_set_id16(dev, f->id16, 0); 1277 1278 return (0); 1279} 1280 1281static int 1282est_get(device_t dev, struct cf_setting *set) 1283{ 1284 struct est_softc *sc; 1285 freq_info *f; 1286 1287 sc = device_get_softc(dev); 1288 f = est_get_current(sc->freq_list); 1289 if (f == NULL) 1290 return (ENXIO); 1291 1292 set->freq = f->freq; 1293 set->volts = f->volts; 1294 set->power = f->power; 1295 set->lat = EST_TRANS_LAT; 1296 set->dev = dev; 1297 return (0); 1298} 1299 1300static int 1301est_type(device_t dev, int *type) 1302{ 1303 1304 if (type == NULL) 1305 return (EINVAL); 1306 1307 *type = CPUFREQ_TYPE_ABSOLUTE; 1308 return (0); 1309} 1310