est.c revision 143902
1/*- 2 * Copyright (c) 2004 Colin Percival 3 * Copyright (c) 2005 Nate Lawson 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted providing that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/i386/cpufreq/est.c 143902 2005-03-21 06:43:25Z njl $"); 30 31#include <sys/param.h> 32#include <sys/bus.h> 33#include <sys/cpu.h> 34#include <sys/kernel.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37#include <sys/smp.h> 38#include <sys/systm.h> 39 40#include "cpufreq_if.h" 41#include <machine/md_var.h> 42 43/* Status/control registers (from the IA-32 System Programming Guide). */ 44#define MSR_PERF_STATUS 0x198 45#define MSR_PERF_CTL 0x199 46 47/* Register and bit for enabling SpeedStep. */ 48#define MSR_MISC_ENABLE 0x1a0 49#define MSR_SS_ENABLE (1<<16) 50 51/* Frequency and MSR control values. */ 52typedef struct { 53 uint16_t freq; 54 uint16_t volts; 55 uint16_t id16; 56 int power; 57} freq_info; 58 59/* Identifying characteristics of a processor and supported frequencies. */ 60typedef struct { 61 const char *vendor; 62 uint32_t id32; 63 uint32_t bus_clk; 64 freq_info *freqtab; 65} cpu_info; 66 67struct est_softc { 68 device_t dev; 69 int acpi_settings; 70 freq_info *freq_list; 71}; 72 73/* Convert MHz and mV into IDs for passing to the MSR. */ 74#define ID16(MHz, mV, bus_clk) \ 75 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4)) 76#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \ 77 ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk))) 78 79/* Format for storing IDs in our table. */ 80#define FREQ_INFO(MHz, mV, bus_clk) \ 81 { MHz, mV, ID16(MHz, mV, bus_clk), CPUFREQ_VAL_UNKNOWN } 82#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \ 83 { GenuineIntel, ID32(zhi, vhi, zlo, vlo, bus_clk), bus_clk, tab } 84 85const char GenuineIntel[] = "GenuineIntel"; 86 87/* Default bus clock value for Centrino processors. */ 88#define INTEL_BUS_CLK 100 89 90/* XXX Update this if new CPUs have more settings. */ 91#define EST_MAX_SETTINGS 10 92CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS); 93 94/* Estimate in microseconds of latency for performing a transition. */ 95#define EST_TRANS_LAT 10 96 97/* 98 * Frequency (MHz) and voltage (mV) settings. Data from the 99 * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5. 100 * 101 * Dothan processors have multiple VID#s with different settings for 102 * each VID#. Since we can't uniquely identify this info 103 * without undisclosed methods from Intel, we can't support newer 104 * processors with this table method. If ACPI Px states are supported, 105 * we get info from them. 106 */ 107static freq_info PM17_130[] = { 108 /* 130nm 1.70GHz Pentium M */ 109 FREQ_INFO(1700, 1484, INTEL_BUS_CLK), 110 FREQ_INFO(1400, 1308, INTEL_BUS_CLK), 111 FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 112 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 113 FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 114 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 115 FREQ_INFO( 0, 0, 1), 116}; 117static freq_info PM16_130[] = { 118 /* 130nm 1.60GHz Pentium M */ 119 FREQ_INFO(1600, 1484, INTEL_BUS_CLK), 120 FREQ_INFO(1400, 1420, INTEL_BUS_CLK), 121 FREQ_INFO(1200, 1276, INTEL_BUS_CLK), 122 FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 123 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 124 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 125 FREQ_INFO( 0, 0, 1), 126}; 127static freq_info PM15_130[] = { 128 /* 130nm 1.50GHz Pentium M */ 129 FREQ_INFO(1500, 1484, INTEL_BUS_CLK), 130 FREQ_INFO(1400, 1452, INTEL_BUS_CLK), 131 FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 132 FREQ_INFO(1000, 1228, INTEL_BUS_CLK), 133 FREQ_INFO( 800, 1116, INTEL_BUS_CLK), 134 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 135 FREQ_INFO( 0, 0, 1), 136}; 137static freq_info PM14_130[] = { 138 /* 130nm 1.40GHz Pentium M */ 139 FREQ_INFO(1400, 1484, INTEL_BUS_CLK), 140 FREQ_INFO(1200, 1436, INTEL_BUS_CLK), 141 FREQ_INFO(1000, 1308, INTEL_BUS_CLK), 142 FREQ_INFO( 800, 1180, INTEL_BUS_CLK), 143 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 144 FREQ_INFO( 0, 0, 1), 145}; 146static freq_info PM13_130[] = { 147 /* 130nm 1.30GHz Pentium M */ 148 FREQ_INFO(1300, 1388, INTEL_BUS_CLK), 149 FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 150 FREQ_INFO(1000, 1292, INTEL_BUS_CLK), 151 FREQ_INFO( 800, 1260, INTEL_BUS_CLK), 152 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 153 FREQ_INFO( 0, 0, 1), 154}; 155static freq_info PM13_LV_130[] = { 156 /* 130nm 1.30GHz Low Voltage Pentium M */ 157 FREQ_INFO(1300, 1180, INTEL_BUS_CLK), 158 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 159 FREQ_INFO(1100, 1100, INTEL_BUS_CLK), 160 FREQ_INFO(1000, 1020, INTEL_BUS_CLK), 161 FREQ_INFO( 900, 1004, INTEL_BUS_CLK), 162 FREQ_INFO( 800, 988, INTEL_BUS_CLK), 163 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 164 FREQ_INFO( 0, 0, 1), 165}; 166static freq_info PM12_LV_130[] = { 167 /* 130 nm 1.20GHz Low Voltage Pentium M */ 168 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 169 FREQ_INFO(1100, 1164, INTEL_BUS_CLK), 170 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 171 FREQ_INFO( 900, 1020, INTEL_BUS_CLK), 172 FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 173 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 174 FREQ_INFO( 0, 0, 1), 175}; 176static freq_info PM11_LV_130[] = { 177 /* 130 nm 1.10GHz Low Voltage Pentium M */ 178 FREQ_INFO(1100, 1180, INTEL_BUS_CLK), 179 FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 180 FREQ_INFO( 900, 1100, INTEL_BUS_CLK), 181 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 182 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 183 FREQ_INFO( 0, 0, 1), 184}; 185static freq_info PM11_ULV_130[] = { 186 /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */ 187 FREQ_INFO(1100, 1004, INTEL_BUS_CLK), 188 FREQ_INFO(1000, 988, INTEL_BUS_CLK), 189 FREQ_INFO( 900, 972, INTEL_BUS_CLK), 190 FREQ_INFO( 800, 956, INTEL_BUS_CLK), 191 FREQ_INFO( 600, 844, INTEL_BUS_CLK), 192 FREQ_INFO( 0, 0, 1), 193}; 194static freq_info PM10_ULV_130[] = { 195 /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */ 196 FREQ_INFO(1000, 1004, INTEL_BUS_CLK), 197 FREQ_INFO( 900, 988, INTEL_BUS_CLK), 198 FREQ_INFO( 800, 972, INTEL_BUS_CLK), 199 FREQ_INFO( 600, 844, INTEL_BUS_CLK), 200 FREQ_INFO( 0, 0, 1), 201}; 202 203/* 204 * Data from "Intel Pentium M Processor on 90nm Process with 205 * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5. 206 */ 207static freq_info PM_765A_90[] = { 208 /* 90 nm 2.10GHz Pentium M, VID #A */ 209 FREQ_INFO(2100, 1340, INTEL_BUS_CLK), 210 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 211 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 212 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 213 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 214 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 215 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 216 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 217 FREQ_INFO( 0, 0, 1), 218}; 219static freq_info PM_765B_90[] = { 220 /* 90 nm 2.10GHz Pentium M, VID #B */ 221 FREQ_INFO(2100, 1324, INTEL_BUS_CLK), 222 FREQ_INFO(1800, 1260, INTEL_BUS_CLK), 223 FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 224 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 225 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 226 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 227 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 228 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 229 FREQ_INFO( 0, 0, 1), 230}; 231static freq_info PM_765C_90[] = { 232 /* 90 nm 2.10GHz Pentium M, VID #C */ 233 FREQ_INFO(2100, 1308, INTEL_BUS_CLK), 234 FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 235 FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 236 FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 237 FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 238 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 239 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 240 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 241 FREQ_INFO( 0, 0, 1), 242}; 243static freq_info PM_765E_90[] = { 244 /* 90 nm 2.10GHz Pentium M, VID #E */ 245 FREQ_INFO(2100, 1356, INTEL_BUS_CLK), 246 FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 247 FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 248 FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 249 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 250 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 251 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 252 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 253 FREQ_INFO( 0, 0, 1), 254}; 255static freq_info PM_755A_90[] = { 256 /* 90 nm 2.00GHz Pentium M, VID #A */ 257 FREQ_INFO(2000, 1340, INTEL_BUS_CLK), 258 FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 259 FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 260 FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 261 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 262 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 263 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 264 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 265 FREQ_INFO( 0, 0, 1), 266}; 267static freq_info PM_755B_90[] = { 268 /* 90 nm 2.00GHz Pentium M, VID #B */ 269 FREQ_INFO(2000, 1324, INTEL_BUS_CLK), 270 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 271 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 272 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 273 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 274 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 275 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 276 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 277 FREQ_INFO( 0, 0, 1), 278}; 279static freq_info PM_755C_90[] = { 280 /* 90 nm 2.00GHz Pentium M, VID #C */ 281 FREQ_INFO(2000, 1308, INTEL_BUS_CLK), 282 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 283 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 284 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 285 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 286 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 287 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 288 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 289 FREQ_INFO( 0, 0, 1), 290}; 291static freq_info PM_755D_90[] = { 292 /* 90 nm 2.00GHz Pentium M, VID #D */ 293 FREQ_INFO(2000, 1276, INTEL_BUS_CLK), 294 FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 295 FREQ_INFO(1600, 1196, INTEL_BUS_CLK), 296 FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 297 FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 298 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 299 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 300 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 301 FREQ_INFO( 0, 0, 1), 302}; 303static freq_info PM_745A_90[] = { 304 /* 90 nm 1.80GHz Pentium M, VID #A */ 305 FREQ_INFO(1800, 1340, INTEL_BUS_CLK), 306 FREQ_INFO(1600, 1292, INTEL_BUS_CLK), 307 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 308 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 309 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 310 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 311 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 312 FREQ_INFO( 0, 0, 1), 313}; 314static freq_info PM_745B_90[] = { 315 /* 90 nm 1.80GHz Pentium M, VID #B */ 316 FREQ_INFO(1800, 1324, INTEL_BUS_CLK), 317 FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 318 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 319 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 320 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 321 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 322 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 323 FREQ_INFO( 0, 0, 1), 324}; 325static freq_info PM_745C_90[] = { 326 /* 90 nm 1.80GHz Pentium M, VID #C */ 327 FREQ_INFO(1800, 1308, INTEL_BUS_CLK), 328 FREQ_INFO(1600, 1260, INTEL_BUS_CLK), 329 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 330 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 331 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 332 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 333 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 334 FREQ_INFO( 0, 0, 1), 335}; 336static freq_info PM_745D_90[] = { 337 /* 90 nm 1.80GHz Pentium M, VID #D */ 338 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 339 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 340 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 341 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 342 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 343 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 344 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 345 FREQ_INFO( 0, 0, 1), 346}; 347static freq_info PM_735A_90[] = { 348 /* 90 nm 1.70GHz Pentium M, VID #A */ 349 FREQ_INFO(1700, 1340, INTEL_BUS_CLK), 350 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 351 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 352 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 353 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 354 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 355 FREQ_INFO( 0, 0, 1), 356}; 357static freq_info PM_735B_90[] = { 358 /* 90 nm 1.70GHz Pentium M, VID #B */ 359 FREQ_INFO(1700, 1324, INTEL_BUS_CLK), 360 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 361 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 362 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 363 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 364 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 365 FREQ_INFO( 0, 0, 1), 366}; 367static freq_info PM_735C_90[] = { 368 /* 90 nm 1.70GHz Pentium M, VID #C */ 369 FREQ_INFO(1700, 1308, INTEL_BUS_CLK), 370 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 371 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 372 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 373 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 374 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 375 FREQ_INFO( 0, 0, 1), 376}; 377static freq_info PM_735D_90[] = { 378 /* 90 nm 1.70GHz Pentium M, VID #D */ 379 FREQ_INFO(1700, 1276, INTEL_BUS_CLK), 380 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 381 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 382 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 383 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 384 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 385 FREQ_INFO( 0, 0, 1), 386}; 387static freq_info PM_725A_90[] = { 388 /* 90 nm 1.60GHz Pentium M, VID #A */ 389 FREQ_INFO(1600, 1340, INTEL_BUS_CLK), 390 FREQ_INFO(1400, 1276, INTEL_BUS_CLK), 391 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 392 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 393 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 394 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 395 FREQ_INFO( 0, 0, 1), 396}; 397static freq_info PM_725B_90[] = { 398 /* 90 nm 1.60GHz Pentium M, VID #B */ 399 FREQ_INFO(1600, 1324, INTEL_BUS_CLK), 400 FREQ_INFO(1400, 1260, INTEL_BUS_CLK), 401 FREQ_INFO(1200, 1196, INTEL_BUS_CLK), 402 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 403 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 404 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 405 FREQ_INFO( 0, 0, 1), 406}; 407static freq_info PM_725C_90[] = { 408 /* 90 nm 1.60GHz Pentium M, VID #C */ 409 FREQ_INFO(1600, 1308, INTEL_BUS_CLK), 410 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 411 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 412 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 413 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 414 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 415 FREQ_INFO( 0, 0, 1), 416}; 417static freq_info PM_725D_90[] = { 418 /* 90 nm 1.60GHz Pentium M, VID #D */ 419 FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 420 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 421 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 422 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 423 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 424 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 425 FREQ_INFO( 0, 0, 1), 426}; 427static freq_info PM_715A_90[] = { 428 /* 90 nm 1.50GHz Pentium M, VID #A */ 429 FREQ_INFO(1500, 1340, INTEL_BUS_CLK), 430 FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 431 FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 432 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 433 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 434 FREQ_INFO( 0, 0, 1), 435}; 436static freq_info PM_715B_90[] = { 437 /* 90 nm 1.50GHz Pentium M, VID #B */ 438 FREQ_INFO(1500, 1324, INTEL_BUS_CLK), 439 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 440 FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 441 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 442 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 443 FREQ_INFO( 0, 0, 1), 444}; 445static freq_info PM_715C_90[] = { 446 /* 90 nm 1.50GHz Pentium M, VID #C */ 447 FREQ_INFO(1500, 1308, INTEL_BUS_CLK), 448 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 449 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 450 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 451 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 452 FREQ_INFO( 0, 0, 1), 453}; 454static freq_info PM_715D_90[] = { 455 /* 90 nm 1.50GHz Pentium M, VID #D */ 456 FREQ_INFO(1500, 1276, INTEL_BUS_CLK), 457 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 458 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 459 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 460 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 461 FREQ_INFO( 0, 0, 1), 462}; 463static freq_info PM_738_90[] = { 464 /* 90 nm 1.40GHz Low Voltage Pentium M */ 465 FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 466 FREQ_INFO(1300, 1116, INTEL_BUS_CLK), 467 FREQ_INFO(1200, 1100, INTEL_BUS_CLK), 468 FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 469 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 470 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 471 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 472 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 473 FREQ_INFO( 0, 0, 1), 474}; 475static freq_info PM_733_90[] = { 476 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */ 477 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 478 FREQ_INFO(1000, 924, INTEL_BUS_CLK), 479 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 480 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 481 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 482 FREQ_INFO( 0, 0, 1), 483}; 484static freq_info PM_723_90[] = { 485 /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */ 486 FREQ_INFO(1000, 940, INTEL_BUS_CLK), 487 FREQ_INFO( 900, 908, INTEL_BUS_CLK), 488 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 489 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 490 FREQ_INFO( 0, 0, 1), 491}; 492 493static cpu_info ESTprocs[] = { 494 INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK), 495 INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK), 496 INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK), 497 INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK), 498 INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK), 499 INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK), 500 INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK), 501 INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK), 502 INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK), 503 INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK), 504 INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK), 505 INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK), 506 INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK), 507 INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK), 508 INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK), 509 INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK), 510 INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK), 511 INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK), 512 INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK), 513 INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK), 514 INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK), 515 INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK), 516 INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK), 517 INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK), 518 INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK), 519 INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK), 520 INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK), 521 INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK), 522 INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK), 523 INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK), 524 INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK), 525 INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK), 526 INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK), 527 INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK), 528 INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK), 529 INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 530 INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK), 531 { NULL, 0, 0, NULL }, 532}; 533 534static void est_identify(driver_t *driver, device_t parent); 535static int est_probe(device_t parent); 536static int est_attach(device_t parent); 537static int est_detach(device_t parent); 538static int est_get_info(device_t dev); 539static int est_acpi_info(device_t dev, freq_info **freqs); 540static int est_table_info(device_t dev, uint64_t msr, uint32_t bus_clk, 541 freq_info **freqs); 542static freq_info *est_get_current(freq_info *freq_list); 543static int est_settings(device_t dev, struct cf_setting *sets, int *count); 544static int est_set(device_t dev, const struct cf_setting *set); 545static int est_get(device_t dev, struct cf_setting *set); 546static int est_type(device_t dev, int *type); 547 548static device_method_t est_methods[] = { 549 /* Device interface */ 550 DEVMETHOD(device_identify, est_identify), 551 DEVMETHOD(device_probe, est_probe), 552 DEVMETHOD(device_attach, est_attach), 553 DEVMETHOD(device_detach, est_detach), 554 555 /* cpufreq interface */ 556 DEVMETHOD(cpufreq_drv_set, est_set), 557 DEVMETHOD(cpufreq_drv_get, est_get), 558 DEVMETHOD(cpufreq_drv_type, est_type), 559 DEVMETHOD(cpufreq_drv_settings, est_settings), 560 {0, 0} 561}; 562 563static driver_t est_driver = { 564 "est", 565 est_methods, 566 sizeof(struct est_softc), 567}; 568 569static devclass_t est_devclass; 570DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0); 571 572static void 573est_identify(driver_t *driver, device_t parent) 574{ 575 u_int p[4]; 576 577 /* Make sure we're not being doubly invoked. */ 578 if (device_find_child(parent, "est", -1) != NULL) 579 return; 580 581 /* Check that CPUID is supported and the vendor is Intel.*/ 582 if (cpu_high == 0 || strcmp(cpu_vendor, GenuineIntel) != 0) 583 return; 584 585 /* Read capability bits and check if the CPU supports EST. */ 586 do_cpuid(1, p); 587 if ((p[2] & 0x80) == 0) 588 return; 589 590 /* 591 * We add a child for each CPU since settings must be performed 592 * on each CPU in the SMP case. 593 */ 594 if (BUS_ADD_CHILD(parent, 0, "est", -1) == NULL) 595 device_printf(parent, "add est child failed\n"); 596} 597 598static int 599est_probe(device_t dev) 600{ 601 device_t perf_dev; 602 uint64_t msr; 603 int error, type; 604 605 if (resource_disabled("est", 0)) 606 return (ENXIO); 607 608 /* 609 * If the ACPI perf driver has attached and is not just offering 610 * info, let it manage things. 611 */ 612 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 613 if (perf_dev && device_is_attached(perf_dev)) { 614 error = CPUFREQ_DRV_TYPE(perf_dev, &type); 615 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 616 return (ENXIO); 617 } 618 619 /* Attempt to enable SpeedStep if not currently enabled. */ 620 msr = rdmsr(MSR_MISC_ENABLE); 621 if ((msr & MSR_SS_ENABLE) == 0) { 622 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE); 623 if (bootverbose) 624 device_printf(dev, "enabling SpeedStep\n"); 625 626 /* Check if the enable failed. */ 627 msr = rdmsr(MSR_MISC_ENABLE); 628 if ((msr & MSR_SS_ENABLE) == 0) { 629 device_printf(dev, "failed to enable SpeedStep\n"); 630 return (ENXIO); 631 } 632 } 633 634 device_set_desc(dev, "Enhanced SpeedStep Frequency Control"); 635 return (0); 636} 637 638static int 639est_attach(device_t dev) 640{ 641 struct est_softc *sc; 642 643 sc = device_get_softc(dev); 644 sc->dev = dev; 645 646 /* Check CPU for supported settings. */ 647 if (est_get_info(dev)) 648 return (ENXIO); 649 650 cpufreq_register(dev); 651 return (0); 652} 653 654static int 655est_detach(device_t dev) 656{ 657 struct est_softc *sc; 658 659 sc = device_get_softc(dev); 660 if (sc->acpi_settings) 661 free(sc->freq_list, M_DEVBUF); 662 return (ENXIO); 663} 664 665/* 666 * Probe for supported CPU settings. First, check our static table of 667 * settings. If no match, try using the ones offered by acpi_perf 668 * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40 669 * series) export both legacy SMM IO-based access and direct MSR access 670 * but the direct access specifies invalid values for _PSS. 671 */ 672static int 673est_get_info(device_t dev) 674{ 675 struct est_softc *sc; 676 uint64_t msr; 677 int error; 678 679 sc = device_get_softc(dev); 680 msr = rdmsr(MSR_PERF_STATUS); 681 error = est_table_info(dev, msr, INTEL_BUS_CLK, &sc->freq_list); 682 if (error) 683 error = est_acpi_info(dev, &sc->freq_list); 684 685 if (error) { 686 printf( 687 "est: CPU supports Enhanced Speedstep, but is not recognized.\n" 688 "est: Please update driver or contact the maintainer.\n" 689 "est: cpu_vendor %s, msr %0jx, bus_clk, %x\n", 690 cpu_vendor, msr, INTEL_BUS_CLK); 691 return (ENXIO); 692 } 693 694 return (0); 695} 696 697static int 698est_acpi_info(device_t dev, freq_info **freqs) 699{ 700 struct est_softc *sc; 701 struct cf_setting *sets; 702 freq_info *table; 703 device_t perf_dev; 704 int count, error, i; 705 706 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 707 if (perf_dev == NULL || !device_is_attached(perf_dev)) 708 return (ENXIO); 709 710 /* Fetch settings from acpi_perf. */ 711 sc = device_get_softc(dev); 712 table = NULL; 713 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); 714 if (sets == NULL) 715 return (ENOMEM); 716 error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count); 717 if (error) 718 goto out; 719 720 /* Parse settings into our local table format. */ 721 table = malloc(count * sizeof(freq_info), M_DEVBUF, M_NOWAIT); 722 if (table == NULL) { 723 error = ENOMEM; 724 goto out; 725 } 726 for (i = 0; i < count; i++) { 727 /* 728 * XXX Figure out validity checks for id16. At least some 729 * systems support both SMM access via SystemIO and the 730 * direct MSR access but only report the SystemIO values 731 * via _PSS. However, since we don't know what should be 732 * valid for this processor, it's hard to know what to check. 733 */ 734 table[i].freq = sets[i].freq; 735 table[i].volts = sets[i].volts; 736 table[i].id16 = sets[i].spec[0]; 737 table[i].power = sets[i].power; 738 } 739 740 sc->acpi_settings = TRUE; 741 *freqs = table; 742 error = 0; 743 744out: 745 if (sets) 746 free(sets, M_TEMP); 747 if (error && table) 748 free(table, M_DEVBUF); 749 return (error); 750} 751 752static int 753est_table_info(device_t dev, uint64_t msr, uint32_t bus_clk, freq_info **freqs) 754{ 755 cpu_info *p; 756 uint32_t id; 757 758 /* Find a table which matches (vendor, id, bus_clk). */ 759 id = msr >> 32; 760 for (p = ESTprocs; p->id32 != 0; p++) { 761 if (strcmp(p->vendor, cpu_vendor) == 0 && p->id32 == id && 762 p->bus_clk == bus_clk) 763 break; 764 } 765 if (p->id32 == 0) 766 return (EOPNOTSUPP); 767 768 /* Make sure the current setpoint is valid. */ 769 if (est_get_current(p->freqtab) == NULL) { 770 device_printf(dev, "current setting not found in table\n"); 771 return (EOPNOTSUPP); 772 } 773 774 *freqs = p->freqtab; 775 return (0); 776} 777 778static freq_info * 779est_get_current(freq_info *freq_list) 780{ 781 freq_info *f; 782 int i; 783 uint16_t id16; 784 785 /* 786 * Try a few times to get a valid value. Sometimes, if the CPU 787 * is in the middle of an asynchronous transition (i.e., P4TCC), 788 * we get a temporary invalid result. 789 */ 790 for (i = 0; i < 5; i++) { 791 id16 = rdmsr(MSR_PERF_STATUS) & 0xffff; 792 for (f = freq_list; f->id16 != 0; f++) { 793 if (f->id16 == id16) 794 return (f); 795 } 796 DELAY(100); 797 } 798 return (NULL); 799} 800 801static int 802est_settings(device_t dev, struct cf_setting *sets, int *count) 803{ 804 struct est_softc *sc; 805 freq_info *f; 806 int i; 807 808 sc = device_get_softc(dev); 809 if (*count < EST_MAX_SETTINGS) 810 return (E2BIG); 811 812 i = 0; 813 for (f = sc->freq_list; f->freq != 0; f++, i++) { 814 sets[i].freq = f->freq; 815 sets[i].volts = f->volts; 816 sets[i].power = f->power; 817 sets[i].lat = EST_TRANS_LAT; 818 sets[i].dev = dev; 819 } 820 *count = i; 821 822 return (0); 823} 824 825static int 826est_set(device_t dev, const struct cf_setting *set) 827{ 828 struct est_softc *sc; 829 freq_info *f; 830 uint64_t msr; 831 832 /* Find the setting matching the requested one. */ 833 sc = device_get_softc(dev); 834 for (f = sc->freq_list; f->freq != 0; f++) { 835 if (f->freq == set->freq) 836 break; 837 } 838 if (f->freq == 0) 839 return (EINVAL); 840 841 /* Read the current register, mask out the old, set the new id. */ 842 msr = rdmsr(MSR_PERF_CTL); 843 msr = (msr & ~0xffff) | f->id16; 844 wrmsr(MSR_PERF_CTL, msr); 845 846 /* Wait a short while for the new setting. XXX Is this necessary? */ 847 DELAY(EST_TRANS_LAT); 848 849 return (0); 850} 851 852static int 853est_get(device_t dev, struct cf_setting *set) 854{ 855 struct est_softc *sc; 856 freq_info *f; 857 858 sc = device_get_softc(dev); 859 f = est_get_current(sc->freq_list); 860 if (f == NULL) 861 return (ENXIO); 862 863 set->freq = f->freq; 864 set->volts = f->volts; 865 set->power = f->power; 866 set->lat = EST_TRANS_LAT; 867 set->dev = dev; 868 return (0); 869} 870 871static int 872est_type(device_t dev, int *type) 873{ 874 875 if (type == NULL) 876 return (EINVAL); 877 878 *type = CPUFREQ_TYPE_ABSOLUTE; 879 return (0); 880} 881