Searched refs:slice_mask (Results 1 - 22 of 22) sorted by relevance

/linux-master/arch/powerpc/mm/book3s64/
H A Dslice.c34 static void slice_print_mask(const char *label, const struct slice_mask *mask)
48 static void slice_print_mask(const char *label, const struct slice_mask *mask) {}
61 struct slice_mask *ret)
117 static void slice_mask_for_free(struct mm_struct *mm, struct slice_mask *ret,
139 const struct slice_mask *available,
188 const struct slice_mask *mask, int psize)
193 struct slice_mask *psize_mask, *old_mask;
215 /* Update the slice_mask */
234 /* Update the slice_mask */
262 const struct slice_mask *availabl
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/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_sseu_debugfs.c36 sseu->slice_mask = BIT(0);
87 sseu->slice_mask |= BIT(s);
140 sseu->slice_mask |= BIT(s);
175 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
177 if (sseu->slice_mask) {
179 for (s = 0; s < fls(sseu->slice_mask); s++)
185 for (s = 0; s < fls(sseu->slice_mask); s++) {
201 sseu->slice_mask);
203 hweight8(sseu->slice_mask));
H A Dintel_sseu.h69 u8 slice_mask; member in struct:sseu_dev_info
102 u8 slice_mask; member in struct:intel_sseu
112 .slice_mask = sseu->slice_mask,
H A Dintel_sseu.c156 sseu->slice_mask |= BIT(0);
172 sseu->slice_mask |= BIT(0);
333 sseu->slice_mask = BIT(0);
388 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
407 if (!(sseu->slice_mask & BIT(s)))
462 !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1;
493 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
519 if (!(sseu->slice_mask & BIT(s)))
564 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
586 sseu->slice_mask
879 unsigned long slice_mask = 0; local
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H A Dintel_workarounds.c1114 slice = ffs(sseu->slice_mask) - 1;
1263 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
1291 unsigned long slice, subslice = 0, slice_mask = 0; local
1322 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
1336 if (slice_mask & lncf_mask) {
1337 slice_mask &= lncf_mask;
1342 if (slice_mask & gt->info.mslice_mask) {
1343 slice_mask &= gt->info.mslice_mask;
1347 slice = __ffs(slice_mask);
/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dicp_qat_fw_loader_handle.h19 unsigned int slice_mask; member in struct:icp_qat_fw_loader_hal_handle
H A Dqat_hal.c798 handle->hal_handle->slice_mask = hw_data->accel_mask;
/linux-master/arch/powerpc/include/asm/book3s/64/
H A Dmmu-hash.h708 struct slice_mask { struct
721 struct slice_mask mask_64k;
723 struct slice_mask mask_4k;
725 struct slice_mask mask_16m;
726 struct slice_mask mask_16g;
H A Dmmu.h169 static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize)
/linux-master/drivers/gpu/drm/i915/
H A Di915_getparam.c172 value = sseu->slice_mask;
H A Di915_query.c42 BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
47 slice_length = sizeof(sseu->slice_mask);
73 &sseu->slice_mask, slice_length))
H A Di915_perf.c3201 out_sseu->slice_mask = 0x1;
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_display_device.c453 .dbuf.slice_mask = BIT(DBUF_S1),
477 .dbuf.slice_mask = BIT(DBUF_S1), \
517 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
570 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
658 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
725 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
H A Dintel_display_device.h142 u8 slice_mask; member in struct:intel_display_device_info::__anon592
H A Dskl_watermark.c526 hweight8(DISPLAY_INFO(i915)->dbuf.slice_mask);
530 skl_ddb_entry_for_slices(struct drm_i915_private *i915, u8 slice_mask, argument
535 if (!slice_mask) {
541 ddb->start = (ffs(slice_mask) - 1) * slice_size;
542 ddb->end = fls(slice_mask) * slice_size;
548 static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask) argument
552 if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2)))
553 slice_mask = BIT(DBUF_S1);
554 else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4)))
555 slice_mask
567 u8 slice_mask = 0; local
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H A Dintel_display_power.c1073 u8 slice_mask = DISPLAY_INFO(dev_priv)->dbuf.slice_mask; local
1076 drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
1078 req_slices, slice_mask);
H A Dintel_display.h115 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
/linux-master/drivers/gpu/drm/i915/gem/
H A Di915_gem_context.c1000 if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS))
1915 if (!user->slice_mask || !user->subslice_mask ||
1927 if (overflows_type(user->slice_mask, context->slice_mask) ||
1936 if (user->slice_mask & ~device->slice_mask)
1945 context->slice_mask = user->slice_mask;
1952 unsigned int hw_s = hweight8(device->slice_mask);
1954 unsigned int req_s = hweight8(context->slice_mask);
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/linux-master/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_context.c1169 unsigned int slices = hweight32(ce->engine->sseu.slice_mask);
1226 hweight32(sseu.slice_mask), spin);
1271 if (hweight32(engine->sseu.slice_mask) < 2)
1282 pg_sseu.slice_mask = 1;
1288 hweight32(engine->sseu.slice_mask),
1289 hweight32(pg_sseu.slice_mask));
/linux-master/tools/include/uapi/drm/
H A Di915_drm.h2194 __u64 slice_mask; member in struct:drm_i915_gem_context_param_sseu
/linux-master/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c892 hweight8(gt->info.sseu.slice_mask));
/linux-master/include/uapi/drm/
H A Di915_drm.h2209 __u64 slice_mask; member in struct:drm_i915_gem_context_param_sseu

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