/linux-master/arch/arm64/kvm/ |
H A D | guest.c | 399 * Number of register slices required to cover each whole SVE register. 653 const unsigned int slices = vcpu_sve_slices(vcpu); local 661 return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */) 668 const unsigned int slices = vcpu_sve_slices(vcpu); local 688 for (i = 0; i < slices; i++) {
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/linux-master/block/partitions/ |
H A D | sysv68.c | 51 int i, slices; local 68 slices = be16_to_cpu(b->dk_ios.ios_slccnt); 76 slices -= 1; /* last slice is the whole disk */ 77 snprintf(tmp, sizeof(tmp), "sysV68: %s(s%u)", state->name, slices); 80 for (i = 0; i < slices; i++, slice++) {
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/linux-master/drivers/accel/qaic/ |
H A D | qaic.h | 188 /* Head in list of slices of this BO */ 189 struct list_head slices; 190 /* Total nents, for all slices of this BO */ 265 /* Node in list of slices maintained by parent BO */ 181 struct list_head slices; member in struct:qaic_bo
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H A D | qaic_data.c | 425 list_add_tail(&slice->slice, &bo->slices); 658 INIT_LIST_HEAD(&bo->slices); 906 list_for_each_entry_safe(slice, temp, &bo->slices, slice) 1215 list_for_each_entry(slice, &bo->slices, slice) { 1594 * divided into multiple slices and a buffer receives as many 1595 * interrupts as slices. So until it receives interrupts for 1596 * all the slices we cannot mark that buffer complete.
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/linux-master/drivers/crypto/intel/qat/qat_common/ |
H A D | adf_admin.c | 334 struct icp_qat_fw_init_admin_slice_cnt *slices) 347 memcpy(slices, &resp.slices, sizeof(*slices)); 521 memcpy(slice_count, &resp.slices, sizeof(*slice_count)); 333 adf_send_admin_rl_init(struct adf_accel_dev *accel_dev, struct icp_qat_fw_init_admin_slice_cnt *slices) argument
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H A D | adf_admin.h | 18 struct icp_qat_fw_init_admin_slice_cnt *slices);
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H A D | adf_rl.c | 565 avail_slice_cycles *= device_data->slices.pke_cnt; 568 avail_slice_cycles *= device_data->slices.cph_cnt; 571 avail_slice_cycles *= device_data->slices.dcpr_cnt; 623 sla_to_bytes *= device_data->slices.dcpr_cnt - 1138 ret = adf_rl_send_admin_init_msg(accel_dev, &rl_hw_data->slices);
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H A D | adf_rl.h | 97 struct rl_slice_cnt slices; member in struct:adf_rl_hw_data
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H A D | icp_qat_fw_init_admin.h | 160 struct icp_qat_fw_init_admin_slice_cnt slices; member in union:icp_qat_fw_init_admin_resp::__anon106
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
H A D | display_mode_vba_20.c | 312 //valid numSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} 1806 unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k]; local 1818 slices, 1832 slices / 2.0, 4236 mode_lib->vba.slices = 0; 4239 mode_lib->vba.slices = 0; 4241 mode_lib->vba.slices = dml_ceil( 4245 mode_lib->vba.slices = 8.0; 4247 mode_lib->vba.slices = 4.0; 4249 mode_lib->vba.slices [all...] |
H A D | display_mode_vba_20v2.c | 336 //valid numSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} 1842 unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k]; local 1854 slices, 1868 slices / 2.0, 4357 mode_lib->vba.slices = 0; 4360 mode_lib->vba.slices = 0; 4362 mode_lib->vba.slices = dml_ceil( 4366 mode_lib->vba.slices = 8.0; 4368 mode_lib->vba.slices = 4.0; 4370 mode_lib->vba.slices [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
H A D | display_mode_vba_21.c | 507 //valid numSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} 1798 unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k]; local 1810 slices, 1824 slices / 2.0, 4451 mode_lib->vba.slices = 0; 4454 mode_lib->vba.slices = 0; 4456 mode_lib->vba.slices = dml_ceil( 4460 mode_lib->vba.slices = 8.0; 4462 mode_lib->vba.slices = 4.0; 4464 mode_lib->vba.slices [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/ |
H A D | display_mode_vba.h | 715 unsigned int slices; member in struct:vba_vars_st
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/linux-master/drivers/gpu/drm/i915/display/ |
H A D | skl_watermark.c | 576 * Per plane DDB entry can in a really worst case be on multiple slices 629 if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe]) 665 dbuf_slice_mask = new_dbuf_state->slices[pipe]; 682 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] && 703 "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n", 705 old_dbuf_state->slices[pipe], new_dbuf_state->slices[pipe], 850 * For more DBuf slices algorith 3066 u8 slices; local 3136 u8 slices; local [all...] |
H A D | skl_watermark.h | 59 u8 slices[I915_MAX_PIPES]; 58 u8 slices[I915_MAX_PIPES]; member in struct:intel_dbuf_state
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/linux-master/drivers/gpu/drm/i915/gem/selftests/ |
H A D | i915_gem_context.c | 1137 __check_rpcs(const char *name, u32 rpcs, int slices, unsigned int expected, argument 1140 if (slices == expected) 1143 if (slices < 0) { 1145 name, prefix, slices, suffix); 1146 return slices; 1150 name, prefix, slices, expected, suffix); 1153 rpcs, slices, 1169 unsigned int slices = hweight32(ce->engine->sseu.slice_mask); local 1186 ret = __check_rpcs(name, rpcs, ret, slices, "Kernel context", "!"); 1279 * half enabled sub-slices [all...] |
/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_sseu.c | 269 * Although gen12 architecture supported multiple slices, TGL, RKL, 306 * Although gen11 architecture supported multiple slices, ICL and 396 * to each of the enabled slices. 403 * Iterate through enabled slices and subslices to 498 * to each of the enabled slices. 515 * Iterate through enabled slices and subslices to 578 * There isn't a register to tell us how many slices/subslices. We 662 u8 slices, subslices; 679 slices = hweight8(req_sseu->slice_mask); 694 * If enabled subslice count is greater than four, two whole slices mus 667 u8 slices, subslices; local [all...] |
/linux-master/drivers/hte/ |
H A D | hte-tegra194.c | 120 u32 slices; member in struct:tegra_hte_data 326 .slices = 3, 335 .slices = 3, 342 .slices = 11, 349 .slices = 17, 689 u32 i, slices, val = 0; local 709 ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); 711 slices = hte_dev->prov_data->slices; 819 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; local 840 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; local [all...] |
/linux-master/drivers/misc/cxl/ |
H A D | cxl.h | 697 u8 slices; member in struct:cxl
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H A D | file.c | 55 if (slice > adapter->slices)
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H A D | flash.c | 349 for (afu = 0; afu < adapter->slices; afu++)
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H A D | guest.c | 273 for (i = 0; i < adapter->slices; i++) { 282 for (i = 0; i < adapter->slices; i++) { 943 adapter->slices++; 1117 adapter->slices = 0;
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H A D | main.c | 89 for (slice = 0; slice < adapter->slices; slice++) {
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H A D | of.c | 440 for (afu = 0; afu < adapter->slices; afu++) 484 adapter->slices = 0;
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H A D | pci.c | 1310 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices); 1324 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices; 1382 if (!adapter->slices) { 1560 for (slice = 0; slice < adapter->slices; slice++) { 1759 for (slice = 0; slice < adapter->slices; slice++) { 1783 for (i = 0; i < adapter->slices; i++) { 1844 for (i = 0; i < adapter->slices; i++) { 1938 for (i = 0; i < adapter->slices; i++) { 1992 for (i = 0; i < adapter->slices; i++) { 2075 for (i = 0; i < adapter->slices; [all...] |