Searched refs:slice (Results 1 - 25 of 75) sorted by path

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/linux-master/arch/mips/include/asm/octeon/
H A Dcvmx-gmxx-defs.h2196 uint64_t slice:7; member in struct:cvmx_gmxx_tx_spi_max::cvmx_gmxx_tx_spi_max_s
2202 uint64_t slice:7;
/linux-master/arch/mips/include/asm/sn/
H A Daddrs.h278 #define EX_HANDLER_OFFSET(slice) ((slice) << 16)
279 #define EX_HANDLER_ADDR(nasid, slice) \
280 PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice))
283 #define EX_FRAME_OFFSET(slice) ((slice) << 16 | 0x400)
284 #define EX_FRAME_ADDR(nasid, slice) \
285 PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice))
332 #define LAUNCH_OFFSET(nasid, slice) \
334 KLD_LAUNCH(nasid)->stride * (slice))
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/linux-master/arch/mips/include/asm/sn/sn0/
H A Daddrs.h143 #define KERN_NMI_ADDR(nasid, slice) \
145 (IP27_NMI_KREGS_CPU_SIZE * (slice)))
/linux-master/drivers/gpu/drm/omapdrm/
H A Dtcm.h213 * This method slices off the topmost 2D slice from the parent area, and stores
214 * it in the 'slice' parameter. The 'parent' parameter will get modified to
216 * fit in a 2D slice, its tcm pointer is set to NULL to mark that it is no
220 * @param slice Pointer to the slice area that will get modified
222 static inline void tcm_slice(struct tcm_area *parent, struct tcm_area *slice) argument
224 *slice = *parent;
226 /* check if we need to slice */
227 if (slice->tcm && !slice
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/linux-master/drivers/misc/cxl/
H A Ddebugfs.c104 snprintf(buf, 32, "psl%i.%i", afu->adapter->adapter_num, afu->slice);
H A Dtrace.h76 __entry->afu = ctx->afu->slice;
105 __entry->afu = ctx->afu->slice;
145 __entry->afu = ctx->afu->slice;
178 __entry->afu = ctx->afu->slice;
212 __entry->afu = ctx->afu->slice;
243 __entry->afu = ctx->afu->slice;
270 __entry->afu = ctx->afu->slice;
299 __entry->afu = ctx->afu->slice;
331 __entry->afu = ctx->afu->slice;
360 __entry->afu = ctx->afu->slice;
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/linux-master/sound/pci/au88x0/
H A Dau88x0_a3d.h38 unsigned int slice; /* this_08 */ member in struct:__anon1746
106 #define a3d_addrA(slice,source,reg) (((slice)<<0xd)+((source)*0x3A4)+(reg))
107 #define a3d_addrB(slice,source,reg) (((slice)<<0xd)+((source)*0x2C8)+(reg))
108 #define a3d_addrS(slice,reg) (((slice)<<0xd)+(reg))
109 //#define a3d_addr(slice,source,reg) (((reg)>=0x19000) ? a3d_addr2((slice),(source),(reg)) : a3d_addr1((slice),(sourc
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/linux-master/tools/perf/scripts/python/
H A Dsched-migration.py234 slice = TimeSlice(ts, TimeSlice(-1, None))
236 slice = self.data[-1].next(ts)
237 return slice
282 def update_rectangle_cpu(self, slice, cpu):
283 rq = slice.rqs[cpu]
285 if slice.total_load != 0:
286 load_rate = rq.load() / float(slice.total_load)
295 if cpu in slice.event_cpus:
298 self.root_win.paint_rectangle_zone(cpu, color, top_color, slice.start, slice
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/linux-master/arch/mips/cavium-octeon/executive/
H A Dcvmx-spi.c367 gmxx_tx_spi_max.s.slice = 0;
/linux-master/arch/mips/sgi-ip27/
H A Dip27-common.h11 extern void install_cpu_nmi_handler(int slice);
H A Dip27-irq.c256 int slice = LOCAL_HUB_L(PI_CPU_NUM); local
259 resched = CPU_RESCHED_A_IRQ + slice;
263 call = CPU_CALL_A_IRQ + slice;
267 if (slice == 0) {
H A Dip27-nmi.c30 void install_cpu_nmi_handler(int slice) argument
34 nmi_addr = (nmi_t *)NMI_ADDR(get_nasid(), slice);
49 static void nmi_cpu_eframe_save(nasid_t nasid, int slice) argument
57 slice * IP27_NMI_KREGS_CPU_SIZE);
59 pr_emerg("NMI nasid %d: slice %d\n", nasid, slice);
125 static void nmi_dump_hub_irq(nasid_t nasid, int slice) argument
129 if (slice == 0) { /* Slice A */
151 int slice; local
157 for (slice
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H A Dip27-timer.c33 int slice = cputoslice(cpu); local
38 LOCAL_HUB_S(PI_RT_COMPARE_A + PI_COUNT_OFFSET * slice, cnt);
50 int slice = cputoslice(cpu); local
55 LOCAL_HUB_S(PI_RT_PEND_A + PI_COUNT_OFFSET * slice, 0);
/linux-master/arch/powerpc/include/asm/book3s/64/
H A Dmmu-hash.h21 #include <asm/book3s/64/slice.h>
667 /* 4 bits per slice and we have one slice per 1TB */
704 * One bit per slice. We have lower slices which cover 256MB segments
/linux-master/arch/powerpc/mm/book3s64/
H A DMakefile8 obj-y += hash_pgtable.o hash_utils.o hash_tlb.o slb.o slice.o
H A Dslice.c97 static int slice_low_has_vma(struct mm_struct *mm, unsigned long slice) argument
99 return !slice_area_is_free(mm, slice << SLICE_LOW_SHIFT,
103 static int slice_high_has_vma(struct mm_struct *mm, unsigned long slice) argument
105 unsigned long start = slice << SLICE_HIGH_SHIFT;
191 /* Write the new slice psize bits */
255 * Compute which slice addr is part of;
256 * set *boundary_addr to the start or end boundary of that slice
258 * return boolean indicating if the slice is marked as available in the
265 unsigned long slice; local
267 slice
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/linux-master/arch/sparc/include/asm/
H A Dvio.h157 u8 slice; member in struct:vio_disk_desc
/linux-master/block/partitions/
H A Dsysv68.c26 __be16 ios_slccnt; /* Number of entries in slice table */
43 struct slice { struct
44 __be32 nblocks; /* slice size (in blocks) */
45 __be32 blkoff; /* block offset of slice */
56 struct slice *slice; local
76 slices -= 1; /* last slice is the whole disk */
79 slice = (struct slice *)data;
80 for (i = 0; i < slices; i++, slice
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/linux-master/crypto/
H A Ddrbg.c1506 unsigned int slice = 0; local
1510 slice = ((buflen - len) / drbg_max_request_bytes(drbg));
1511 chunk = slice ? drbg_max_request_bytes(drbg) : (buflen - len);
1518 } while (slice > 0 && (len < buflen));
/linux-master/drivers/accel/qaic/
H A Dqaic.h191 /* Number of slice that belongs to this buffer */
193 /* Number of slice that have been transferred by DMA engine */
258 struct list_head slice; member in struct:bo_slice
259 /* Size of this slice in bytes */
261 /* Offset of this slice in buffer */
H A Dqaic_data.c161 struct bo_slice *slice = container_of(kref, struct bo_slice, ref_count); local
163 slice->bo->total_slice_nents -= slice->nents;
164 list_del(&slice->slice);
165 drm_gem_object_put(&slice->bo->base);
166 sg_free_table(slice->sgt);
167 kfree(slice->sgt);
168 kfree(slice->reqs);
169 kfree(slice);
252 encode_reqs(struct qaic_device *qdev, struct bo_slice *slice, struct qaic_attach_slice_entry *req) argument
391 struct bo_slice *slice; local
904 struct bo_slice *slice, *temp; local
1070 copy_exec_reqs(struct qaic_device *qdev, struct bo_slice *slice, u32 dbc_id, u32 head, u32 *ptail) argument
1099 copy_partial_exec_reqs(struct qaic_device *qdev, struct bo_slice *slice, u64 resize, struct dma_bridge_chan *dbc, u32 head, u32 *ptail) argument
1173 struct bo_slice *slice; local
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/linux-master/drivers/block/
H A Dsunvdc.c511 desc->slice = 0xff;
513 desc->slice = 0;
680 desc->slice = 0;
/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dadf_tl_debugfs.h42 #define ADF_TL_SLICE_REG_OFF(slice, reg, qat_gen) \
43 (ADF_TL_DEV_REG_OFF(slice##_slices[0], qat_gen) + \
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_bw.c1022 enum dbuf_slice slice; local
1024 for_each_dbuf_slice(i915, slice) {
1025 if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
1026 old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
1046 enum dbuf_slice slice; local
1052 for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) {
1053 crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rat
1096 enum dbuf_slice slice; local
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H A Dintel_display_power.c1059 enum dbuf_slice slice, bool enable)
1061 i915_reg_t reg = DBUF_CTL_S(slice);
1071 "DBuf slice %d power %s timeout!\n",
1072 slice, str_enable_disable(enable));
1080 enum dbuf_slice slice; local
1098 for_each_dbuf_slice(dev_priv, slice)
1099 gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice));
1119 * Just power up at least 1 slice, we will
1135 enum dbuf_slice slice; local
1058 gen9_dbuf_slice_set(struct drm_i915_private *dev_priv, enum dbuf_slice slice, bool enable) argument
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