Searched refs:rings (Results 1 - 25 of 59) sorted by last modified time

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/linux-master/drivers/net/ethernet/intel/ice/
H A Dice_debugfs.c499 log = &hw->fwlog_ring.rings[hw->fwlog_ring.head];
H A Dice_lib.c38 * ice_vsi_ctrl_all_rx_rings - Start or stop a VSI's Rx rings
40 * @ena: start or stop the Rx rings
42 * First enable/disable all of the Rx rings, flush any remaining writes, and
44 * let all of the register writes complete when enabling/disabling the Rx rings
93 /* txq_map needs to have enough space to track both Tx (stack) rings
94 * and XDP rings; at this point vsi->num_xdp_txq might not be set,
217 * Tx and Rx rings are always equal
1366 * ice_vsi_clear_rings - Deallocates the Tx and Rx rings for VSI
1367 * @vsi: the VSI having rings deallocated
1404 * ice_vsi_alloc_rings - Allocates Tx and Rx rings fo
1994 ice_vsi_stop_tx_rings(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src, u16 rel_vmvf_num, struct ice_tx_ring **rings, u16 count) argument
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H A Dice_base.c270 * To correctly work with many netdevs ring->q_index of Tx rings on switchdev
679 /* set up individual rings */
807 * ice_vsi_map_rings_to_vectors - Map VSI rings to interrupt vectors
810 * This function maps descriptor rings to the queue-specific vectors allotted
812 * and Rx rings to the vector as "efficiently" as possible.
820 /* initially assigning remaining rings count to VSIs num queue value */
829 /* Tx rings mapping to vector */
846 /* Rx rings mapping to vector */
972 * @rings: Tx ring array to be configured
979 ice_vsi_cfg_txqs(struct ice_vsi *vsi, struct ice_tx_ring **rings, u1 argument
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H A Dice_main.c1266 fwlog = &hw->fwlog_ring.rings[hw->fwlog_ring.tail];
1275 /* the rings are full so bump the head to create room */
1439 * __ice_clean_ctrlq - helper function to clean controlq rings
1596 * ice_clean_adminq_subtask - clean the AdminQ rings
1623 * ice_clean_mailboxq_subtask - clean the MailboxQ rings
1645 * ice_clean_sbq_subtask - clean the Sideband Queue rings
2598 * ice_xdp_alloc_setup_rings - Allocate and setup Tx rings for XDP
2599 * @vsi: VSI to setup Tx rings used by XDP
2674 * ice_prepare_xdp_rings - Allocate, configure and setup Tx rings for XDP
2675 * @vsi: VSI to bring up Tx rings use
6649 ice_update_vsi_tx_ring_stats(struct ice_vsi *vsi, struct rtnl_link_stats64 *vsi_stats, struct ice_tx_ring **rings, u16 count) argument
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H A Dice_fwlog.c9 bool ice_fwlog_ring_full(struct ice_fwlog_ring *rings) argument
13 head = rings->head;
14 tail = rings->tail;
16 if (head < tail && (tail - head == (rings->size - 1)))
24 bool ice_fwlog_ring_empty(struct ice_fwlog_ring *rings) argument
26 return rings->head == rings->tail;
34 static int ice_fwlog_alloc_ring_buffs(struct ice_fwlog_ring *rings) argument
39 nr_bytes = rings->size * ICE_AQ_MAX_BUF_LEN;
44 for (i = 0; i < rings
55 ice_fwlog_free_ring_buffs(struct ice_fwlog_ring *rings) argument
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/linux-master/drivers/net/
H A Dtun.c3669 struct ptr_ring **rings; local
3673 rings = kmalloc_array(n, sizeof(*rings), GFP_KERNEL);
3674 if (!rings)
3679 rings[i] = &tfile->tx_ring;
3682 rings[i++] = &tfile->tx_ring;
3684 ret = ptr_ring_resize_multiple(rings, n,
3688 kfree(rings);
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vm.c596 ring = adev->rings[i];
598 /* only compute rings */
H A Daqua_vanjaram.c142 ring = adev->rings[i];
165 struct amdgpu_ring *ring = adev->rings[i];
H A Damdgpu_drv.c639 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
642 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
2697 /* wait for all rings to drain before suspending */
2699 struct amdgpu_ring *ring = adev->rings[i];
H A Damdgpu_job.c112 (*job)->base.sched = &adev->rings[0]->sched;
H A Damdgpu_device.c2627 struct amdgpu_ring *ring = adev->rings[i];
2629 /* No need to setup the GPU scheduler for rings that don't need it */
5049 struct amdgpu_ring *ring = adev->rings[i];
5188 struct amdgpu_ring *ring = adev->rings[i];
5656 struct amdgpu_ring *ring = tmp_adev->rings[i];
5726 struct amdgpu_ring *ring = tmp_adev->rings[i];
6081 struct amdgpu_ring *ring = adev->rings[i];
6223 struct amdgpu_ring *ring = adev->rings[i];
H A Damdgpu.h489 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
955 /* rings */
958 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; member in struct:amdgpu_device
H A Damdgpu_ring.c107 * This is the generic insert_nop function for rings except SDMA
123 * This is the generic pad_ib function for rings except SDMA
229 adev->rings[ring->idx] = ring;
377 (!ring->is_mes_queue && !(ring->adev->rings[ring->idx])))
401 ring->adev->rings[ring->idx] = NULL;
413 * Helper for rings that don't support write and wait in a
H A Damdgpu_ib.c368 * amdgpu_ib_ring_tests - test IBs on the rings
405 struct amdgpu_ring *ring = adev->rings[i];
408 /* KIQ rings don't have an IB test because we never submit IBs
H A Damdgpu_gmc.c589 ring = adev->rings[i];
H A Damdgpu_fence.c468 * Not all asics have all rings, so each asic will only
469 * start the fence driver on the rings it has.
539 * for all possible rings.
543 * Init the fence driver for all possible rings (all asics).
544 * Not all asics have all rings, so each asic will only
545 * start the fence driver on the rings it has using
560 * Interrupts for rings that belong to GFX IP don't need to be restored
592 * for all possible rings.
596 * Tear down the fence driver for all possible rings (all asics).
603 struct amdgpu_ring *ring = adev->rings[
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H A Damdgpu_debugfs.c1679 struct amdgpu_ring *ring = adev->rings[i];
1695 struct amdgpu_ring *ring = adev->rings[i];
1922 ring = adev->rings[val];
2170 struct amdgpu_ring *ring = adev->rings[i];
/linux-master/io_uring/
H A Dio_uring.c186 return ctx->cached_cq_tail - READ_ONCE(ctx->rings->cq.head);
191 return READ_ONCE(ctx->rings->cq.tail) - READ_ONCE(ctx->rings->cq.head);
361 struct io_rings *r = ctx->rings;
578 if (READ_ONCE(ctx->rings->cq_flags) & IORING_CQ_EVENTFD_DISABLED)
653 /* IOPOLL rings only need to wake up if it's also SQPOLL */
712 atomic_andnot(IORING_SQ_CQ_OVERFLOW, &ctx->rings->sq_flags);
806 atomic_or(IORING_SQ_CQ_OVERFLOW, &ctx->rings->sq_flags);
835 struct io_rings *rings = ctx->rings; local
2411 struct io_rings *rings = ctx->rings; local
2592 struct io_rings *rings = ctx->rings; local
2828 struct io_rings *rings; local
3760 struct io_rings *rings; local
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H A Dsqpoll.c175 /* if we're handling multiple rings, cap submit size for fairness */
335 &ctx->rings->sq_flags);
362 &ctx->rings->sq_flags);
375 atomic_or(IORING_SQ_NEED_WAKEUP, &ctx->rings->sq_flags);
H A Dio_uring.h54 int dist = READ_ONCE(ctx->rings->cq.tail) - (int) iowq->cq_tail;
260 smp_store_release(&ctx->rings->cq.tail, ctx->cached_cq_tail);
289 struct io_rings *r = ctx->rings;
296 struct io_rings *rings = ctx->rings; local
300 entries = smp_load_acquire(&rings->sq.tail) - ctx->cached_sq_head;
H A Dfdinfo.c57 struct io_rings *r = ctx->rings;
/linux-master/include/linux/
H A Dio_uring_types.h247 struct io_rings *rings; member in struct:io_ring_ctx::__anon47
432 * the gup'ed pages for the two rings, and the sqes.
/linux-master/drivers/gpu/drm/amd/pm/
H A Damdgpu_dpm.c550 struct amdgpu_ring *ring = adev->rings[i];
/linux-master/drivers/net/wireless/ath/ath10k/
H A Dhtt.h287 struct htt_rx_ring_setup_ring32 rings[]; member in struct:htt_rx_ring_setup_32
292 struct htt_rx_ring_setup_ring64 rings[]; member in struct:htt_rx_ring_setup_64
1322 /* Extra frags on rings 0-3 */
/linux-master/drivers/mailbox/
H A Dbcm-flexrm-mailbox.c9 * manager provides a set of rings which can be used to submit
13 * rings where each mailbox channel represents a separate FlexRM ring.
285 struct flexrm_ring *rings; member in struct:flexrm_mbox
931 ring = &mbox->rings[i];
959 ring = &mbox->rings[i];
1477 struct flexrm_ring *ring = &mbox->rings[desc->msi_index];
1504 /* Get resource for registers and map registers of all rings */
1515 /* Scan and count available rings */
1532 mbox->rings = ring;
1537 ring = &mbox->rings[inde
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