Searched refs:rings (Results 1 - 25 of 59) sorted by path

123

/linux-master/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dflowring.h41 struct brcmf_flowring_ring **rings; member in struct:brcmf_flowring
/linux-master/include/linux/
H A Dskb_array.h201 static inline int skb_array_resize_multiple(struct skb_array **rings, argument
206 return ptr_ring_resize_multiple((struct ptr_ring **)rings,
/linux-master/drivers/block/xen-blkback/
H A Dcommon.h320 /* All rings for this device. */
321 struct xen_blkif_ring *rings; member in struct:xen_blkif
H A Dxenbus.c84 if (!blkif->rings || !blkif->rings[0].irq || !blkif->vbd.bdev_file)
110 ring = &blkif->rings[i];
124 ring = &blkif->rings[i];
134 blkif->rings = kcalloc(blkif->nr_rings, sizeof(struct xen_blkif_ring),
136 if (!blkif->rings)
140 struct xen_blkif_ring *ring = &blkif->rings[r];
274 struct xen_blkif_ring *ring = &blkif->rings[r];
335 * blkif->rings was allocated in connect_ring, so we should free it in
338 kfree(blkif->rings);
[all...]
/linux-master/drivers/crypto/inside-secure/
H A Dsafexcel.c29 MODULE_PARM_DESC(max_rings, "Maximum number of rings to use.");
36 * Map all interfaces/rings to register index 0
51 for (i = 0; i < priv->config.rings; i++) {
510 for (i = 0; i < priv->config.rings; i++) {
558 for (i = 0; i < priv->config.rings; i++) {
600 priv->config.pes, priv->config.rings);
660 /* enable HIA input interface arbiter and rings */
662 GENMASK(priv->config.rings - 1, 0),
720 for (i = 0; i < priv->config.rings; i++) {
746 for (i = 0; i < priv->config.rings;
[all...]
H A Dsafexcel.h677 u32 rings; member in struct:safexcel_config
700 /* command/result rings */
H A Dsafexcel_ring.c74 return (atomic_inc_return(&priv->ring_used) % priv->config.rings);
/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dadf_transport.c267 ring = &bank->rings[ring_num];
338 adf_handle_response(&bank->rings[i]);
404 /* Allocate the rings in the bank */
406 bank->rings = kzalloc_node(size, GFP_KERNEL,
408 if (!bank->rings)
425 ring = &bank->rings[i];
436 "Invalid tx rings mask config\n");
439 tx_ring = &bank->rings[i - hw_data->tx_rx_gap];
456 ring = &bank->rings[i];
460 kfree(bank->rings);
[all...]
H A Dadf_transport_debug.c155 struct adf_etr_ring_data *ring = &bank->rings[ring_id];
H A Dadf_transport_internal.h32 struct adf_etr_ring_data *rings; member in struct:adf_etr_bank_data
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu.h489 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
955 /* rings */
958 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; member in struct:amdgpu_device
H A Damdgpu_debugfs.c1679 struct amdgpu_ring *ring = adev->rings[i];
1695 struct amdgpu_ring *ring = adev->rings[i];
1922 ring = adev->rings[val];
2170 struct amdgpu_ring *ring = adev->rings[i];
H A Damdgpu_device.c2627 struct amdgpu_ring *ring = adev->rings[i];
2629 /* No need to setup the GPU scheduler for rings that don't need it */
5049 struct amdgpu_ring *ring = adev->rings[i];
5188 struct amdgpu_ring *ring = adev->rings[i];
5656 struct amdgpu_ring *ring = tmp_adev->rings[i];
5726 struct amdgpu_ring *ring = tmp_adev->rings[i];
6081 struct amdgpu_ring *ring = adev->rings[i];
6223 struct amdgpu_ring *ring = adev->rings[i];
H A Damdgpu_drv.c639 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
642 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
2697 /* wait for all rings to drain before suspending */
2699 struct amdgpu_ring *ring = adev->rings[i];
H A Damdgpu_fence.c468 * Not all asics have all rings, so each asic will only
469 * start the fence driver on the rings it has.
539 * for all possible rings.
543 * Init the fence driver for all possible rings (all asics).
544 * Not all asics have all rings, so each asic will only
545 * start the fence driver on the rings it has using
560 * Interrupts for rings that belong to GFX IP don't need to be restored
592 * for all possible rings.
596 * Tear down the fence driver for all possible rings (all asics).
603 struct amdgpu_ring *ring = adev->rings[
[all...]
H A Damdgpu_gmc.c589 ring = adev->rings[i];
H A Damdgpu_ib.c368 * amdgpu_ib_ring_tests - test IBs on the rings
405 struct amdgpu_ring *ring = adev->rings[i];
408 /* KIQ rings don't have an IB test because we never submit IBs
H A Damdgpu_job.c112 (*job)->base.sched = &adev->rings[0]->sched;
H A Damdgpu_ring.c107 * This is the generic insert_nop function for rings except SDMA
123 * This is the generic pad_ib function for rings except SDMA
229 adev->rings[ring->idx] = ring;
377 (!ring->is_mes_queue && !(ring->adev->rings[ring->idx])))
401 ring->adev->rings[ring->idx] = NULL;
413 * Helper for rings that don't support write and wait in a
H A Damdgpu_vm.c596 ring = adev->rings[i];
598 /* only compute rings */
H A Daqua_vanjaram.c142 ring = adev->rings[i];
165 struct amdgpu_ring *ring = adev->rings[i];
/linux-master/drivers/gpu/drm/amd/pm/
H A Damdgpu_dpm.c550 struct amdgpu_ring *ring = adev->rings[i];
/linux-master/drivers/gpu/drm/i915/gvt/
H A Dcmd_parser.c432 /* rings that support this cmd: BLT/RCS/VCS/VECS */
433 intel_engine_mask_t rings; member in struct:cmd_info
672 e->info->rings & engine->mask)
3228 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
3230 e->info->devices, e->info->rings);
/linux-master/drivers/i3c/master/mipi-i3c-hci/
H A Ddma.c167 struct hci_rings_data *rings = hci->io_data; local
171 if (!rings)
174 for (i = 0; i < rings->total; i++) {
175 rh = &rings->headers[i];
204 kfree(rings);
210 struct hci_rings_data *rings; local
219 dev_info(&hci->master.dev, "%d DMA rings available\n", nr_rings);
221 dev_err(&hci->master.dev, "number of rings should be <= 8\n");
226 rings = kzalloc(struct_size(rings, header
361 struct hci_rings_data *rings = hci->io_data; local
448 struct hci_rings_data *rings = hci->io_data; local
738 struct hci_rings_data *rings = hci->io_data; local
[all...]
/linux-master/drivers/mailbox/
H A Dbcm-flexrm-mailbox.c9 * manager provides a set of rings which can be used to submit
13 * rings where each mailbox channel represents a separate FlexRM ring.
285 struct flexrm_ring *rings; member in struct:flexrm_mbox
931 ring = &mbox->rings[i];
959 ring = &mbox->rings[i];
1477 struct flexrm_ring *ring = &mbox->rings[desc->msi_index];
1504 /* Get resource for registers and map registers of all rings */
1515 /* Scan and count available rings */
1532 mbox->rings = ring;
1537 ring = &mbox->rings[inde
[all...]

Completed in 679 milliseconds

123