/linux-master/arch/sparc/include/asm/ |
H A D | turbosparc.h | 106 static inline void turbosparc_set_ccreg(unsigned long regval) argument 110 : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS) 116 unsigned long regval; local 119 : "=r" (regval) 121 return regval;
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H A D | pgtsrmmu.h | 112 void srmmu_set_mmureg(unsigned long regval);
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H A D | viking.h | 147 static inline void viking_set_bpreg(unsigned long regval) argument 151 : "r" (regval), "i" (ASI_M_ACTION) 157 unsigned long regval; local 160 : "=r" (regval) 162 return regval;
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/linux-master/drivers/clk/hisilicon/ |
H A D | clk-hisi-phase.c | 31 u32 regval) 36 if (phase->phase_regvals[i] == regval) 45 u32 regval; local 47 regval = readl(phase->reg); 48 regval = (regval & phase->mask) >> phase->shift; 50 return hisi_phase_regval_to_degrees(phase, regval); 69 int regval; local 72 regval = hisi_phase_degrees_to_regval(phase, degrees); 73 if (regval < 30 hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, u32 regval) argument [all...] |
/linux-master/drivers/crypto/ccp/ |
H A D | ccp-debugfs.c | 47 unsigned int regval; local 63 regval = ioread32(ccp->io_regs + CMD5_PSP_CCP_VERSION); 64 oboff += OSCNPRINTF(" Version: %d\n", regval & RI_VERSION_NUM); 66 if (regval & RI_AES_PRESENT) 68 if (regval & RI_3DES_PRESENT) 70 if (regval & RI_SHA_PRESENT) 72 if (regval & RI_RSA_PRESENT) 74 if (regval & RI_ECC_PRESENT) 76 if (regval & RI_ZDE_PRESENT) 78 if (regval 196 unsigned int regval; local [all...] |
/linux-master/drivers/media/dvb-frontends/ |
H A D | stv0900_priv.h | 48 s32 regval;/* binary value */ member in struct:stv000_lookpoint
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/linux-master/drivers/rapidio/switches/ |
H A D | idt_gen2.c | 199 u32 regval; local 205 IDT_RIO_DOMAIN, ®val); 207 *sw_domain = (u8)(regval & 0xff); 215 u32 regval; local 240 rio_read_config_32(rdev, IDT_DEV_CTRL_1, ®val); 242 regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH); 258 rio_read_config_32(rdev, IDT_PORT_OPS(i), ®val); 260 IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW | 280 rio_read_config_32(rdev, IDT_LANE_CTRL(i), ®val); 282 regval | IDT_LANE_CTRL_GENP 324 u32 regval, em_perrdet, em_ltlerrdet; local 373 u32 regval; local [all...] |
H A D | idtcps.c | 105 u32 regval; local 111 IDTCPS_RIO_DOMAIN, ®val); 113 *sw_domain = (u8)(regval & 0xff);
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/linux-master/include/linux/fsl/bestcomm/ |
H A D | bestcomm_priv.h | 254 u16 regval; local 256 regval = in_be16(&bcom_eng->regs->PtdCntrl); 257 out_be16(&bcom_eng->regs->PtdCntrl, regval | 1);
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/linux-master/sound/x86/ |
H A D | intel_hdmi_lpe_audio.h | 124 u32 regval; member in union:aud_cfg 148 u32 regval; member in union:aud_ch_status_0 167 u32 regval; member in union:aud_ch_status_1 182 u32 regval; member in union:aud_hdmi_cts 192 u32 regval; member in union:aud_hdmi_n_enable 204 u32 regval; member in union:aud_buf_config 223 u32 regval; member in union:aud_buf_ch_swap 236 u32 regval; member in union:aud_buf_addr 248 u32 regval; member in union:aud_buf_len 265 u32 regval; member in union:aud_ctrl_st 276 u32 regval; member in union:aud_info_frame1 294 u32 regval; member in union:aud_info_frame2 306 u32 regval; member in union:aud_info_frame3 [all...] |
/linux-master/arch/arm/mach-omap1/ |
H A D | clock.c | 268 u16 regval; local 276 regval = __raw_readw(DSP_CKCTL); 277 regval &= ~(3 << clk->rate_offset); 278 regval |= dsor_exp << clk->rate_offset; 279 __raw_writew(regval, DSP_CKCTL); 301 u16 regval; local 312 regval = omap_readw(ARM_CKCTL); 313 regval &= ~(3 << clk->rate_offset); 314 regval |= dsor_exp << clk->rate_offset; 315 regval [all...] |
/linux-master/arch/arm64/kvm/hyp/nvhe/ |
H A D | sys_regs.c | 254 p->regval = 0; 287 * If access is allowed, set the regval to the protected VM's view of the 300 p->regval = read_id_reg(vcpu, r); 310 p->regval = ICC_SRE_EL1_DIB | ICC_SRE_EL1_DFB | ICC_SRE_EL1_SRE; 482 params.regval = vcpu_get_reg(vcpu, Rt); 501 vcpu_set_reg(vcpu, Rt, params.regval);
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/linux-master/arch/arm64/kvm/ |
H A D | sys_regs.c | 313 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 315 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 397 val |= (p->regval & (mask >> shift)) << shift; 414 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 465 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 477 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 533 if (p->regval & OSLAR_EL1_OSLK) 547 p->regval = __vcpu_sys_reg(vcpu, r->reg); 572 p->regval = read_sysreg(dbgauthstatus_el1); 612 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); [all...] |
H A D | sys_regs.h | 26 u64 regval; member in struct:sys_reg_params 131 p->regval = 0;
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/linux-master/arch/mips/loongson2ef/lemote-2f/ |
H A D | clock.c | 37 int regval; local 45 regval = readl(LOONGSON_CHIPCFG); 46 regval = (regval & ~0x7) | (pos->driver_data - 1); 47 writel(regval, LOONGSON_CHIPCFG);
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/linux-master/arch/sparc/kernel/ |
H A D | auxio_32.c | 87 unsigned char regval; local 94 regval = sbus_readb(auxio_register); 95 sbus_writeb(((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN4M,
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H A D | auxio_64.c | 36 u8 regval, newval; local 40 regval = (ebus ? 43 newval = regval | bits_on;
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/linux-master/drivers/ata/ |
H A D | sata_nv.c | 1850 u8 regval; local 1853 pci_read_config_byte(pdev, 0x7f, ®val); 1854 regval &= ~(1 << 7); 1855 pci_write_config_byte(pdev, 0x7f, regval); 2363 u8 regval; local 2365 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); 2366 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; 2367 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); 2400 u8 regval; local 2402 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); 2440 u8 regval; local [all...] |
/linux-master/drivers/bus/mhi/ep/ |
H A D | mmio.c | 25 u32 regval; local 27 regval = mhi_ep_mmio_read(mhi_cntrl, offset); 28 regval &= ~mask; 29 regval |= (val << __ffs(mask)) & mask; 30 mhi_ep_mmio_write(mhi_cntrl, offset, regval); 35 u32 regval; local 37 regval = mhi_ep_mmio_read(dev, offset); 38 regval &= mask; 39 regval >>= __ffs(mask); 41 return regval; 47 u32 regval; local 185 u32 regval; local 197 u32 regval; local 209 u32 regval; local 223 u32 regval; local 254 u32 regval; local 268 u32 regval; local [all...] |
/linux-master/drivers/clk/ |
H A D | clk-apple-nco.c | 144 static unsigned int applnco_div_translate_inv(struct applnco_tables *tbl, u32 regval) argument 148 coarse = tbl->inv[FIELD_GET(DIV_COARSE, regval)] + COARSE_DIV_OFFSET; 149 fine = FIELD_GET(DIV_FINE, regval);
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H A D | clk-bm1880.c | 474 static unsigned long bm1880_pll_rate_calc(u32 regval, unsigned long parent_rate) argument 480 fbdiv = (regval >> 16) & 0xfff; 481 refdiv = regval & 0x1f; 482 postdiv1 = (regval >> 8) & 0x7; 483 postdiv2 = (regval >> 12) & 0x7; 497 u32 regval; local 499 regval = readl(pll_hw->base + pll_hw->pll.reg); 500 rate = bm1880_pll_rate_calc(regval, parent_rate);
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/linux-master/drivers/clk/mediatek/ |
H A D | clk-fhctl.c | 163 unsigned int regval; local 165 regval = readl(pll->pd_addr) >> pll->data->pd_shift; 166 regval &= POSTDIV_MASK; 168 return BIT(regval); 173 unsigned int regval; local 175 regval = readl(pll->pd_addr); 176 regval &= ~(POSTDIV_MASK << pll->data->pd_shift); 177 regval |= (ffs(postdiv) - 1) << pll->data->pd_shift; 178 writel(regval, pll->pd_addr);
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/linux-master/drivers/clk/qcom/ |
H A D | clk-hfpll.c | 36 u32 regval = hd->user_val; local 43 regval |= hd->user_vco_mask; 44 regmap_write(regmap, hd->user_reg, regval);
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H A D | clk-krait.c | 26 u32 regval; local 30 regval = krait_get_l2_indirect_reg(mux->offset); 34 regval |= SECCLKAGD; 35 krait_set_l2_indirect_reg(mux->offset, regval); 38 regval &= ~(mux->mask << mux->shift); 39 regval |= (sel & mux->mask) << mux->shift; 41 regval &= ~(mux->mask << (mux->shift + LPL_SHIFT)); 42 regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT); 44 krait_set_l2_indirect_reg(mux->offset, regval); 48 regval [all...] |
/linux-master/drivers/clk/xilinx/ |
H A D | clk-xlnx-clock-wizard.c | 235 u32 value, regh, edged, p5en, p5fedge, regval, regval1; local 256 regval = regh | regh << WZRD_CLKFBOUT_H_SHIFT; 257 writel(regval, div_addr + 4); 433 u32 regh, edged, p5en, p5fedge, value2, m, regval, regval1, value; local 488 regval = regh | regh << WZRD_CLKFBOUT_H_SHIFT; 489 writel(regval, divider->base + WZRD_CLK_CFG_REG(1,
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