mhi/ep/mmio.c

25 	u32 regval;
27 	regval = mhi_ep_mmio_read(mhi_cntrl, offset);
28 	regval &= ~mask;
29 	regval |= (val << __ffs(mask)) & mask;
30 	mhi_ep_mmio_write(mhi_cntrl, offset, regval);
35 	u32 regval;
37 	regval = mhi_ep_mmio_read(dev, offset);
38 	regval &= mask;
39 	regval >>= __ffs(mask);
41 	return regval;
47 	u32 regval;
49 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_MHICTRL);
50 	*state = FIELD_GET(MHICTRL_MHISTATE_MASK, regval);
51 	*mhi_reset = !!FIELD_GET(MHICTRL_RESET_MASK, regval);
185 	u32 regval;
187 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_CCABAP_HIGHER);
188 	mhi_cntrl->ch_ctx_host_pa = regval;
191 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_CCABAP_LOWER);
192 	mhi_cntrl->ch_ctx_host_pa |= regval;
197 	u32 regval;
199 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_ECABAP_HIGHER);
200 	mhi_cntrl->ev_ctx_host_pa = regval;
203 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_ECABAP_LOWER);
204 	mhi_cntrl->ev_ctx_host_pa |= regval;
209 	u32 regval;
211 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_CRCBAP_HIGHER);
212 	mhi_cntrl->cmd_ctx_host_pa = regval;
215 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_CRCBAP_LOWER);
216 	mhi_cntrl->cmd_ctx_host_pa |= regval;
223 	u32 regval;
225 	regval = mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_h);
226 	db_offset = regval;
229 	regval = mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_l);
230 	db_offset |= regval;
254 	u32 regval;
259 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_MHICFG);
260 	mhi_cntrl->event_rings = FIELD_GET(MHICFG_NER_MASK, regval);
261 	mhi_cntrl->hw_event_rings = FIELD_GET(MHICFG_NHWER_MASK, regval);
268 	u32 regval;
270 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_MHICFG);
271 	mhi_cntrl->event_rings = FIELD_GET(MHICFG_NER_MASK, regval);
272 	mhi_cntrl->hw_event_rings = FIELD_GET(MHICFG_NHWER_MASK, regval);