/linux-master/include/linux/ |
H A D | regmap.h | 1489 * @reg_offset: Offset of the status/mask register within the bank 1494 unsigned int reg_offset; member in struct:regmap_irq 1500 [_irq] = { .reg_offset = (_off), .mask = (_mask) } 1505 .reg_offset = (_id) / (_reg_bits), \
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/linux-master/drivers/net/ethernet/broadcom/genet/ |
H A D | bcmgenet.c | 978 u16 reg_offset; member in struct:bcmgenet_stats 1005 .reg_offset = offset, \ 1227 val = bcmgenet_umac_readl(priv, s->reg_offset); 1231 s->reg_offset); 1234 s->reg_offset);
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/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm.c | 1723 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 1724 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 1725 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
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/linux-master/drivers/pinctrl/intel/ |
H A D | pinctrl-baytrail.c | 564 u32 reg_offset; local 572 reg_offset = (offset / 32) * 4; 575 reg_offset = 0; 578 reg_offset = comm->pad_map[offset] * 16; 582 return comm->pad_regs + reg_offset + reg;
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | vpe_v6_1.c | 67 base = vpe->ring.adev->reg_offset[VPE_HWIP][inst][0];
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H A D | sdma_v5_2.c | 74 base = adev->reg_offset[GC_HWIP][0][1]; 79 base = adev->reg_offset[GC_HWIP][0][0]; 83 base = adev->reg_offset[GC_HWIP][0][2]; 1382 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); local 1385 sdma_cntl = RREG32(reg_offset); 1388 WREG32(reg_offset, sdma_cntl);
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H A D | sdma_v4_4_2.c | 66 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset);
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H A D | gfx_v9_0.c | 4927 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 6637 if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset ||
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H A D | gfx_v10_0.c | 7863 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7871 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7880 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 7976 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
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H A D | amdgpu_mes.c | 810 op_input.read_reg.reg_offset = reg; 835 op_input.write_reg.reg_offset = reg;
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H A D | soc21.c | 279 u32 sh_num, u32 reg_offset) 287 val = RREG32(reg_offset); 297 u32 sh_num, u32 reg_offset) 300 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); 302 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) 304 return RREG32(reg_offset); 309 u32 sh_num, u32 reg_offset, u32 *value) 317 if (!adev->reg_offset[en->hwip][en->inst]) 319 else if (reg_offset != (adev->reg_offset[e 278 soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset) argument 295 soc21_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) argument 308 soc21_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) argument [all...] |
H A D | umsch_mm_v4_0.c | 290 memcpy(set_hw_resources.mmhub_base, adev->reg_offset[MMHUB_HWIP][0], 295 memcpy(set_hw_resources.osssys_base, adev->reg_offset[OSSSYS_HWIP][0],
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H A D | mes_v11_0.c | 319 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 324 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 401 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 403 adev->reg_offset[MMHUB_HWIP][0][i]; 405 adev->reg_offset[OSSSYS_HWIP][0][i];
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H A D | amdgpu_mes.h | 280 uint32_t reg_offset; member in struct:mes_misc_op_input::__anon12::__anon13 285 uint32_t reg_offset; member in struct:mes_misc_op_input::__anon12::__anon14
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H A D | amdgpu_discovery.c | 1344 * so that we don't need to convert them when accessing adev->reg_offset. 1348 * and only store lower 32bit ip base in reg_offset[]. 1351 * By this way reg_offset[] and related helpers can 1368 adev->reg_offset[hw_ip][ip->instance_number] =
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H A D | amdgpu.h | 511 uint32_t reg_offset; member in struct:amdgpu_allowed_register_entry 578 u32 sh_num, u32 reg_offset, u32 *value); 670 u32 reg_offset; member in struct:amdgpu_mmio_remap 1064 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; member in struct:amdgpu_device
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H A D | amdgpu_umsch_mm.h | 184 uint32_t reg_offset = adev->reg_offset[VCN_HWIP][0][reg##_BASE_IDX] + reg; \ 186 *adev->umsch_mm.cmd_buf_curr_ptr++ = (reg_offset << 2); \ 189 WREG32(reg_offset, value); \
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/linux-master/drivers/gpio/ |
H A D | gpio-tangier.c | 67 u8 reg_offset = offset / 32; local 69 return priv->reg_base + reg + reg_offset * 4; 76 u8 reg_offset = offset / 32; local 80 return priv->reg_base + reg + reg_offset * 4;
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/linux-master/drivers/tty/serial/ |
H A D | mxs-auart.c | 360 const u16 *reg_offset; member in struct:vendor_data 407 .reg_offset = mxs_asm9260_offsets, 411 .reg_offset = mxs_stmp37xx_offsets, 476 return uap->vendor->reg_offset[reg];
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H A D | amba-pl011.c | 104 const u16 *reg_offset; member in struct:vendor_data 127 .reg_offset = pl011_std_offsets, 142 .reg_offset = pl011_std_offsets, 157 .reg_offset = pl011_std_offsets, 205 .reg_offset = pl011_st_offsets, 256 const u16 *reg_offset; member in struct:uart_amba_port 282 return uap->reg_offset[reg]; 2798 uap->reg_offset = vendor->reg_offset; 2918 uap->reg_offset [all...] |
/linux-master/drivers/platform/x86/amd/pmf/ |
H A D | core.c | 160 static inline u32 amd_pmf_reg_read(struct amd_pmf_dev *dev, int reg_offset) argument 162 return ioread32(dev->regbase + reg_offset); 165 static inline void amd_pmf_reg_write(struct amd_pmf_dev *dev, int reg_offset, u32 val) argument 167 iowrite32(val, dev->regbase + reg_offset);
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/linux-master/drivers/gpu/drm/amd/amdkfd/ |
H A D | kfd_device_queue_manager.c | 1682 uint32_t reg_offset = 0; local 1693 grace_period, ®_offset,
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/linux-master/sound/soc/sof/amd/ |
H A D | acp.c | 325 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; local 329 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i); 334 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; local 338 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]);
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H A D | acp.h | 168 unsigned int reg_offset[8]; member in struct:scratch_reg_conf 183 unsigned int reg_offset; member in struct:acp_dsp_stream
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/linux-master/drivers/net/ethernet/renesas/ |
H A D | sh_eth.c | 350 u16 offset = mdp->reg_offset[enum_index]; 361 u16 offset = mdp->reg_offset[enum_index]; 378 return mdp->reg_offset[enum_index]; 2084 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ 2208 mdp->reg_offset[TSU_ADRH0] + 2727 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); local 2731 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2732 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr); 2754 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); local 2762 ret = sh_eth_tsu_write_entry(ndev, reg_offset 2771 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); local 2845 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); local 3151 const u16 *reg_offset = NULL; local [all...] |