/linux-master/sound/soc/meson/ |
H A D | axg-tdm-interface.c | 107 if (!iface->mclk) { 110 ret = clk_set_rate(iface->mclk, freq); 125 if (!iface->mclk) { 126 dev_err(dai->dev, "cpu clock master: mclk missing\n"); 278 /* If no specific mclk is requested, default to bit clock * 2 */ 279 clk_set_rate(iface->mclk, 2 * srate); 281 /* Check if we can actually get the bit clock from mclk */ 284 "can't derive sclk %lu from mclk %lu\n", 483 ret = clk_prepare_enable(iface->mclk); 488 clk_disable_unprepare(iface->mclk); [all...] |
H A D | axg-tdm.h | 29 struct clk *mclk; member in struct:axg_tdm_iface
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H A D | axg-tdm-formatter.c | 405 ret = clk_prepare_enable(ts->iface->mclk); 429 clk_disable_unprepare(ts->iface->mclk);
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/linux-master/sound/soc/intel/boards/ |
H A D | bytcr_rt5640.c | 103 struct clk *mclk; member in struct:byt_rt5640_private 280 ret = clk_prepare_enable(priv->mclk); 296 clk_disable_unprepare(priv->mclk); 1370 ret = clk_prepare_enable(priv->mclk); 1372 clk_disable_unprepare(priv->mclk); 1375 ret = clk_set_rate(priv->mclk, 25000000); 1377 ret = clk_set_rate(priv->mclk, 19200000); 1802 priv->mclk = devm_clk_get_optional(dev, "pmc_plt_clk_3"); 1803 if (IS_ERR(priv->mclk)) { 1804 ret_val = dev_err_probe(dev, PTR_ERR(priv->mclk), [all...] |
H A D | sof_rt5682.c | 195 dev_err(rtd->dev, "invalid mclk freq %d\n", mclk_freq); 199 /* need to enable ASRC function for 24MHz mclk rate */ 244 ret = clk_prepare_enable(ctx->rt5682.mclk); 246 clk_disable_unprepare(ctx->rt5682.mclk); 248 ret = clk_set_rate(ctx->rt5682.mclk, 19200000); 307 ret = clk_prepare_enable(ctx->rt5682.mclk); 331 /* get the tplg configured mclk. */ 334 dev_err(rtd->dev, "invalid mclk freq %d\n", pll_in); 679 ctx->rt5682.mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3"); 680 if (IS_ERR(ctx->rt5682.mclk)) { [all...] |
H A D | sof_board_helpers.h | 39 * @mclk: mclk clock data 43 struct clk *mclk; member in struct:sof_rt5682_private
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/linux-master/sound/soc/codecs/ |
H A D | da7219-aad.c | 125 if (da7219->mclk) { 126 ret = clk_prepare_enable(da7219->mclk); 128 dev_err(component->dev, "Failed to enable mclk - %d\n", ret); 320 if (da7219->mclk) 321 clk_disable_unprepare(da7219->mclk);
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H A D | es8326.c | 22 struct clk *mclk; member in struct:es8326_priv 351 u32 mclk; member in struct:_coeff_div 362 /* codec hifi mclk clock divider coefficients */ 460 static inline int get_coeff(int mclk, int rate, int array, argument 466 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk) 648 ret = clk_prepare_enable(es8326->mclk); 670 clk_disable_unprepare(es8326->mclk); 1226 es8326->mclk = devm_clk_get_optional(&i2c->dev, "mclk"); [all...] |
H A D | cs42l43.c | 1442 ret = clk_prepare_enable(priv->mclk); 1455 clk_disable_unprepare(priv->mclk); 2319 priv->mclk = clk_get_optional(cs42l43->dev, "mclk"); 2320 if (IS_ERR(priv->mclk)) { 2321 ret = PTR_ERR(priv->mclk); 2322 dev_err_probe(priv->dev, ret, "Failed to get mclk\n"); 2339 clk_put(priv->mclk); 2350 clk_put(priv->mclk);
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H A D | tlv320adc3xxx.c | 319 struct clk *mclk; member in struct:adc3xxx 469 u32 mclk; member in struct:adc3xxx_rate_divs 488 /* mclk, rate, p, r, j, d, nadc, madc, aosr */ 515 static int adc3xxx_get_divs(struct device *dev, int mclk, int rate, int pll_mode) argument 519 dev_dbg(dev, "mclk = %d, rate = %d, clock mode %u\n", 520 mclk, rate, pll_mode); 532 if (mode->rate == rate && mode->mclk == mclk) 537 mclk, rate); 1368 adc3xxx->mclk [all...] |
H A D | rt5682s.c | 2650 * Whether the wclk's parent clk (mclk) exists or not, please ensure 2654 * It will set the codec anyway by assuming mclk is 48MHz. 2659 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", 2800 if (rt5682s->mclk) { 2802 .fw_name = "mclk", 2849 rt5682s->mclk = devm_clk_get_optional(component->dev, "mclk"); 2850 if (IS_ERR(rt5682s->mclk)) 2851 return PTR_ERR(rt5682s->mclk); [all...] |
H A D | rt5682-i2c.c | 274 rt5682->mclk = devm_clk_get_optional(&i2c->dev, "mclk"); 275 if (IS_ERR(rt5682->mclk)) 276 return PTR_ERR(rt5682->mclk);
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H A D | rt5659.c | 3438 ret = clk_set_rate(rt5659->mclk, freq); 3635 ret = clk_prepare_enable(rt5659->mclk); 3653 clk_disable_unprepare(rt5659->mclk); 4143 rt5659->mclk = devm_clk_get_optional(&i2c->dev, "mclk"); 4144 if (IS_ERR(rt5659->mclk)) 4145 return PTR_ERR(rt5659->mclk);
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/linux-master/drivers/gpu/drm/amd/pm/ |
H A D | amdgpu_pm.c | 255 * to the lowest level. profile_min_mclk forces the mclk to the lowest level. 256 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels. 659 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE 665 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at 690 * - a list of valid ranges for sclk, mclk, voltage curve points 718 * "m 1 800" will update maximum mclk to be 800Mhz. For core 1004 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie" 2316 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */ 3194 uint32_t mclk; local 3199 (void *)&mclk); [all...] |
/linux-master/drivers/gpu/drm/radeon/ |
H A D | radeon_atombios.c | 2141 rdev->pm.power_state[state_index].clock_info[0].mclk = 2146 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2176 rdev->pm.power_state[state_index].clock_info[0].mclk = 2181 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2212 rdev->pm.power_state[state_index].clock_info[0].mclk = 2217 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2450 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2460 /* patch the table values with the default sclk/mclk from firmware info */ 2462 rdev->pm.power_state[state_index].clock_info[j].mclk = 2481 u32 sclk, mclk; local [all...] |
/linux-master/sound/soc/rockchip/ |
H A D | rockchip_i2s_tdm.c | 100 * This function attempts to enable all mclk clocks, but cleans up after 658 struct clk *mclk = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? local 661 err = clk_set_rate(mclk, DEFAULT_MCLK_FS * params_rate(params)); 665 mclk_rate = clk_get_rate(mclk);
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/linux-master/drivers/iio/adc/ |
H A D | ad4130.c | 265 struct clk *mclk; member in struct:ad4130_state 1629 st->mclk = devm_clk_get_optional(dev, "mclk"); 1630 if (IS_ERR(st->mclk)) 1631 return dev_err_probe(dev, PTR_ERR(st->mclk), 1632 "Failed to get mclk\n"); 1659 if (st->mclk && ext_clk_freq == AD4130_MCLK_FREQ_153_6KHZ) 1661 else if (st->mclk) 1836 ret = clk_set_rate(st->mclk, rate); 1840 ret = clk_prepare_enable(st->mclk); [all...] |
/linux-master/drivers/ufs/host/ |
H A D | ufs-mediatek.h | 175 struct ufs_mtk_clk mclk; member in struct:ufs_mtk_host
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H A D | ufs-mediatek.c | 780 struct ufs_mtk_clk *mclk = &host->mclk; local 790 host->mclk.ufs_sel_clki = clki; 792 host->mclk.ufs_sel_max_clki = clki; 796 host->mclk.ufs_sel_min_clki = clki; 802 if (!mclk->ufs_sel_clki || !mclk->ufs_sel_max_clki || 803 !mclk->ufs_sel_min_clki) { 1534 struct ufs_mtk_clk *mclk = &host->mclk; local [all...] |
/linux-master/drivers/media/platform/st/stm32/ |
H A D | stm32-dcmi.c | 156 struct clk *mclk; member in struct:stm32_dcmi 1897 struct clk *mclk; local 1948 mclk = devm_clk_get(&pdev->dev, "mclk"); 1949 if (IS_ERR(mclk)) 1950 return dev_err_probe(&pdev->dev, PTR_ERR(mclk), 1951 "Unable to get mclk\n"); 1970 dcmi->mclk = mclk; 2105 clk_disable_unprepare(dcmi->mclk); [all...] |
/linux-master/drivers/media/platform/samsung/exynos4-is/ |
H A D | fimc-is.c | 627 soe->mclk = 0;
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/linux-master/drivers/media/platform/intel/ |
H A D | pxa_camera.c | 675 unsigned long mclk; member in struct:pxa_camera_dev 1078 unsigned long mclk = pcdev->mclk; local 1085 /* mclk <= ciclk / 4 (27.4.2) */ 1086 if (mclk > lcdclk / 4) { 1087 mclk = lcdclk / 4; 1089 "Limiting master clock to %lu\n", mclk); 1092 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ 1093 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) [all...] |
/linux-master/drivers/media/pci/ttpci/ |
H A D | budget-av.c | 570 .mclk = 88000000UL, 583 .mclk = 88000000UL, 595 .mclk = 88000000UL, 869 .mclk = 88000000UL,
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/linux-master/drivers/media/i2c/ |
H A D | s5k5baf.c | 36 #define S5K5BAF_CLK_NAME "mclk" 579 unsigned long mclk = state->mclk_frequency / 1000; local 590 s5k5baf_write_seq(state, REG_I_INCLK_FREQ_L, mclk & 0xffff, mclk >> 16);
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/linux-master/drivers/media/dvb-frontends/ |
H A D | stv0367.c | 45 u32 mclk; member in struct:stv0367cab_state 2297 cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal); 2506 cab_state->mclk); 2569 cab_state->mclk, 2589 p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk); 2967 state->cab_state->mclk = stv0367cab_get_mclk(&state->fe,
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