1185573Srwatson// SPDX-License-Identifier: GPL-2.0-or-later 2189279Srwatson/* 3155131Srwatson * V4L2 Driver for PXA camera host 4155131Srwatson * 5155131Srwatson * Copyright (C) 2006, Sascha Hauer, Pengutronix 6155131Srwatson * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> 7155131Srwatson * Copyright (C) 2016, Robert Jarzmik <robert.jarzmik@free.fr> 8155131Srwatson */ 9155131Srwatson 10155131Srwatson#include <linux/init.h> 11155131Srwatson#include <linux/module.h> 12155131Srwatson#include <linux/io.h> 13155131Srwatson#include <linux/delay.h> 14155131Srwatson#include <linux/device.h> 15155131Srwatson#include <linux/dma-mapping.h> 16155131Srwatson#include <linux/err.h> 17185573Srwatson#include <linux/errno.h> 18155131Srwatson#include <linux/fs.h> 19155131Srwatson#include <linux/interrupt.h> 20155131Srwatson#include <linux/kernel.h> 21155131Srwatson#include <linux/mm.h> 22155131Srwatson#include <linux/moduleparam.h> 23155131Srwatson#include <linux/of.h> 24155131Srwatson#include <linux/of_graph.h> 25155131Srwatson#include <linux/time.h> 26155131Srwatson#include <linux/platform_device.h> 27155131Srwatson#include <linux/clk.h> 28155131Srwatson#include <linux/sched.h> 29155131Srwatson#include <linux/slab.h> 30155131Srwatson#include <linux/dmaengine.h> 31155131Srwatson#include <linux/dma/pxa-dma.h> 32155131Srwatson 33155131Srwatson#include <media/v4l2-async.h> 34155131Srwatson#include <media/v4l2-common.h> 35156283Srwatson#include <media/v4l2-ctrls.h> 36156283Srwatson#include <media/v4l2-device.h> 37243750Srwatson#include <media/v4l2-event.h> 38243750Srwatson#include <media/v4l2-ioctl.h> 39243750Srwatson#include <media/v4l2-fwnode.h> 40243750Srwatson 41243750Srwatson#include <media/videobuf2-dma-sg.h> 42156283Srwatson 43243750Srwatson#include <linux/videodev2.h> 44243750Srwatson 45156283Srwatson#include <linux/platform_data/media/camera-pxa.h> 46243750Srwatson 47243750Srwatson#define PXA_CAM_VERSION "0.0.6" 48155131Srwatson#define PXA_CAM_DRV_NAME "pxa27x-camera" 49243750Srwatson 50243750Srwatson#define DEFAULT_WIDTH 640 51243750Srwatson#define DEFAULT_HEIGHT 480 52243750Srwatson 53243750Srwatson/* Camera Interface */ 54156283Srwatson#define CICR0 0x0000 55156283Srwatson#define CICR1 0x0004 56156283Srwatson#define CICR2 0x0008 57156283Srwatson#define CICR3 0x000C 58156283Srwatson#define CICR4 0x0010 59156283Srwatson#define CISR 0x0014 60155131Srwatson#define CIFR 0x0018 61155131Srwatson#define CITOR 0x001C 62155131Srwatson#define CIBR0 0x0028 63155131Srwatson#define CIBR1 0x0030 64155131Srwatson#define CIBR2 0x0038 65155131Srwatson 66155131Srwatson#define CICR0_DMAEN (1UL << 31) /* DMA request enable */ 67155131Srwatson#define CICR0_PAR_EN (1 << 30) /* Parity enable */ 68155131Srwatson#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ 69155131Srwatson#define CICR0_ENB (1 << 28) /* Camera interface enable */ 70155131Srwatson#define CICR0_DIS (1 << 27) /* Camera interface disable */ 71155131Srwatson#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ 72155131Srwatson#define CICR0_TOM (1 << 9) /* Time-out mask */ 73155131Srwatson#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ 74155131Srwatson#define CICR0_FEM (1 << 7) /* FIFO-empty mask */ 75155131Srwatson#define CICR0_EOLM (1 << 6) /* End-of-line mask */ 76155131Srwatson#define CICR0_PERRM (1 << 5) /* Parity-error mask */ 77155131Srwatson#define CICR0_QDM (1 << 4) /* Quick-disable mask */ 78155131Srwatson#define CICR0_CDM (1 << 3) /* Disable-done mask */ 79155131Srwatson#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ 80155131Srwatson#define CICR0_EOFM (1 << 1) /* End-of-frame mask */ 81155131Srwatson#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ 82155131Srwatson 83243750Srwatson#define CICR1_TBIT (1UL << 31) /* Transparency bit */ 84155131Srwatson#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ 85155131Srwatson#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ 86155131Srwatson#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ 87243750Srwatson#define CICR1_RGB_F (1 << 11) /* RGB format */ 88155131Srwatson#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ 89155131Srwatson#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ 90185573Srwatson#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ 91155131Srwatson#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ 92155131Srwatson#define CICR1_DW (0x7 << 0) /* Data width mask */ 93155131Srwatson 94155131Srwatson#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock 95243750Srwatson wait count mask */ 96243750Srwatson#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock 97243750Srwatson wait count mask */ 98243750Srwatson#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ 99243750Srwatson#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock 100243750Srwatson wait count mask */ 101243750Srwatson#define CICR2_FSW (0x7 << 0) /* Frame stabilization 102243750Srwatson wait count mask */ 103243750Srwatson 104243750Srwatson#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock 105243750Srwatson wait count mask */ 106243750Srwatson#define CICR3_EFW (0xff << 16) /* End-of-frame line clock 107243750Srwatson wait count mask */ 108243750Srwatson#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ 109243750Srwatson#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock 110243750Srwatson wait count mask */ 111243750Srwatson#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ 112243750Srwatson 113243750Srwatson#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ 114243750Srwatson#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ 115243750Srwatson#define CICR4_PCP (1 << 22) /* Pixel clock polarity */ 116243750Srwatson#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ 117243750Srwatson#define CICR4_VSP (1 << 20) /* Vertical sync polarity */ 118243750Srwatson#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ 119243750Srwatson#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ 120243750Srwatson#define CICR4_DIV (0xff << 0) /* Clock divisor mask */ 121243750Srwatson 122243750Srwatson#define CISR_FTO (1 << 15) /* FIFO time-out */ 123243750Srwatson#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ 124243750Srwatson#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ 125243750Srwatson#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ 126243750Srwatson#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ 127243750Srwatson#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ 128243750Srwatson#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ 129243750Srwatson#define CISR_EOL (1 << 8) /* End of line */ 130243750Srwatson#define CISR_PAR_ERR (1 << 7) /* Parity error */ 131243750Srwatson#define CISR_CQD (1 << 6) /* Camera interface quick disable */ 132243750Srwatson#define CISR_CDD (1 << 5) /* Camera interface disable done */ 133243750Srwatson#define CISR_SOF (1 << 4) /* Start of frame */ 134243750Srwatson#define CISR_EOF (1 << 3) /* End of frame */ 135243750Srwatson#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ 136243750Srwatson#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ 137243750Srwatson#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ 138243750Srwatson 139243750Srwatson#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ 140243750Srwatson#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ 141243750Srwatson#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ 142243750Srwatson#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ 143243750Srwatson#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ 144243750Srwatson#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ 145243750Srwatson#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ 146243750Srwatson#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ 147243750Srwatson 148155131Srwatson#define CICR0_SIM_MP (0 << 24) 149155131Srwatson#define CICR0_SIM_SP (1 << 24) 150155131Srwatson#define CICR0_SIM_MS (2 << 24) 151155131Srwatson#define CICR0_SIM_EP (3 << 24) 152155131Srwatson#define CICR0_SIM_ES (4 << 24) 153155131Srwatson 154185573Srwatson#define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ 155155131Srwatson#define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ 156155131Srwatson#define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */ 157155131Srwatson#define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */ 158155131Srwatson#define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */ 159155131Srwatson 160155131Srwatson#define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ 161155131Srwatson#define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ 162155131Srwatson#define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ 163155131Srwatson#define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ 164155131Srwatson#define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ 165155131Srwatson 166155131Srwatson#define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ 167155131Srwatson#define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ 168155131Srwatson#define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ 169155131Srwatson#define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ 170155131Srwatson 171155131Srwatson#define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ 172155131Srwatson CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ 173155131Srwatson CICR0_EOFM | CICR0_FOM) 174155131Srwatson 175155131Srwatson#define sensor_call(cam, o, f, args...) \ 176155131Srwatson v4l2_subdev_call(cam->sensor, o, f, ##args) 177155131Srwatson 178185573Srwatson/* 179155131Srwatson * Format handling 180155131Srwatson */ 181155131Srwatson 182155131Srwatson/** 183155131Srwatson * enum pxa_mbus_packing - data packing types on the media-bus 184155131Srwatson * @PXA_MBUS_PACKING_NONE: no packing, bit-for-bit transfer to RAM, one 185155131Srwatson * sample represents one pixel 186155131Srwatson * @PXA_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the 187155131Srwatson * possibly incomplete byte high bits are padding 188155131Srwatson * @PXA_MBUS_PACKING_EXTEND16: sample width (e.g., 10 bits) has to be extended 189155131Srwatson * to 16 bits 190155131Srwatson */ 191155131Srwatsonenum pxa_mbus_packing { 192155131Srwatson PXA_MBUS_PACKING_NONE, 193155131Srwatson PXA_MBUS_PACKING_2X8_PADHI, 194155131Srwatson PXA_MBUS_PACKING_EXTEND16, 195155131Srwatson}; 196155131Srwatson 197155131Srwatson/** 198155131Srwatson * enum pxa_mbus_order - sample order on the media bus 199155131Srwatson * @PXA_MBUS_ORDER_LE: least significant sample first 200155131Srwatson * @PXA_MBUS_ORDER_BE: most significant sample first 201155131Srwatson */ 202185573Srwatsonenum pxa_mbus_order { 203155131Srwatson PXA_MBUS_ORDER_LE, 204155131Srwatson PXA_MBUS_ORDER_BE, 205155131Srwatson}; 206155131Srwatson 207155131Srwatson/** 208155131Srwatson * enum pxa_mbus_layout - planes layout in memory 209155131Srwatson * @PXA_MBUS_LAYOUT_PACKED: color components packed 210155131Srwatson * @PXA_MBUS_LAYOUT_PLANAR_2Y_U_V: YUV components stored in 3 planes (4:2:2) 211155131Srwatson * @PXA_MBUS_LAYOUT_PLANAR_2Y_C: YUV components stored in a luma and a 212155131Srwatson * chroma plane (C plane is half the size 213155131Srwatson * of Y plane) 214155131Srwatson * @PXA_MBUS_LAYOUT_PLANAR_Y_C: YUV components stored in a luma and a 215155131Srwatson * chroma plane (C plane is the same size 216155131Srwatson * as Y plane) 217155131Srwatson */ 218155131Srwatsonenum pxa_mbus_layout { 219155131Srwatson PXA_MBUS_LAYOUT_PACKED = 0, 220155131Srwatson PXA_MBUS_LAYOUT_PLANAR_2Y_U_V, 221155131Srwatson PXA_MBUS_LAYOUT_PLANAR_2Y_C, 222155131Srwatson PXA_MBUS_LAYOUT_PLANAR_Y_C, 223155131Srwatson}; 224189279Srwatson 225155131Srwatson/** 226155131Srwatson * struct pxa_mbus_pixelfmt - Data format on the media bus 227155131Srwatson * @name: Name of the format 228155131Srwatson * @fourcc: Fourcc code, that will be obtained if the data is 229155131Srwatson * stored in memory in the following way: 230155131Srwatson * @packing: Type of sample-packing, that has to be used 231155131Srwatson * @order: Sample order when storing in memory 232155131Srwatson * @layout: Planes layout in memory 233155131Srwatson * @bits_per_sample: How many bits the bridge has to sample 234186647Srwatson */ 235186647Srwatsonstruct pxa_mbus_pixelfmt { 236186647Srwatson const char *name; 237186647Srwatson u32 fourcc; 238186647Srwatson enum pxa_mbus_packing packing; 239186647Srwatson enum pxa_mbus_order order; 240155131Srwatson enum pxa_mbus_layout layout; 241155131Srwatson u8 bits_per_sample; 242155131Srwatson}; 243155131Srwatson 244155131Srwatson/** 245155131Srwatson * struct pxa_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through 246155131Srwatson * @code: mediabus pixel-code 247155131Srwatson * @fmt: pixel format description 248155131Srwatson */ 249185573Srwatsonstruct pxa_mbus_lookup { 250155131Srwatson u32 code; 251155131Srwatson struct pxa_mbus_pixelfmt fmt; 252155131Srwatson}; 253155131Srwatson 254155131Srwatsonstatic const struct pxa_mbus_lookup mbus_fmt[] = { 255155131Srwatson{ 256155131Srwatson .code = MEDIA_BUS_FMT_YUYV8_2X8, 257155131Srwatson .fmt = { 258155131Srwatson .fourcc = V4L2_PIX_FMT_YUYV, 259155131Srwatson .name = "YUYV", 260155131Srwatson .bits_per_sample = 8, 261155131Srwatson .packing = PXA_MBUS_PACKING_2X8_PADHI, 262155131Srwatson .order = PXA_MBUS_ORDER_LE, 263155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 264155131Srwatson }, 265155131Srwatson}, { 266155131Srwatson .code = MEDIA_BUS_FMT_YVYU8_2X8, 267155131Srwatson .fmt = { 268155131Srwatson .fourcc = V4L2_PIX_FMT_YVYU, 269155131Srwatson .name = "YVYU", 270168777Srwatson .bits_per_sample = 8, 271168777Srwatson .packing = PXA_MBUS_PACKING_2X8_PADHI, 272168777Srwatson .order = PXA_MBUS_ORDER_LE, 273189279Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 274155131Srwatson }, 275168777Srwatson}, { 276168777Srwatson .code = MEDIA_BUS_FMT_UYVY8_2X8, 277168777Srwatson .fmt = { 278168777Srwatson .fourcc = V4L2_PIX_FMT_UYVY, 279168777Srwatson .name = "UYVY", 280168777Srwatson .bits_per_sample = 8, 281168777Srwatson .packing = PXA_MBUS_PACKING_2X8_PADHI, 282168777Srwatson .order = PXA_MBUS_ORDER_LE, 283186647Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 284186647Srwatson }, 285186647Srwatson}, { 286186647Srwatson .code = MEDIA_BUS_FMT_VYUY8_2X8, 287186647Srwatson .fmt = { 288186647Srwatson .fourcc = V4L2_PIX_FMT_VYUY, 289168777Srwatson .name = "VYUY", 290168777Srwatson .bits_per_sample = 8, 291168777Srwatson .packing = PXA_MBUS_PACKING_2X8_PADHI, 292168777Srwatson .order = PXA_MBUS_ORDER_LE, 293168777Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 294168777Srwatson }, 295168777Srwatson}, { 296168777Srwatson .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, 297168777Srwatson .fmt = { 298168777Srwatson .fourcc = V4L2_PIX_FMT_RGB555, 299168777Srwatson .name = "RGB555", 300168777Srwatson .bits_per_sample = 8, 301168777Srwatson .packing = PXA_MBUS_PACKING_2X8_PADHI, 302168777Srwatson .order = PXA_MBUS_ORDER_LE, 303168777Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 304168777Srwatson }, 305168777Srwatson}, { 306168777Srwatson .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, 307168777Srwatson .fmt = { 308168777Srwatson .fourcc = V4L2_PIX_FMT_RGB555X, 309168777Srwatson .name = "RGB555X", 310168777Srwatson .bits_per_sample = 8, 311168777Srwatson .packing = PXA_MBUS_PACKING_2X8_PADHI, 312168777Srwatson .order = PXA_MBUS_ORDER_BE, 313168777Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 314155131Srwatson }, 315155131Srwatson}, { 316155131Srwatson .code = MEDIA_BUS_FMT_RGB565_2X8_LE, 317155131Srwatson .fmt = { 318155131Srwatson .fourcc = V4L2_PIX_FMT_RGB565, 319155131Srwatson .name = "RGB565", 320155131Srwatson .bits_per_sample = 8, 321155131Srwatson .packing = PXA_MBUS_PACKING_2X8_PADHI, 322155131Srwatson .order = PXA_MBUS_ORDER_LE, 323155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 324155131Srwatson }, 325155131Srwatson}, { 326155131Srwatson .code = MEDIA_BUS_FMT_RGB565_2X8_BE, 327155131Srwatson .fmt = { 328155131Srwatson .fourcc = V4L2_PIX_FMT_RGB565X, 329155131Srwatson .name = "RGB565X", 330155131Srwatson .bits_per_sample = 8, 331155131Srwatson .packing = PXA_MBUS_PACKING_2X8_PADHI, 332185573Srwatson .order = PXA_MBUS_ORDER_BE, 333155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 334155131Srwatson }, 335155131Srwatson}, { 336155131Srwatson .code = MEDIA_BUS_FMT_SBGGR8_1X8, 337155131Srwatson .fmt = { 338155131Srwatson .fourcc = V4L2_PIX_FMT_SBGGR8, 339155131Srwatson .name = "Bayer 8 BGGR", 340155131Srwatson .bits_per_sample = 8, 341159248Srwatson .packing = PXA_MBUS_PACKING_NONE, 342155131Srwatson .order = PXA_MBUS_ORDER_LE, 343155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 344155131Srwatson }, 345155131Srwatson}, { 346155131Srwatson .code = MEDIA_BUS_FMT_SGBRG8_1X8, 347155131Srwatson .fmt = { 348155131Srwatson .fourcc = V4L2_PIX_FMT_SGBRG8, 349159248Srwatson .name = "Bayer 8 GBRG", 350159248Srwatson .bits_per_sample = 8, 351159248Srwatson .packing = PXA_MBUS_PACKING_NONE, 352155131Srwatson .order = PXA_MBUS_ORDER_LE, 353155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 354159248Srwatson }, 355159248Srwatson}, { 356159248Srwatson .code = MEDIA_BUS_FMT_SGRBG8_1X8, 357159248Srwatson .fmt = { 358155131Srwatson .fourcc = V4L2_PIX_FMT_SGRBG8, 359155131Srwatson .name = "Bayer 8 GRBG", 360185573Srwatson .bits_per_sample = 8, 361155131Srwatson .packing = PXA_MBUS_PACKING_NONE, 362155131Srwatson .order = PXA_MBUS_ORDER_LE, 363155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 364155131Srwatson }, 365159248Srwatson}, { 366155131Srwatson .code = MEDIA_BUS_FMT_SRGGB8_1X8, 367155131Srwatson .fmt = { 368155131Srwatson .fourcc = V4L2_PIX_FMT_SRGGB8, 369186647Srwatson .name = "Bayer 8 RGGB", 370186647Srwatson .bits_per_sample = 8, 371186647Srwatson .packing = PXA_MBUS_PACKING_NONE, 372186647Srwatson .order = PXA_MBUS_ORDER_LE, 373155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 374155131Srwatson }, 375155131Srwatson}, { 376155131Srwatson .code = MEDIA_BUS_FMT_SBGGR10_1X10, 377155131Srwatson .fmt = { 378155131Srwatson .fourcc = V4L2_PIX_FMT_SBGGR10, 379155131Srwatson .name = "Bayer 10 BGGR", 380155131Srwatson .bits_per_sample = 10, 381155131Srwatson .packing = PXA_MBUS_PACKING_EXTEND16, 382155131Srwatson .order = PXA_MBUS_ORDER_LE, 383155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 384155131Srwatson }, 385155131Srwatson}, { 386155131Srwatson .code = MEDIA_BUS_FMT_Y8_1X8, 387155131Srwatson .fmt = { 388155131Srwatson .fourcc = V4L2_PIX_FMT_GREY, 389155131Srwatson .name = "Grey", 390155131Srwatson .bits_per_sample = 8, 391155131Srwatson .packing = PXA_MBUS_PACKING_NONE, 392155131Srwatson .order = PXA_MBUS_ORDER_LE, 393155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 394155131Srwatson }, 395155131Srwatson}, { 396155131Srwatson .code = MEDIA_BUS_FMT_Y10_1X10, 397155131Srwatson .fmt = { 398155131Srwatson .fourcc = V4L2_PIX_FMT_Y10, 399155131Srwatson .name = "Grey 10bit", 400155131Srwatson .bits_per_sample = 10, 401155131Srwatson .packing = PXA_MBUS_PACKING_EXTEND16, 402155131Srwatson .order = PXA_MBUS_ORDER_LE, 403155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 404155131Srwatson }, 405155131Srwatson}, { 406155131Srwatson .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, 407155131Srwatson .fmt = { 408155131Srwatson .fourcc = V4L2_PIX_FMT_SBGGR10, 409155131Srwatson .name = "Bayer 10 BGGR", 410155131Srwatson .bits_per_sample = 8, 411185573Srwatson .packing = PXA_MBUS_PACKING_2X8_PADHI, 412155131Srwatson .order = PXA_MBUS_ORDER_LE, 413155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 414155131Srwatson }, 415155131Srwatson}, { 416155131Srwatson .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE, 417155131Srwatson .fmt = { 418155131Srwatson .fourcc = V4L2_PIX_FMT_SBGGR10, 419155131Srwatson .name = "Bayer 10 BGGR", 420155131Srwatson .bits_per_sample = 8, 421155131Srwatson .packing = PXA_MBUS_PACKING_2X8_PADHI, 422155131Srwatson .order = PXA_MBUS_ORDER_BE, 423155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 424155131Srwatson }, 425155131Srwatson}, { 426155131Srwatson .code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE, 427155131Srwatson .fmt = { 428155131Srwatson .fourcc = V4L2_PIX_FMT_RGB444, 429155131Srwatson .name = "RGB444", 430155131Srwatson .bits_per_sample = 8, 431155131Srwatson .packing = PXA_MBUS_PACKING_2X8_PADHI, 432155131Srwatson .order = PXA_MBUS_ORDER_BE, 433155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 434155131Srwatson }, 435155131Srwatson}, { 436155131Srwatson .code = MEDIA_BUS_FMT_UYVY8_1X16, 437155131Srwatson .fmt = { 438155131Srwatson .fourcc = V4L2_PIX_FMT_UYVY, 439155131Srwatson .name = "UYVY 16bit", 440155131Srwatson .bits_per_sample = 16, 441155131Srwatson .packing = PXA_MBUS_PACKING_EXTEND16, 442155131Srwatson .order = PXA_MBUS_ORDER_LE, 443155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 444155131Srwatson }, 445155131Srwatson}, { 446155131Srwatson .code = MEDIA_BUS_FMT_VYUY8_1X16, 447155131Srwatson .fmt = { 448155131Srwatson .fourcc = V4L2_PIX_FMT_VYUY, 449159248Srwatson .name = "VYUY 16bit", 450155131Srwatson .bits_per_sample = 16, 451155131Srwatson .packing = PXA_MBUS_PACKING_EXTEND16, 452155131Srwatson .order = PXA_MBUS_ORDER_LE, 453155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 454159248Srwatson }, 455155131Srwatson}, { 456155131Srwatson .code = MEDIA_BUS_FMT_YUYV8_1X16, 457155131Srwatson .fmt = { 458155131Srwatson .fourcc = V4L2_PIX_FMT_YUYV, 459155131Srwatson .name = "YUYV 16bit", 460155131Srwatson .bits_per_sample = 16, 461155131Srwatson .packing = PXA_MBUS_PACKING_EXTEND16, 462185573Srwatson .order = PXA_MBUS_ORDER_LE, 463155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 464155131Srwatson }, 465155131Srwatson}, { 466155131Srwatson .code = MEDIA_BUS_FMT_YVYU8_1X16, 467155131Srwatson .fmt = { 468155131Srwatson .fourcc = V4L2_PIX_FMT_YVYU, 469186647Srwatson .name = "YVYU 16bit", 470155131Srwatson .bits_per_sample = 16, 471159248Srwatson .packing = PXA_MBUS_PACKING_EXTEND16, 472155131Srwatson .order = PXA_MBUS_ORDER_LE, 473155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 474155131Srwatson }, 475155131Srwatson}, { 476155131Srwatson .code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8, 477171537Srwatson .fmt = { 478155131Srwatson .fourcc = V4L2_PIX_FMT_SGRBG10DPCM8, 479155131Srwatson .name = "Bayer 10 BGGR DPCM 8", 480155131Srwatson .bits_per_sample = 8, 481155131Srwatson .packing = PXA_MBUS_PACKING_NONE, 482155131Srwatson .order = PXA_MBUS_ORDER_LE, 483155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 484155131Srwatson }, 485168777Srwatson}, { 486168777Srwatson .code = MEDIA_BUS_FMT_SGBRG10_1X10, 487155131Srwatson .fmt = { 488155131Srwatson .fourcc = V4L2_PIX_FMT_SGBRG10, 489155131Srwatson .name = "Bayer 10 GBRG", 490155131Srwatson .bits_per_sample = 10, 491155131Srwatson .packing = PXA_MBUS_PACKING_EXTEND16, 492155131Srwatson .order = PXA_MBUS_ORDER_LE, 493155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 494155131Srwatson }, 495155131Srwatson}, { 496155131Srwatson .code = MEDIA_BUS_FMT_SGRBG10_1X10, 497155131Srwatson .fmt = { 498155131Srwatson .fourcc = V4L2_PIX_FMT_SGRBG10, 499155131Srwatson .name = "Bayer 10 GRBG", 500155131Srwatson .bits_per_sample = 10, 501155131Srwatson .packing = PXA_MBUS_PACKING_EXTEND16, 502155131Srwatson .order = PXA_MBUS_ORDER_LE, 503155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 504155131Srwatson }, 505155131Srwatson}, { 506155131Srwatson .code = MEDIA_BUS_FMT_SRGGB10_1X10, 507155131Srwatson .fmt = { 508155131Srwatson .fourcc = V4L2_PIX_FMT_SRGGB10, 509155131Srwatson .name = "Bayer 10 RGGB", 510155131Srwatson .bits_per_sample = 10, 511155131Srwatson .packing = PXA_MBUS_PACKING_EXTEND16, 512155131Srwatson .order = PXA_MBUS_ORDER_LE, 513155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 514155131Srwatson }, 515155131Srwatson}, { 516155131Srwatson .code = MEDIA_BUS_FMT_SBGGR12_1X12, 517155131Srwatson .fmt = { 518155131Srwatson .fourcc = V4L2_PIX_FMT_SBGGR12, 519155131Srwatson .name = "Bayer 12 BGGR", 520155131Srwatson .bits_per_sample = 12, 521155131Srwatson .packing = PXA_MBUS_PACKING_EXTEND16, 522155131Srwatson .order = PXA_MBUS_ORDER_LE, 523155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 524155131Srwatson }, 525155131Srwatson}, { 526155131Srwatson .code = MEDIA_BUS_FMT_SGBRG12_1X12, 527155131Srwatson .fmt = { 528155131Srwatson .fourcc = V4L2_PIX_FMT_SGBRG12, 529155131Srwatson .name = "Bayer 12 GBRG", 530155131Srwatson .bits_per_sample = 12, 531155131Srwatson .packing = PXA_MBUS_PACKING_EXTEND16, 532155131Srwatson .order = PXA_MBUS_ORDER_LE, 533155131Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 534155131Srwatson }, 535155131Srwatson}, { 536155131Srwatson .code = MEDIA_BUS_FMT_SGRBG12_1X12, 537155131Srwatson .fmt = { 538155131Srwatson .fourcc = V4L2_PIX_FMT_SGRBG12, 539155131Srwatson .name = "Bayer 12 GRBG", 540155131Srwatson .bits_per_sample = 12, 541155131Srwatson .packing = PXA_MBUS_PACKING_EXTEND16, 542155131Srwatson .order = PXA_MBUS_ORDER_LE, 543189279Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 544189279Srwatson }, 545155131Srwatson}, { 546155131Srwatson .code = MEDIA_BUS_FMT_SRGGB12_1X12, 547155131Srwatson .fmt = { 548155131Srwatson .fourcc = V4L2_PIX_FMT_SRGGB12, 549155131Srwatson .name = "Bayer 12 RGGB", 550155131Srwatson .bits_per_sample = 12, 551186647Srwatson .packing = PXA_MBUS_PACKING_EXTEND16, 552186647Srwatson .order = PXA_MBUS_ORDER_LE, 553186647Srwatson .layout = PXA_MBUS_LAYOUT_PACKED, 554186647Srwatson }, 555186647Srwatson}, 556186647Srwatson}; 557186647Srwatson 558186647Srwatsonstatic s32 pxa_mbus_bytes_per_line(u32 width, const struct pxa_mbus_pixelfmt *mf) 559155131Srwatson{ 560186647Srwatson if (mf->layout != PXA_MBUS_LAYOUT_PACKED) 561186647Srwatson return width * mf->bits_per_sample / 8; 562186647Srwatson 563186647Srwatson switch (mf->packing) { 564186647Srwatson case PXA_MBUS_PACKING_NONE: 565186647Srwatson return width * mf->bits_per_sample / 8; 566186647Srwatson case PXA_MBUS_PACKING_2X8_PADHI: 567186647Srwatson case PXA_MBUS_PACKING_EXTEND16: 568186647Srwatson return width * 2; 569186647Srwatson } 570186647Srwatson return -EINVAL; 571186647Srwatson} 572186647Srwatson 573186647Srwatsonstatic s32 pxa_mbus_image_size(const struct pxa_mbus_pixelfmt *mf, 574186647Srwatson u32 bytes_per_line, u32 height) 575155131Srwatson{ 576155131Srwatson if (mf->layout == PXA_MBUS_LAYOUT_PACKED) 577155131Srwatson return bytes_per_line * height; 578155131Srwatson 579155131Srwatson switch (mf->packing) { 580156283Srwatson case PXA_MBUS_PACKING_2X8_PADHI: 581156283Srwatson return bytes_per_line * height * 2; 582156283Srwatson default: 583185573Srwatson return -EINVAL; 584185573Srwatson } 585185573Srwatson} 586185573Srwatson 587155131Srwatsonstatic const struct pxa_mbus_pixelfmt *pxa_mbus_find_fmtdesc( 588185573Srwatson u32 code, 589185573Srwatson const struct pxa_mbus_lookup *lookup, 590155131Srwatson int n) 591156283Srwatson{ 592156283Srwatson int i; 593185573Srwatson 594185573Srwatson for (i = 0; i < n; i++) 595185573Srwatson if (lookup[i].code == code) 596185573Srwatson return &lookup[i].fmt; 597155131Srwatson 598185573Srwatson return NULL; 599185573Srwatson} 600155131Srwatson 601155131Srwatsonstatic const struct pxa_mbus_pixelfmt *pxa_mbus_get_fmtdesc( 602155131Srwatson u32 code) 603155131Srwatson{ 604155131Srwatson return pxa_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt)); 605155131Srwatson} 606155131Srwatson 607155131Srwatson/** 608155131Srwatson * struct pxa_camera_format_xlate - match between host and sensor formats 609155131Srwatson * @code: code of a sensor provided format 610155131Srwatson * @host_fmt: host format after host translation from code 611155131Srwatson * 612155131Srwatson * Host and sensor translation structure. Used in table of host and sensor 613155131Srwatson * formats matchings in pxa_camera_device. A host can override the generic list 614155131Srwatson * generation by implementing get_formats(), and use it for format checks and 615155131Srwatson * format setup. 616155131Srwatson */ 617155131Srwatsonstruct pxa_camera_format_xlate { 618155131Srwatson u32 code; 619155131Srwatson const struct pxa_mbus_pixelfmt *host_fmt; 620155131Srwatson}; 621155131Srwatson 622155131Srwatson/* 623155131Srwatson * Structures 624155131Srwatson */ 625155131Srwatsonenum pxa_camera_active_dma { 626155131Srwatson DMA_Y = 0x1, 627155131Srwatson DMA_U = 0x2, 628155131Srwatson DMA_V = 0x4, 629155131Srwatson}; 630185573Srwatson 631155131Srwatson/* buffer for one video frame */ 632155131Srwatsonstruct pxa_buffer { 633155131Srwatson /* common v4l buffer stuff -- must be first */ 634155131Srwatson struct vb2_v4l2_buffer vbuf; 635155131Srwatson struct list_head queue; 636155131Srwatson u32 code; 637155131Srwatson int nb_planes; 638155131Srwatson /* our descriptor lists for Y, U and V channels */ 639155131Srwatson struct dma_async_tx_descriptor *descs[3]; 640155131Srwatson dma_cookie_t cookie[3]; 641155131Srwatson struct scatterlist *sg[3]; 642155131Srwatson int sg_len[3]; 643155131Srwatson size_t plane_sizes[3]; 644155131Srwatson int inwork; 645155131Srwatson enum pxa_camera_active_dma active_dma; 646155131Srwatson}; 647155131Srwatson 648155131Srwatsonstruct pxa_camera_dev { 649155131Srwatson struct v4l2_device v4l2_dev; 650155131Srwatson struct video_device vdev; 651155131Srwatson struct v4l2_async_notifier notifier; 652155131Srwatson struct vb2_queue vb2_vq; 653155131Srwatson struct v4l2_subdev *sensor; 654185573Srwatson struct pxa_camera_format_xlate *user_formats; 655155131Srwatson const struct pxa_camera_format_xlate *current_fmt; 656155131Srwatson struct v4l2_pix_format current_pix; 657155131Srwatson 658155131Srwatson /* 659155131Srwatson * PXA27x is only supposed to handle one camera on its Quick Capture 660155131Srwatson * interface. If anyone ever builds hardware to enable more than 661155131Srwatson * one camera, they will have to modify this driver too 662155131Srwatson */ 663155131Srwatson struct clk *clk; 664155131Srwatson 665155131Srwatson unsigned int irq; 666155131Srwatson void __iomem *base; 667155131Srwatson 668155131Srwatson int channels; 669155131Srwatson struct dma_chan *dma_chans[3]; 670155131Srwatson 671155131Srwatson struct pxacamera_platform_data *pdata; 672155131Srwatson struct resource *res; 673155131Srwatson unsigned long platform_flags; 674155131Srwatson unsigned long ciclk; 675155131Srwatson unsigned long mclk; 676155131Srwatson u32 mclk_divisor; 677155131Srwatson u16 width_flags; /* max 10 bits */ 678155131Srwatson 679155131Srwatson struct list_head capture; 680155131Srwatson 681155131Srwatson spinlock_t lock; 682155131Srwatson struct mutex mlock; 683155131Srwatson unsigned int buf_sequence; 684155131Srwatson 685155131Srwatson struct pxa_buffer *active; 686185573Srwatson struct tasklet_struct task_eof; 687155131Srwatson 688155131Srwatson u32 save_cicr[5]; 689155131Srwatson}; 690155131Srwatson 691155131Srwatsonstruct pxa_cam { 692155131Srwatson unsigned long flags; 693155131Srwatson}; 694155131Srwatson 695186647Srwatsonstatic const char *pxa_cam_driver_description = "PXA_Camera"; 696186647Srwatson 697155131Srwatson/* 698155131Srwatson * Format translation functions 699155131Srwatson */ 700155131Srwatsonstatic const struct pxa_camera_format_xlate 701155131Srwatson*pxa_mbus_xlate_by_fourcc(struct pxa_camera_format_xlate *user_formats, 702155131Srwatson unsigned int fourcc) 703155131Srwatson{ 704155131Srwatson unsigned int i; 705155131Srwatson 706155131Srwatson for (i = 0; user_formats[i].code; i++) 707155131Srwatson if (user_formats[i].host_fmt->fourcc == fourcc) 708155131Srwatson return user_formats + i; 709155131Srwatson return NULL; 710155131Srwatson} 711155131Srwatson 712155131Srwatsonstatic struct pxa_camera_format_xlate *pxa_mbus_build_fmts_xlate( 713155131Srwatson struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev, 714185573Srwatson int (*get_formats)(struct v4l2_device *, unsigned int, 715155131Srwatson struct pxa_camera_format_xlate *xlate)) 716155131Srwatson{ 717155131Srwatson unsigned int i, fmts = 0, raw_fmts = 0; 718155131Srwatson int ret; 719155131Srwatson struct v4l2_subdev_mbus_code_enum code = { 720155131Srwatson .which = V4L2_SUBDEV_FORMAT_ACTIVE, 721155131Srwatson }; 722155131Srwatson struct pxa_camera_format_xlate *user_formats; 723155131Srwatson 724155131Srwatson while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) { 725155131Srwatson raw_fmts++; 726155131Srwatson code.index++; 727155131Srwatson } 728155131Srwatson 729155131Srwatson /* 730155131Srwatson * First pass - only count formats this host-sensor 731155131Srwatson * configuration can provide 732155131Srwatson */ 733155131Srwatson for (i = 0; i < raw_fmts; i++) { 734155131Srwatson ret = get_formats(v4l2_dev, i, NULL); 735155131Srwatson if (ret < 0) 736155131Srwatson return ERR_PTR(ret); 737155131Srwatson fmts += ret; 738155131Srwatson } 739155131Srwatson 740155131Srwatson if (!fmts) 741155131Srwatson return ERR_PTR(-ENXIO); 742155131Srwatson 743155131Srwatson user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL); 744155131Srwatson if (!user_formats) 745155131Srwatson return ERR_PTR(-ENOMEM); 746155131Srwatson 747155131Srwatson /* Second pass - actually fill data formats */ 748155131Srwatson fmts = 0; 749155131Srwatson for (i = 0; i < raw_fmts; i++) { 750155131Srwatson ret = get_formats(v4l2_dev, i, user_formats + fmts); 751155131Srwatson if (ret < 0) 752155131Srwatson goto egfmt; 753155131Srwatson fmts += ret; 754155131Srwatson } 755155131Srwatson user_formats[fmts].code = 0; 756155131Srwatson 757155131Srwatson return user_formats; 758155131Srwatsonegfmt: 759155131Srwatson kfree(user_formats); 760155131Srwatson return ERR_PTR(ret); 761155131Srwatson} 762155131Srwatson 763155131Srwatson/* 764155131Srwatson * Videobuf operations 765155131Srwatson */ 766155131Srwatsonstatic struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb) 767186647Srwatson{ 768186647Srwatson struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 769186647Srwatson 770186647Srwatson return container_of(vbuf, struct pxa_buffer, vbuf); 771186647Srwatson} 772186647Srwatson 773186647Srwatsonstatic struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev) 774159248Srwatson{ 775155131Srwatson return pcdev->v4l2_dev.dev; 776155131Srwatson} 777155131Srwatson 778155131Srwatsonstatic struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev) 779155131Srwatson{ 780168777Srwatson return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev); 781168777Srwatson} 782155131Srwatson 783168777Srwatsonstatic void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev, 784168777Srwatson enum pxa_camera_active_dma act_dma); 785155131Srwatson 786168777Srwatsonstatic void pxa_camera_dma_irq_y(void *data) 787168777Srwatson{ 788168777Srwatson struct pxa_camera_dev *pcdev = data; 789168777Srwatson 790168777Srwatson pxa_camera_dma_irq(pcdev, DMA_Y); 791168777Srwatson} 792168777Srwatson 793168777Srwatsonstatic void pxa_camera_dma_irq_u(void *data) 794168777Srwatson{ 795168777Srwatson struct pxa_camera_dev *pcdev = data; 796168777Srwatson 797168777Srwatson pxa_camera_dma_irq(pcdev, DMA_U); 798168777Srwatson} 799168777Srwatson 800186647Srwatsonstatic void pxa_camera_dma_irq_v(void *data) 801186647Srwatson{ 802186647Srwatson struct pxa_camera_dev *pcdev = data; 803186647Srwatson 804186647Srwatson pxa_camera_dma_irq(pcdev, DMA_V); 805186647Srwatson} 806186647Srwatson 807168777Srwatson/** 808168777Srwatson * pxa_init_dma_channel - init dma descriptors 809168777Srwatson * @pcdev: pxa camera device 810155131Srwatson * @buf: pxa camera buffer 811155131Srwatson * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V') 812155131Srwatson * @sg: dma scatter list 813168777Srwatson * @sglen: dma scatter list length 814168777Srwatson * 815155131Srwatson * Prepares the pxa dma descriptors to transfer one camera channel. 816155131Srwatson * 817155131Srwatson * Returns 0 if success or -ENOMEM if no memory is available 818155131Srwatson */ 819155131Srwatsonstatic int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, 820155131Srwatson struct pxa_buffer *buf, int channel, 821155131Srwatson struct scatterlist *sg, int sglen) 822155131Srwatson{ 823155131Srwatson struct dma_chan *dma_chan = pcdev->dma_chans[channel]; 824155131Srwatson struct dma_async_tx_descriptor *tx; 825155131Srwatson 826155131Srwatson tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM, 827155131Srwatson DMA_PREP_INTERRUPT | DMA_CTRL_REUSE); 828155131Srwatson if (!tx) { 829155131Srwatson dev_err(pcdev_to_dev(pcdev), 830155131Srwatson "dmaengine_prep_slave_sg failed\n"); 831155131Srwatson goto fail; 832155131Srwatson } 833155131Srwatson 834155131Srwatson tx->callback_param = pcdev; 835155131Srwatson switch (channel) { 836155131Srwatson case 0: 837155131Srwatson tx->callback = pxa_camera_dma_irq_y; 838155131Srwatson break; 839155131Srwatson case 1: 840155131Srwatson tx->callback = pxa_camera_dma_irq_u; 841155131Srwatson break; 842159985Srwatson case 2: 843159985Srwatson tx->callback = pxa_camera_dma_irq_v; 844159985Srwatson break; 845159985Srwatson } 846159985Srwatson 847159985Srwatson buf->descs[channel] = tx; 848159985Srwatson return 0; 849159985Srwatsonfail: 850159985Srwatson dev_dbg(pcdev_to_dev(pcdev), 851159985Srwatson "%s (vb=%p) dma_tx=%p\n", 852155131Srwatson __func__, buf, tx); 853155131Srwatson 854155131Srwatson return -ENOMEM; 855155131Srwatson} 856155131Srwatson 857155131Srwatsonstatic void pxa_video_buf_set_actdma(struct pxa_camera_dev *pcdev, 858155131Srwatson struct pxa_buffer *buf) 859155131Srwatson{ 860155131Srwatson buf->active_dma = DMA_Y; 861155131Srwatson if (buf->nb_planes == 3) 862155131Srwatson buf->active_dma |= DMA_U | DMA_V; 863155131Srwatson} 864155131Srwatson 865168777Srwatson/** 866159985Srwatson * pxa_dma_start_channels - start DMA channel for active buffer 867168777Srwatson * @pcdev: pxa camera device 868168777Srwatson * 869168777Srwatson * Initialize DMA channels to the beginning of the active video buffer, and 870159985Srwatson * start these channels. 871155131Srwatson */ 872155131Srwatsonstatic void pxa_dma_start_channels(struct pxa_camera_dev *pcdev) 873155131Srwatson{ 874155131Srwatson int i; 875155131Srwatson 876155131Srwatson for (i = 0; i < pcdev->channels; i++) { 877155131Srwatson dev_dbg(pcdev_to_dev(pcdev), 878155131Srwatson "%s (channel=%d)\n", __func__, i); 879168777Srwatson dma_async_issue_pending(pcdev->dma_chans[i]); 880168777Srwatson } 881155131Srwatson} 882168777Srwatson 883168777Srwatsonstatic void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev) 884168777Srwatson{ 885168777Srwatson int i; 886168777Srwatson 887168777Srwatson for (i = 0; i < pcdev->channels; i++) { 888168777Srwatson dev_dbg(pcdev_to_dev(pcdev), 889168777Srwatson "%s (channel=%d)\n", __func__, i); 890168777Srwatson dmaengine_terminate_all(pcdev->dma_chans[i]); 891168777Srwatson } 892168777Srwatson} 893168777Srwatson 894168777Srwatsonstatic void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev, 895168777Srwatson struct pxa_buffer *buf) 896168777Srwatson{ 897168777Srwatson int i; 898168777Srwatson 899168777Srwatson for (i = 0; i < pcdev->channels; i++) { 900168777Srwatson buf->cookie[i] = dmaengine_submit(buf->descs[i]); 901168777Srwatson dev_dbg(pcdev_to_dev(pcdev), 902168777Srwatson "%s (channel=%d) : submit vb=%p cookie=%d\n", 903168777Srwatson __func__, i, buf, buf->descs[i]->cookie); 904168777Srwatson } 905168777Srwatson} 906168777Srwatson 907168777Srwatson/** 908168777Srwatson * pxa_camera_start_capture - start video capturing 909168777Srwatson * @pcdev: camera device 910168777Srwatson * 911168777Srwatson * Launch capturing. DMA channels should not be active yet. They should get 912168777Srwatson * activated at the end of frame interrupt, to capture only whole frames, and 913168777Srwatson * never begin the capture of a partial frame. 914168777Srwatson */ 915155131Srwatsonstatic void pxa_camera_start_capture(struct pxa_camera_dev *pcdev) 916155131Srwatson{ 917155131Srwatson unsigned long cicr0; 918155131Srwatson 919155131Srwatson dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__); 920155131Srwatson __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR); 921155131Srwatson /* Enable End-Of-Frame Interrupt */ 922155131Srwatson cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; 923155131Srwatson cicr0 &= ~CICR0_EOFM; 924155131Srwatson __raw_writel(cicr0, pcdev->base + CICR0); 925155131Srwatson} 926155131Srwatson 927155131Srwatsonstatic void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev) 928155131Srwatson{ 929155131Srwatson unsigned long cicr0; 930155131Srwatson 931155131Srwatson pxa_dma_stop_channels(pcdev); 932155131Srwatson 933155131Srwatson cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; 934155131Srwatson __raw_writel(cicr0, pcdev->base + CICR0); 935155131Srwatson 936155131Srwatson pcdev->active = NULL; 937155131Srwatson dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__); 938155131Srwatson} 939155131Srwatson 940155131Srwatsonstatic void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, 941155131Srwatson struct pxa_buffer *buf, 942155131Srwatson enum vb2_buffer_state state) 943155131Srwatson{ 944155131Srwatson struct vb2_buffer *vb = &buf->vbuf.vb2_buf; 945155131Srwatson struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 946155131Srwatson 947155131Srwatson /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ 948155131Srwatson list_del_init(&buf->queue); 949155131Srwatson vb->timestamp = ktime_get_ns(); 950155131Srwatson vbuf->sequence = pcdev->buf_sequence++; 951155131Srwatson vbuf->field = V4L2_FIELD_NONE; 952155131Srwatson vb2_buffer_done(vb, VB2_BUF_STATE_DONE); 953155131Srwatson dev_dbg(pcdev_to_dev(pcdev), "%s dequeued buffer (buf=0x%p)\n", 954155131Srwatson __func__, buf); 955155131Srwatson 956155131Srwatson if (list_empty(&pcdev->capture)) { 957155131Srwatson pxa_camera_stop_capture(pcdev); 958155131Srwatson return; 959155131Srwatson } 960155131Srwatson 961155131Srwatson pcdev->active = list_entry(pcdev->capture.next, 962155131Srwatson struct pxa_buffer, queue); 963155131Srwatson} 964155131Srwatson 965155131Srwatson/** 966155131Srwatson * pxa_camera_check_link_miss - check missed DMA linking 967155131Srwatson * @pcdev: camera device 968155131Srwatson * @last_submitted: an opaque DMA cookie for last submitted 969155131Srwatson * @last_issued: an opaque DMA cookie for last issued 970155131Srwatson * 971155131Srwatson * The DMA chaining is done with DMA running. This means a tiny temporal window 972155131Srwatson * remains, where a buffer is queued on the chain, while the chain is already 973155131Srwatson * stopped. This means the tailed buffer would never be transferred by DMA. 974155131Srwatson * This function restarts the capture for this corner case, where : 975155131Srwatson * - DADR() == DADDR_STOP 976155131Srwatson * - a video buffer is queued on the pcdev->capture list 977155131Srwatson * 978155131Srwatson * Please check the "DMA hot chaining timeslice issue" in 979155131Srwatson * Documentation/driver-api/media/drivers/pxa_camera.rst 980155131Srwatson * 981155131Srwatson * Context: should only be called within the dma irq handler 982155131Srwatson */ 983155131Srwatsonstatic void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev, 984155131Srwatson dma_cookie_t last_submitted, 985155131Srwatson dma_cookie_t last_issued) 986155131Srwatson{ 987155131Srwatson bool is_dma_stopped = last_submitted != last_issued; 988155131Srwatson 989155131Srwatson dev_dbg(pcdev_to_dev(pcdev), 990155131Srwatson "%s : top queued buffer=%p, is_dma_stopped=%d\n", 991155131Srwatson __func__, pcdev->active, is_dma_stopped); 992155131Srwatson 993155131Srwatson if (pcdev->active && is_dma_stopped) 994186647Srwatson pxa_camera_start_capture(pcdev); 995186647Srwatson} 996186647Srwatson 997186647Srwatsonstatic void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev, 998186647Srwatson enum pxa_camera_active_dma act_dma) 999186647Srwatson{ 1000186647Srwatson struct pxa_buffer *buf, *last_buf; 1001187214Srwatson unsigned long flags; 1002187214Srwatson u32 camera_status, overrun; 1003187214Srwatson int chan; 1004186647Srwatson enum dma_status last_status; 1005186647Srwatson dma_cookie_t last_issued; 1006186647Srwatson 1007186647Srwatson spin_lock_irqsave(&pcdev->lock, flags); 1008186647Srwatson 1009186647Srwatson camera_status = __raw_readl(pcdev->base + CISR); 1010186647Srwatson dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n", 1011186647Srwatson camera_status, act_dma); 1012186647Srwatson overrun = CISR_IFO_0; 1013186647Srwatson if (pcdev->channels == 3) 1014186647Srwatson overrun |= CISR_IFO_1 | CISR_IFO_2; 1015186647Srwatson 1016186647Srwatson /* 1017186647Srwatson * pcdev->active should not be NULL in DMA irq handler. 1018186647Srwatson * 1019189279Srwatson * But there is one corner case : if capture was stopped due to an 1020186647Srwatson * overrun of channel 1, and at that same channel 2 was completed. 1021186647Srwatson * 1022186647Srwatson * When handling the overrun in DMA irq for channel 1, we'll stop the 1023186647Srwatson * capture and restart it (and thus set pcdev->active to NULL). But the 1024243750Srwatson * DMA irq handler will already be pending for channel 2. So on entering 1025243750Srwatson * the DMA irq handler for channel 2 there will be no active buffer, yet 1026186647Srwatson * that is normal. 1027186647Srwatson */ 1028189279Srwatson if (!pcdev->active) 1029189279Srwatson goto out; 1030186647Srwatson 1031186647Srwatson buf = pcdev->active; 1032186647Srwatson WARN_ON(buf->inwork || list_empty(&buf->queue)); 1033186647Srwatson 1034186647Srwatson /* 1035186647Srwatson * It's normal if the last frame creates an overrun, as there 1036186647Srwatson * are no more DMA descriptors to fetch from QCI fifos 1037186647Srwatson */ 1038186647Srwatson switch (act_dma) { 1039186647Srwatson case DMA_U: 1040186647Srwatson chan = 1; 1041186647Srwatson break; 1042186647Srwatson case DMA_V: 1043186647Srwatson chan = 2; 1044186647Srwatson break; 1045186647Srwatson default: 1046186647Srwatson chan = 0; 1047186647Srwatson break; 1048186647Srwatson } 1049186647Srwatson last_buf = list_entry(pcdev->capture.prev, 1050186647Srwatson struct pxa_buffer, queue); 1051186647Srwatson last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan], 1052186647Srwatson last_buf->cookie[chan], 1053155131Srwatson NULL, &last_issued); 1054195740Srwatson if (camera_status & overrun && 1055155131Srwatson last_status != DMA_COMPLETE) { 1056155131Srwatson dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n", 1057155131Srwatson camera_status); 1058155131Srwatson pxa_camera_stop_capture(pcdev); 1059155131Srwatson list_for_each_entry(buf, &pcdev->capture, queue) 1060155131Srwatson pxa_dma_add_tail_buf(pcdev, buf); 1061155131Srwatson pxa_camera_start_capture(pcdev); 1062155131Srwatson goto out; 1063155131Srwatson } 1064155131Srwatson buf->active_dma &= ~act_dma; 1065155131Srwatson if (!buf->active_dma) { 1066185573Srwatson pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_DONE); 1067155131Srwatson pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan], 1068155131Srwatson last_issued); 1069155131Srwatson } 1070155131Srwatson 1071155131Srwatsonout: 1072155131Srwatson spin_unlock_irqrestore(&pcdev->lock, flags); 1073155131Srwatson} 1074155131Srwatson 1075155131Srwatsonstatic u32 mclk_get_divisor(struct platform_device *pdev, 1076155131Srwatson struct pxa_camera_dev *pcdev) 1077155131Srwatson{ 1078155131Srwatson unsigned long mclk = pcdev->mclk; 1079155131Srwatson u32 div; 1080155131Srwatson unsigned long lcdclk; 1081155131Srwatson 1082155131Srwatson lcdclk = clk_get_rate(pcdev->clk); 1083155131Srwatson pcdev->ciclk = lcdclk; 1084155131Srwatson 1085155131Srwatson /* mclk <= ciclk / 4 (27.4.2) */ 1086159248Srwatson if (mclk > lcdclk / 4) { 1087155131Srwatson mclk = lcdclk / 4; 1088159248Srwatson dev_warn(&pdev->dev, 1089159248Srwatson "Limiting master clock to %lu\n", mclk); 1090155131Srwatson } 1091155131Srwatson 1092155131Srwatson /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ 1093155131Srwatson div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; 1094155131Srwatson 1095159248Srwatson /* If we're not supplying MCLK, leave it at 0 */ 1096159248Srwatson if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) 1097159248Srwatson pcdev->mclk = lcdclk / (2 * (div + 1)); 1098159248Srwatson 1099159248Srwatson dev_dbg(&pdev->dev, "LCD clock %luHz, target freq %luHz, divisor %u\n", 1100159248Srwatson lcdclk, mclk, div); 1101159248Srwatson 1102159248Srwatson return div; 1103185573Srwatson} 1104159248Srwatson 1105159248Srwatsonstatic void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, 1106159248Srwatson unsigned long pclk) 1107159248Srwatson{ 1108155131Srwatson /* We want a timeout > 1 pixel time, not ">=" */ 1109155131Srwatson u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1; 1110155131Srwatson 1111155131Srwatson __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); 1112155131Srwatson} 1113155131Srwatson 1114155131Srwatsonstatic void pxa_camera_activate(struct pxa_camera_dev *pcdev) 1115155131Srwatson{ 1116155131Srwatson u32 cicr4 = 0; 1117155131Srwatson 1118155131Srwatson /* disable all interrupts */ 1119155131Srwatson __raw_writel(0x3ff, pcdev->base + CICR0); 1120155131Srwatson 1121155131Srwatson if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) 1122155131Srwatson cicr4 |= CICR4_PCLK_EN; 1123155131Srwatson if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) 1124155131Srwatson cicr4 |= CICR4_MCLK_EN; 1125186647Srwatson if (pcdev->platform_flags & PXA_CAMERA_PCP) 1126186647Srwatson cicr4 |= CICR4_PCP; 1127186647Srwatson if (pcdev->platform_flags & PXA_CAMERA_HSP) 1128185573Srwatson cicr4 |= CICR4_HSP; 1129155131Srwatson if (pcdev->platform_flags & PXA_CAMERA_VSP) 1130155131Srwatson cicr4 |= CICR4_VSP; 1131155131Srwatson 1132155131Srwatson __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); 1133159248Srwatson 1134155131Srwatson if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) 1135155131Srwatson /* Initialise the timeout under the assumption pclk = mclk */ 1136155131Srwatson recalculate_fifo_timeout(pcdev, pcdev->mclk); 1137155131Srwatson else 1138155131Srwatson /* "Safe default" - 13MHz */ 1139155131Srwatson recalculate_fifo_timeout(pcdev, 13000000); 1140155131Srwatson 1141155131Srwatson clk_prepare_enable(pcdev->clk); 1142155131Srwatson} 1143155131Srwatson 1144155131Srwatsonstatic void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) 1145155131Srwatson{ 1146155131Srwatson clk_disable_unprepare(pcdev->clk); 1147155131Srwatson} 1148155131Srwatson 1149155131Srwatsonstatic void pxa_camera_eof(struct tasklet_struct *t) 1150155131Srwatson{ 1151155131Srwatson struct pxa_camera_dev *pcdev = from_tasklet(pcdev, t, task_eof); 1152155131Srwatson unsigned long cifr; 1153155131Srwatson struct pxa_buffer *buf; 1154155131Srwatson 1155155131Srwatson dev_dbg(pcdev_to_dev(pcdev), 1156155131Srwatson "Camera interrupt status 0x%x\n", 1157155131Srwatson __raw_readl(pcdev->base + CISR)); 1158155131Srwatson 1159155131Srwatson /* Reset the FIFOs */ 1160155131Srwatson cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; 1161155131Srwatson __raw_writel(cifr, pcdev->base + CIFR); 1162155131Srwatson 1163155131Srwatson pcdev->active = list_first_entry(&pcdev->capture, 1164155131Srwatson struct pxa_buffer, queue); 1165155131Srwatson buf = pcdev->active; 1166155131Srwatson pxa_video_buf_set_actdma(pcdev, buf); 1167155131Srwatson 1168155131Srwatson pxa_dma_start_channels(pcdev); 1169155131Srwatson} 1170155131Srwatson 1171155131Srwatsonstatic irqreturn_t pxa_camera_irq(int irq, void *data) 1172155131Srwatson{ 1173155131Srwatson struct pxa_camera_dev *pcdev = data; 1174155131Srwatson unsigned long status, cicr0; 1175155131Srwatson 1176155131Srwatson status = __raw_readl(pcdev->base + CISR); 1177155131Srwatson dev_dbg(pcdev_to_dev(pcdev), 1178159248Srwatson "Camera interrupt status 0x%lx\n", status); 1179155131Srwatson 1180155131Srwatson if (!status) 1181155131Srwatson return IRQ_NONE; 1182155131Srwatson 1183155131Srwatson __raw_writel(status, pcdev->base + CISR); 1184155131Srwatson 1185155131Srwatson if (status & CISR_EOF) { 1186155131Srwatson cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; 1187168777Srwatson __raw_writel(cicr0, pcdev->base + CICR0); 1188168777Srwatson tasklet_schedule(&pcdev->task_eof); 1189155131Srwatson } 1190168777Srwatson 1191168777Srwatson return IRQ_HANDLED; 1192168777Srwatson} 1193168777Srwatson 1194168777Srwatsonstatic void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev, 1195168777Srwatson unsigned long flags, __u32 pixfmt) 1196168777Srwatson{ 1197168777Srwatson unsigned long dw, bpp; 1198168777Srwatson u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top; 1199168777Srwatson int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top); 1200168777Srwatson 1201168777Srwatson if (ret < 0) 1202168777Srwatson y_skip_top = 0; 1203168777Srwatson 1204168777Srwatson /* 1205168777Srwatson * Datawidth is now guaranteed to be equal to one of the three values. 1206168777Srwatson * We fix bit-per-pixel equal to data-width... 1207155131Srwatson */ 1208155131Srwatson switch (pcdev->current_fmt->host_fmt->bits_per_sample) { 1209155131Srwatson case 10: 1210155131Srwatson dw = 4; 1211155131Srwatson bpp = 0x40; 1212155131Srwatson break; 1213155131Srwatson case 9: 1214155131Srwatson dw = 3; 1215155131Srwatson bpp = 0x20; 1216155131Srwatson break; 1217155131Srwatson default: 1218155131Srwatson /* 1219155131Srwatson * Actually it can only be 8 now, 1220155131Srwatson * default is just to silence compiler warnings 1221155131Srwatson */ 1222155131Srwatson case 8: 1223155131Srwatson dw = 2; 1224155131Srwatson bpp = 0; 1225155131Srwatson } 1226155131Srwatson 1227155131Srwatson if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) 1228155131Srwatson cicr4 |= CICR4_PCLK_EN; 1229155131Srwatson if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) 1230155131Srwatson cicr4 |= CICR4_MCLK_EN; 1231155131Srwatson if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) 1232155131Srwatson cicr4 |= CICR4_PCP; 1233155131Srwatson if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) 1234155131Srwatson cicr4 |= CICR4_HSP; 1235155131Srwatson if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) 1236155131Srwatson cicr4 |= CICR4_VSP; 1237155131Srwatson 1238155131Srwatson cicr0 = __raw_readl(pcdev->base + CICR0); 1239159985Srwatson if (cicr0 & CICR0_ENB) 1240159985Srwatson __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); 1241159985Srwatson 1242159985Srwatson cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw; 1243159985Srwatson 1244159985Srwatson switch (pixfmt) { 1245159985Srwatson case V4L2_PIX_FMT_YUV422P: 1246159985Srwatson pcdev->channels = 3; 1247159985Srwatson cicr1 |= CICR1_YCBCR_F; 1248159985Srwatson /* 1249155131Srwatson * Normally, pxa bus wants as input UYVY format. We allow all 1250155131Srwatson * reorderings of the YUV422 format, as no processing is done, 1251155131Srwatson * and the YUV stream is just passed through without any 1252155131Srwatson * transformation. Note that UYVY is the only format that 1253155131Srwatson * should be used if pxa framebuffer Overlay2 is used. 1254155131Srwatson */ 1255155131Srwatson fallthrough; 1256155131Srwatson case V4L2_PIX_FMT_UYVY: 1257155131Srwatson case V4L2_PIX_FMT_VYUY: 1258155131Srwatson case V4L2_PIX_FMT_YUYV: 1259155131Srwatson case V4L2_PIX_FMT_YVYU: 1260155131Srwatson cicr1 |= CICR1_COLOR_SP_VAL(2); 1261155131Srwatson break; 1262168777Srwatson case V4L2_PIX_FMT_RGB555: 1263168777Srwatson cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) | 1264168777Srwatson CICR1_TBIT | CICR1_COLOR_SP_VAL(1); 1265168777Srwatson break; 1266155131Srwatson case V4L2_PIX_FMT_RGB565: 1267155131Srwatson cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2); 1268155131Srwatson break; 1269155131Srwatson } 1270155131Srwatson 1271155131Srwatson cicr2 = 0; 1272155131Srwatson cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) | 1273155131Srwatson CICR3_BFW_VAL(min((u32)255, y_skip_top)); 1274168777Srwatson cicr4 |= pcdev->mclk_divisor; 1275168777Srwatson 1276155131Srwatson __raw_writel(cicr1, pcdev->base + CICR1); 1277168777Srwatson __raw_writel(cicr2, pcdev->base + CICR2); 1278168777Srwatson __raw_writel(cicr3, pcdev->base + CICR3); 1279168777Srwatson __raw_writel(cicr4, pcdev->base + CICR4); 1280168777Srwatson 1281168777Srwatson /* CIF interrupts are not used, only DMA */ 1282168777Srwatson cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ? 1283168777Srwatson CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); 1284168777Srwatson cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; 1285168777Srwatson __raw_writel(cicr0, pcdev->base + CICR0); 1286168777Srwatson} 1287168777Srwatson 1288168777Srwatson/* 1289168777Srwatson * Videobuf2 section 1290168777Srwatson */ 1291168777Srwatsonstatic void pxa_buffer_cleanup(struct pxa_buffer *buf) 1292168777Srwatson{ 1293168777Srwatson int i; 1294168777Srwatson 1295168777Srwatson for (i = 0; i < 3 && buf->descs[i]; i++) { 1296168777Srwatson dmaengine_desc_free(buf->descs[i]); 1297168777Srwatson kfree(buf->sg[i]); 1298168777Srwatson buf->descs[i] = NULL; 1299168777Srwatson buf->sg[i] = NULL; 1300168777Srwatson buf->sg_len[i] = 0; 1301168777Srwatson buf->plane_sizes[i] = 0; 1302168777Srwatson } 1303168777Srwatson buf->nb_planes = 0; 1304168777Srwatson} 1305168777Srwatson 1306168777Srwatsonstatic int pxa_buffer_init(struct pxa_camera_dev *pcdev, 1307168777Srwatson struct pxa_buffer *buf) 1308155131Srwatson{ 1309155131Srwatson struct vb2_buffer *vb = &buf->vbuf.vb2_buf; 1310155131Srwatson struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0); 1311155131Srwatson int nb_channels = pcdev->channels; 1312155131Srwatson int i, ret = 0; 1313155131Srwatson unsigned long size = vb2_plane_size(vb, 0); 1314155131Srwatson 1315155131Srwatson switch (nb_channels) { 1316155131Srwatson case 1: 1317155131Srwatson buf->plane_sizes[0] = size; 1318155131Srwatson break; 1319156283Srwatson case 3: 1320155131Srwatson buf->plane_sizes[0] = size / 2; 1321185573Srwatson buf->plane_sizes[1] = size / 4; 1322185573Srwatson buf->plane_sizes[2] = size / 4; 1323155131Srwatson break; 1324155131Srwatson default: 1325155131Srwatson return -EINVAL; 1326155131Srwatson } 1327155131Srwatson buf->nb_planes = nb_channels; 1328195740Srwatson 1329155131Srwatson ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels, 1330195740Srwatson buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL); 1331195740Srwatson if (ret < 0) { 1332195740Srwatson dev_err(pcdev_to_dev(pcdev), 1333195740Srwatson "sg_split failed: %d\n", ret); 1334195740Srwatson return ret; 1335195740Srwatson } 1336195740Srwatson for (i = 0; i < nb_channels; i++) { 1337195740Srwatson ret = pxa_init_dma_channel(pcdev, buf, i, 1338195740Srwatson buf->sg[i], buf->sg_len[i]); 1339195740Srwatson if (ret) { 1340195740Srwatson pxa_buffer_cleanup(buf); 1341195740Srwatson return ret; 1342195740Srwatson } 1343243750Srwatson } 1344195740Srwatson INIT_LIST_HEAD(&buf->queue); 1345243750Srwatson 1346155131Srwatson return ret; 1347195740Srwatson} 1348195740Srwatson 1349155131Srwatsonstatic void pxac_vb2_cleanup(struct vb2_buffer *vb) 1350155131Srwatson{ 1351155131Srwatson struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); 1352155131Srwatson struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); 1353155131Srwatson 1354155131Srwatson dev_dbg(pcdev_to_dev(pcdev), 1355155131Srwatson "%s(vb=%p)\n", __func__, vb); 1356155131Srwatson pxa_buffer_cleanup(buf); 1357155131Srwatson} 1358161818Srwatson 1359155131Srwatsonstatic void pxac_vb2_queue(struct vb2_buffer *vb) 1360155131Srwatson{ 1361155131Srwatson struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); 1362155131Srwatson struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); 1363155131Srwatson 1364155131Srwatson dev_dbg(pcdev_to_dev(pcdev), 1365155131Srwatson "%s(vb=%p) nb_channels=%d size=%lu active=%p\n", 1366161630Srwatson __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0), 1367155131Srwatson pcdev->active); 1368155131Srwatson 1369155131Srwatson list_add_tail(&buf->queue, &pcdev->capture); 1370155131Srwatson 1371155131Srwatson pxa_dma_add_tail_buf(pcdev, buf); 1372155131Srwatson} 1373155131Srwatson 1374161630Srwatson/* 1375155131Srwatson * Please check the DMA prepared buffer structure in : 1376155131Srwatson * Documentation/driver-api/media/drivers/pxa_camera.rst 1377155131Srwatson * Please check also in pxa_camera_check_link_miss() to understand why DMA chain 1378155131Srwatson * modification while DMA chain is running will work anyway. 1379155131Srwatson */ 1380155131Srwatsonstatic int pxac_vb2_prepare(struct vb2_buffer *vb) 1381155131Srwatson{ 1382155131Srwatson struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); 1383155131Srwatson struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); 1384155131Srwatson int ret = 0; 1385161630Srwatson#ifdef DEBUG 1386155131Srwatson int i; 1387155131Srwatson#endif 1388155131Srwatson 1389155131Srwatson switch (pcdev->channels) { 1390155131Srwatson case 1: 1391155131Srwatson case 3: 1392155131Srwatson vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage); 1393155131Srwatson break; 1394155131Srwatson default: 1395155131Srwatson return -EINVAL; 1396155131Srwatson } 1397155131Srwatson 1398161818Srwatson dev_dbg(pcdev_to_dev(pcdev), 1399155131Srwatson "%s (vb=%p) nb_channels=%d size=%lu\n", 1400155131Srwatson __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0)); 1401155131Srwatson 1402155131Srwatson WARN_ON(!pcdev->current_fmt); 1403155131Srwatson 1404155131Srwatson#ifdef DEBUG 1405155131Srwatson /* 1406161630Srwatson * This can be useful if you want to see if we actually fill 1407155131Srwatson * the buffer with something 1408155131Srwatson */ 1409155131Srwatson for (i = 0; i < vb->num_planes; i++) 1410155131Srwatson memset((void *)vb2_plane_vaddr(vb, i), 1411155131Srwatson 0xaa, vb2_get_plane_payload(vb, i)); 1412155131Srwatson#endif 1413155131Srwatson 1414161630Srwatson /* 1415155131Srwatson * I think, in buf_prepare you only have to protect global data, 1416155131Srwatson * the actual buffer is yours 1417155131Srwatson */ 1418155131Srwatson buf->inwork = 0; 1419155131Srwatson pxa_video_buf_set_actdma(pcdev, buf); 1420155131Srwatson 1421155131Srwatson return ret; 1422155131Srwatson} 1423155131Srwatson 1424155131Srwatsonstatic int pxac_vb2_init(struct vb2_buffer *vb) 1425161630Srwatson{ 1426155131Srwatson struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); 1427155131Srwatson struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); 1428155131Srwatson 1429155131Srwatson dev_dbg(pcdev_to_dev(pcdev), 1430155131Srwatson "%s(nb_channels=%d)\n", 1431155131Srwatson __func__, pcdev->channels); 1432155131Srwatson 1433155131Srwatson return pxa_buffer_init(pcdev, buf); 1434186647Srwatson} 1435186647Srwatson 1436186647Srwatsonstatic int pxac_vb2_queue_setup(struct vb2_queue *vq, 1437186647Srwatson unsigned int *nbufs, 1438186647Srwatson unsigned int *num_planes, unsigned int sizes[], 1439186647Srwatson struct device *alloc_devs[]) 1440186647Srwatson{ 1441186647Srwatson struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq); 1442186647Srwatson int size = pcdev->current_pix.sizeimage; 1443186647Srwatson 1444186647Srwatson dev_dbg(pcdev_to_dev(pcdev), 1445186647Srwatson "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n", 1446186647Srwatson __func__, vq, *nbufs, *num_planes, size); 1447186647Srwatson /* 1448186647Srwatson * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P 1449186647Srwatson * format, even if there are 3 planes Y, U and V, we reply there is only 1450186647Srwatson * one plane, containing Y, U and V data, one after the other. 1451186647Srwatson */ 1452186647Srwatson if (*num_planes) 1453186647Srwatson return sizes[0] < size ? -EINVAL : 0; 1454186647Srwatson 1455186647Srwatson *num_planes = 1; 1456186647Srwatson switch (pcdev->channels) { 1457155131Srwatson case 1: 1458155131Srwatson case 3: 1459155131Srwatson sizes[0] = size; 1460155131Srwatson break; 1461155131Srwatson default: 1462155131Srwatson return -EINVAL; 1463155131Srwatson } 1464155131Srwatson 1465159248Srwatson if (!*nbufs) 1466155131Srwatson *nbufs = 1; 1467155131Srwatson 1468155131Srwatson return 0; 1469155131Srwatson} 1470155131Srwatson 1471155131Srwatsonstatic int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count) 1472155131Srwatson{ 1473155131Srwatson struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq); 1474155131Srwatson 1475155131Srwatson dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n", 1476155131Srwatson __func__, count, pcdev->active); 1477155131Srwatson 1478155131Srwatson pcdev->buf_sequence = 0; 1479161630Srwatson if (!pcdev->active) 1480155131Srwatson pxa_camera_start_capture(pcdev); 1481155131Srwatson 1482155131Srwatson return 0; 1483155131Srwatson} 1484155131Srwatson 1485155131Srwatsonstatic void pxac_vb2_stop_streaming(struct vb2_queue *vq) 1486155131Srwatson{ 1487155131Srwatson struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq); 1488155131Srwatson struct pxa_buffer *buf, *tmp; 1489155131Srwatson 1490155131Srwatson dev_dbg(pcdev_to_dev(pcdev), "%s active=%p\n", 1491185573Srwatson __func__, pcdev->active); 1492185573Srwatson pxa_camera_stop_capture(pcdev); 1493185573Srwatson 1494185573Srwatson list_for_each_entry_safe(buf, tmp, &pcdev->capture, queue) 1495185573Srwatson pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_ERROR); 1496185573Srwatson} 1497185573Srwatson 1498185573Srwatsonstatic const struct vb2_ops pxac_vb2_ops = { 1499185573Srwatson .queue_setup = pxac_vb2_queue_setup, 1500185573Srwatson .buf_init = pxac_vb2_init, 1501185573Srwatson .buf_prepare = pxac_vb2_prepare, 1502168777Srwatson .buf_queue = pxac_vb2_queue, 1503185573Srwatson .buf_cleanup = pxac_vb2_cleanup, 1504185573Srwatson .start_streaming = pxac_vb2_start_streaming, 1505185573Srwatson .stop_streaming = pxac_vb2_stop_streaming, 1506185573Srwatson .wait_prepare = vb2_ops_wait_prepare, 1507185573Srwatson .wait_finish = vb2_ops_wait_finish, 1508186647Srwatson}; 1509186647Srwatson 1510185573Srwatsonstatic int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev) 1511186647Srwatson{ 1512185573Srwatson int ret; 1513185573Srwatson struct vb2_queue *vq = &pcdev->vb2_vq; 1514185573Srwatson 1515185573Srwatson memset(vq, 0, sizeof(*vq)); 1516185573Srwatson vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 1517243750Srwatson vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; 1518185573Srwatson vq->drv_priv = pcdev; 1519185573Srwatson vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1520185573Srwatson vq->buf_struct_size = sizeof(struct pxa_buffer); 1521185573Srwatson vq->dev = pcdev->v4l2_dev.dev; 1522185573Srwatson 1523185573Srwatson vq->ops = &pxac_vb2_ops; 1524185573Srwatson vq->mem_ops = &vb2_dma_sg_memops; 1525185573Srwatson vq->lock = &pcdev->mlock; 1526185573Srwatson 1527185573Srwatson ret = vb2_queue_init(vq); 1528185573Srwatson dev_dbg(pcdev_to_dev(pcdev), 1529185573Srwatson "vb2_queue_init(vq=%p): %d\n", vq, ret); 1530185573Srwatson 1531185573Srwatson return ret; 1532185573Srwatson} 1533185573Srwatson 1534185573Srwatson/* 1535185573Srwatson * Video ioctls section 1536243750Srwatson */ 1537185573Srwatsonstatic int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev) 1538185573Srwatson{ 1539185573Srwatson unsigned int bus_width = pcdev->current_fmt->host_fmt->bits_per_sample; 1540168777Srwatson struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; 1541168777Srwatson u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc; 1542168777Srwatson int mbus_config; 1543168777Srwatson int ret; 1544168777Srwatson 1545168777Srwatson if (!((1 << (bus_width - 1)) & pcdev->width_flags)) { 1546168777Srwatson dev_err(pcdev_to_dev(pcdev), "Unsupported bus width %u", 1547168777Srwatson bus_width); 1548168777Srwatson return -EINVAL; 1549168777Srwatson } 1550168777Srwatson 1551168777Srwatson pcdev->channels = 1; 1552168777Srwatson 1553168777Srwatson /* Make choices, based on platform preferences */ 1554168777Srwatson mbus_config = 0; 1555168777Srwatson if (pcdev->platform_flags & PXA_CAMERA_MASTER) 1556168777Srwatson mbus_config |= V4L2_MBUS_MASTER; 1557168777Srwatson else 1558168777Srwatson mbus_config |= V4L2_MBUS_SLAVE; 1559168777Srwatson 1560168777Srwatson if (pcdev->platform_flags & PXA_CAMERA_HSP) 1561168777Srwatson mbus_config |= V4L2_MBUS_HSYNC_ACTIVE_HIGH; 1562168777Srwatson else 1563168777Srwatson mbus_config |= V4L2_MBUS_HSYNC_ACTIVE_LOW; 1564168777Srwatson 1565168777Srwatson if (pcdev->platform_flags & PXA_CAMERA_VSP) 1566159248Srwatson mbus_config |= V4L2_MBUS_VSYNC_ACTIVE_HIGH; 1567185573Srwatson else 1568155131Srwatson mbus_config |= V4L2_MBUS_VSYNC_ACTIVE_LOW; 1569185573Srwatson 1570185573Srwatson if (pcdev->platform_flags & PXA_CAMERA_PCP) 1571185573Srwatson mbus_config |= V4L2_MBUS_PCLK_SAMPLE_RISING; 1572185573Srwatson else 1573185573Srwatson mbus_config |= V4L2_MBUS_PCLK_SAMPLE_FALLING; 1574185573Srwatson mbus_config |= V4L2_MBUS_DATA_ACTIVE_HIGH; 1575185573Srwatson 1576191273Srwatson ret = sensor_call(pcdev, pad, get_mbus_config, 0, &cfg); 1577185573Srwatson if (ret < 0 && ret != -ENOIOCTLCMD) { 1578185573Srwatson dev_err(pcdev_to_dev(pcdev), 1579185573Srwatson "Failed to call get_mbus_config: %d\n", ret); 1580185573Srwatson return ret; 1581185573Srwatson } 1582185573Srwatson 1583185573Srwatson /* 1584185573Srwatson * If the media bus configuration of the sensor differs, make sure it 1585185573Srwatson * is supported by the platform. 1586159248Srwatson * 1587159248Srwatson * PXA does not support V4L2_MBUS_DATA_ACTIVE_LOW and the bus mastering 1588159248Srwatson * roles should match. 1589159248Srwatson */ 1590159248Srwatson if (cfg.bus.parallel.flags != mbus_config) { 1591159248Srwatson unsigned int pxa_mbus_role = mbus_config & (V4L2_MBUS_MASTER | 1592159248Srwatson V4L2_MBUS_SLAVE); 1593159248Srwatson unsigned int flags = cfg.bus.parallel.flags; 1594159248Srwatson 1595159248Srwatson if (pxa_mbus_role != (flags & (V4L2_MBUS_MASTER | 1596155131Srwatson V4L2_MBUS_SLAVE))) { 1597155131Srwatson dev_err(pcdev_to_dev(pcdev), 1598155131Srwatson "Unsupported mbus configuration: bus mastering\n"); 1599168777Srwatson return -EINVAL; 1600155131Srwatson } 1601168777Srwatson 1602168777Srwatson if (flags & V4L2_MBUS_DATA_ACTIVE_LOW) { 1603168777Srwatson dev_err(pcdev_to_dev(pcdev), 1604155131Srwatson "Unsupported mbus configuration: DATA_ACTIVE_LOW\n"); 1605155131Srwatson return -EINVAL; 1606155131Srwatson } 1607155131Srwatson } 1608155131Srwatson 1609155131Srwatson pxa_camera_setup_cicr(pcdev, cfg.bus.parallel.flags, pixfmt); 1610155131Srwatson 1611155131Srwatson return 0; 1612155131Srwatson} 1613185573Srwatson 1614185573Srwatsonstatic const struct pxa_mbus_pixelfmt pxa_camera_formats[] = { 1615185573Srwatson { 1616185573Srwatson .fourcc = V4L2_PIX_FMT_YUV422P, 1617185573Srwatson .name = "Planar YUV422 16 bit", 1618185573Srwatson .bits_per_sample = 8, 1619185573Srwatson .packing = PXA_MBUS_PACKING_2X8_PADHI, 1620185573Srwatson .order = PXA_MBUS_ORDER_LE, 1621185573Srwatson .layout = PXA_MBUS_LAYOUT_PLANAR_2Y_U_V, 1622185573Srwatson }, 1623155131Srwatson}; 1624155131Srwatson 1625155131Srwatson/* This will be corrected as we get more formats */ 1626155131Srwatsonstatic bool pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt *fmt) 1627155131Srwatson{ 1628155131Srwatson return fmt->packing == PXA_MBUS_PACKING_NONE || 1629155131Srwatson (fmt->bits_per_sample == 8 && 1630155131Srwatson fmt->packing == PXA_MBUS_PACKING_2X8_PADHI) || 1631155131Srwatson (fmt->bits_per_sample > 8 && 1632155131Srwatson fmt->packing == PXA_MBUS_PACKING_EXTEND16); 1633186647Srwatson} 1634155131Srwatson 1635155131Srwatsonstatic int pxa_camera_get_formats(struct v4l2_device *v4l2_dev, 1636155131Srwatson unsigned int idx, 1637155131Srwatson struct pxa_camera_format_xlate *xlate) 1638155131Srwatson{ 1639155131Srwatson struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev); 1640155131Srwatson int formats = 0, ret; 1641155131Srwatson struct v4l2_subdev_mbus_code_enum code = { 1642155131Srwatson .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1643155131Srwatson .index = idx, 1644155131Srwatson }; 1645155131Srwatson const struct pxa_mbus_pixelfmt *fmt; 1646 1647 ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code); 1648 if (ret < 0) 1649 /* No more formats */ 1650 return 0; 1651 1652 fmt = pxa_mbus_get_fmtdesc(code.code); 1653 if (!fmt) { 1654 dev_err(pcdev_to_dev(pcdev), 1655 "Invalid format code #%u: %d\n", idx, code.code); 1656 return 0; 1657 } 1658 1659 switch (code.code) { 1660 case MEDIA_BUS_FMT_UYVY8_2X8: 1661 formats++; 1662 if (xlate) { 1663 xlate->host_fmt = &pxa_camera_formats[0]; 1664 xlate->code = code.code; 1665 xlate++; 1666 dev_dbg(pcdev_to_dev(pcdev), 1667 "Providing format %s using code %d\n", 1668 pxa_camera_formats[0].name, code.code); 1669 } 1670 fallthrough; 1671 case MEDIA_BUS_FMT_VYUY8_2X8: 1672 case MEDIA_BUS_FMT_YUYV8_2X8: 1673 case MEDIA_BUS_FMT_YVYU8_2X8: 1674 case MEDIA_BUS_FMT_RGB565_2X8_LE: 1675 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: 1676 if (xlate) 1677 dev_dbg(pcdev_to_dev(pcdev), 1678 "Providing format %s packed\n", 1679 fmt->name); 1680 break; 1681 default: 1682 if (!pxa_camera_packing_supported(fmt)) 1683 return 0; 1684 if (xlate) 1685 dev_dbg(pcdev_to_dev(pcdev), 1686 "Providing format %s in pass-through mode\n", 1687 fmt->name); 1688 break; 1689 } 1690 1691 /* Generic pass-through */ 1692 formats++; 1693 if (xlate) { 1694 xlate->host_fmt = fmt; 1695 xlate->code = code.code; 1696 xlate++; 1697 } 1698 1699 return formats; 1700} 1701 1702static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev) 1703{ 1704 struct pxa_camera_format_xlate *xlate; 1705 1706 xlate = pxa_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor, 1707 pxa_camera_get_formats); 1708 if (IS_ERR(xlate)) 1709 return PTR_ERR(xlate); 1710 1711 pcdev->user_formats = xlate; 1712 return 0; 1713} 1714 1715static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev) 1716{ 1717 kfree(pcdev->user_formats); 1718} 1719 1720static int pxa_camera_check_frame(u32 width, u32 height) 1721{ 1722 /* limit to pxa hardware capabilities */ 1723 return height < 32 || height > 2048 || width < 48 || width > 2048 || 1724 (width & 0x01); 1725} 1726 1727#ifdef CONFIG_VIDEO_ADV_DEBUG 1728static int pxac_vidioc_g_register(struct file *file, void *priv, 1729 struct v4l2_dbg_register *reg) 1730{ 1731 struct pxa_camera_dev *pcdev = video_drvdata(file); 1732 1733 if (reg->reg > CIBR2) 1734 return -ERANGE; 1735 1736 reg->val = __raw_readl(pcdev->base + reg->reg); 1737 reg->size = sizeof(__u32); 1738 return 0; 1739} 1740 1741static int pxac_vidioc_s_register(struct file *file, void *priv, 1742 const struct v4l2_dbg_register *reg) 1743{ 1744 struct pxa_camera_dev *pcdev = video_drvdata(file); 1745 1746 if (reg->reg > CIBR2) 1747 return -ERANGE; 1748 if (reg->size != sizeof(__u32)) 1749 return -EINVAL; 1750 __raw_writel(reg->val, pcdev->base + reg->reg); 1751 return 0; 1752} 1753#endif 1754 1755static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void *priv, 1756 struct v4l2_fmtdesc *f) 1757{ 1758 struct pxa_camera_dev *pcdev = video_drvdata(filp); 1759 const struct pxa_mbus_pixelfmt *format; 1760 unsigned int idx; 1761 1762 for (idx = 0; pcdev->user_formats[idx].code; idx++); 1763 if (f->index >= idx) 1764 return -EINVAL; 1765 1766 format = pcdev->user_formats[f->index].host_fmt; 1767 f->pixelformat = format->fourcc; 1768 return 0; 1769} 1770 1771static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv, 1772 struct v4l2_format *f) 1773{ 1774 struct pxa_camera_dev *pcdev = video_drvdata(filp); 1775 struct v4l2_pix_format *pix = &f->fmt.pix; 1776 1777 pix->width = pcdev->current_pix.width; 1778 pix->height = pcdev->current_pix.height; 1779 pix->bytesperline = pcdev->current_pix.bytesperline; 1780 pix->sizeimage = pcdev->current_pix.sizeimage; 1781 pix->field = pcdev->current_pix.field; 1782 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc; 1783 pix->colorspace = pcdev->current_pix.colorspace; 1784 dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n", 1785 pcdev->current_fmt->host_fmt->fourcc); 1786 return 0; 1787} 1788 1789static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv, 1790 struct v4l2_format *f) 1791{ 1792 struct pxa_camera_dev *pcdev = video_drvdata(filp); 1793 const struct pxa_camera_format_xlate *xlate; 1794 struct v4l2_pix_format *pix = &f->fmt.pix; 1795 struct v4l2_subdev_pad_config pad_cfg; 1796 struct v4l2_subdev_state pad_state = { 1797 .pads = &pad_cfg, 1798 }; 1799 struct v4l2_subdev_format format = { 1800 .which = V4L2_SUBDEV_FORMAT_TRY, 1801 }; 1802 struct v4l2_mbus_framefmt *mf = &format.format; 1803 __u32 pixfmt = pix->pixelformat; 1804 int ret; 1805 1806 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt); 1807 if (!xlate) { 1808 dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt); 1809 return -EINVAL; 1810 } 1811 1812 /* 1813 * Limit to pxa hardware capabilities. YUV422P planar format requires 1814 * images size to be a multiple of 16 bytes. If not, zeros will be 1815 * inserted between Y and U planes, and U and V planes, which violates 1816 * the YUV422P standard. 1817 */ 1818 v4l_bound_align_image(&pix->width, 48, 2048, 1, 1819 &pix->height, 32, 2048, 0, 1820 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0); 1821 1822 v4l2_fill_mbus_format(mf, pix, xlate->code); 1823 ret = sensor_call(pcdev, pad, set_fmt, &pad_state, &format); 1824 if (ret < 0) 1825 return ret; 1826 1827 v4l2_fill_pix_format(pix, mf); 1828 1829 /* Only progressive video supported so far */ 1830 switch (mf->field) { 1831 case V4L2_FIELD_ANY: 1832 case V4L2_FIELD_NONE: 1833 pix->field = V4L2_FIELD_NONE; 1834 break; 1835 default: 1836 /* TODO: support interlaced at least in pass-through mode */ 1837 dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n", 1838 mf->field); 1839 return -EINVAL; 1840 } 1841 1842 ret = pxa_mbus_bytes_per_line(pix->width, xlate->host_fmt); 1843 if (ret < 0) 1844 return ret; 1845 1846 pix->bytesperline = ret; 1847 ret = pxa_mbus_image_size(xlate->host_fmt, pix->bytesperline, 1848 pix->height); 1849 if (ret < 0) 1850 return ret; 1851 1852 pix->sizeimage = ret; 1853 return 0; 1854} 1855 1856static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv, 1857 struct v4l2_format *f) 1858{ 1859 struct pxa_camera_dev *pcdev = video_drvdata(filp); 1860 const struct pxa_camera_format_xlate *xlate; 1861 struct v4l2_pix_format *pix = &f->fmt.pix; 1862 struct v4l2_subdev_format format = { 1863 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1864 }; 1865 unsigned long flags; 1866 int ret, is_busy; 1867 1868 dev_dbg(pcdev_to_dev(pcdev), 1869 "s_fmt_vid_cap(pix=%dx%d:%x)\n", 1870 pix->width, pix->height, pix->pixelformat); 1871 1872 spin_lock_irqsave(&pcdev->lock, flags); 1873 is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq); 1874 spin_unlock_irqrestore(&pcdev->lock, flags); 1875 1876 if (is_busy) 1877 return -EBUSY; 1878 1879 ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f); 1880 if (ret) 1881 return ret; 1882 1883 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, 1884 pix->pixelformat); 1885 v4l2_fill_mbus_format(&format.format, pix, xlate->code); 1886 ret = sensor_call(pcdev, pad, set_fmt, NULL, &format); 1887 if (ret < 0) { 1888 dev_warn(pcdev_to_dev(pcdev), 1889 "Failed to configure for format %x\n", 1890 pix->pixelformat); 1891 } else if (pxa_camera_check_frame(pix->width, pix->height)) { 1892 dev_warn(pcdev_to_dev(pcdev), 1893 "Camera driver produced an unsupported frame %dx%d\n", 1894 pix->width, pix->height); 1895 return -EINVAL; 1896 } 1897 1898 pcdev->current_fmt = xlate; 1899 pcdev->current_pix = *pix; 1900 1901 ret = pxa_camera_set_bus_param(pcdev); 1902 return ret; 1903} 1904 1905static int pxac_vidioc_querycap(struct file *file, void *priv, 1906 struct v4l2_capability *cap) 1907{ 1908 strscpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info)); 1909 strscpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver)); 1910 strscpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); 1911 return 0; 1912} 1913 1914static int pxac_vidioc_enum_input(struct file *file, void *priv, 1915 struct v4l2_input *i) 1916{ 1917 if (i->index > 0) 1918 return -EINVAL; 1919 1920 i->type = V4L2_INPUT_TYPE_CAMERA; 1921 strscpy(i->name, "Camera", sizeof(i->name)); 1922 1923 return 0; 1924} 1925 1926static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i) 1927{ 1928 *i = 0; 1929 1930 return 0; 1931} 1932 1933static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i) 1934{ 1935 if (i > 0) 1936 return -EINVAL; 1937 1938 return 0; 1939} 1940 1941static int pxac_sensor_set_power(struct pxa_camera_dev *pcdev, int on) 1942{ 1943 int ret; 1944 1945 ret = sensor_call(pcdev, core, s_power, on); 1946 if (ret == -ENOIOCTLCMD) 1947 ret = 0; 1948 if (ret) { 1949 dev_warn(pcdev_to_dev(pcdev), 1950 "Failed to put subdevice in %s mode: %d\n", 1951 on ? "normal operation" : "power saving", ret); 1952 } 1953 1954 return ret; 1955} 1956 1957static int pxac_fops_camera_open(struct file *filp) 1958{ 1959 struct pxa_camera_dev *pcdev = video_drvdata(filp); 1960 int ret; 1961 1962 mutex_lock(&pcdev->mlock); 1963 ret = v4l2_fh_open(filp); 1964 if (ret < 0) 1965 goto out; 1966 1967 if (!v4l2_fh_is_singular_file(filp)) 1968 goto out; 1969 1970 ret = pxac_sensor_set_power(pcdev, 1); 1971 if (ret) 1972 v4l2_fh_release(filp); 1973out: 1974 mutex_unlock(&pcdev->mlock); 1975 return ret; 1976} 1977 1978static int pxac_fops_camera_release(struct file *filp) 1979{ 1980 struct pxa_camera_dev *pcdev = video_drvdata(filp); 1981 int ret; 1982 bool fh_singular; 1983 1984 mutex_lock(&pcdev->mlock); 1985 1986 fh_singular = v4l2_fh_is_singular_file(filp); 1987 1988 ret = _vb2_fop_release(filp, NULL); 1989 1990 if (fh_singular) 1991 ret = pxac_sensor_set_power(pcdev, 0); 1992 1993 mutex_unlock(&pcdev->mlock); 1994 1995 return ret; 1996} 1997 1998static const struct v4l2_file_operations pxa_camera_fops = { 1999 .owner = THIS_MODULE, 2000 .open = pxac_fops_camera_open, 2001 .release = pxac_fops_camera_release, 2002 .read = vb2_fop_read, 2003 .poll = vb2_fop_poll, 2004 .mmap = vb2_fop_mmap, 2005 .unlocked_ioctl = video_ioctl2, 2006}; 2007 2008static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = { 2009 .vidioc_querycap = pxac_vidioc_querycap, 2010 2011 .vidioc_enum_input = pxac_vidioc_enum_input, 2012 .vidioc_g_input = pxac_vidioc_g_input, 2013 .vidioc_s_input = pxac_vidioc_s_input, 2014 2015 .vidioc_enum_fmt_vid_cap = pxac_vidioc_enum_fmt_vid_cap, 2016 .vidioc_g_fmt_vid_cap = pxac_vidioc_g_fmt_vid_cap, 2017 .vidioc_s_fmt_vid_cap = pxac_vidioc_s_fmt_vid_cap, 2018 .vidioc_try_fmt_vid_cap = pxac_vidioc_try_fmt_vid_cap, 2019 2020 .vidioc_reqbufs = vb2_ioctl_reqbufs, 2021 .vidioc_create_bufs = vb2_ioctl_create_bufs, 2022 .vidioc_querybuf = vb2_ioctl_querybuf, 2023 .vidioc_qbuf = vb2_ioctl_qbuf, 2024 .vidioc_dqbuf = vb2_ioctl_dqbuf, 2025 .vidioc_expbuf = vb2_ioctl_expbuf, 2026 .vidioc_streamon = vb2_ioctl_streamon, 2027 .vidioc_streamoff = vb2_ioctl_streamoff, 2028#ifdef CONFIG_VIDEO_ADV_DEBUG 2029 .vidioc_g_register = pxac_vidioc_g_register, 2030 .vidioc_s_register = pxac_vidioc_s_register, 2031#endif 2032 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 2033 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 2034}; 2035 2036static const struct video_device pxa_camera_videodev_template = { 2037 .name = "pxa-camera", 2038 .minor = -1, 2039 .fops = &pxa_camera_fops, 2040 .ioctl_ops = &pxa_camera_ioctl_ops, 2041 .release = video_device_release_empty, 2042 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING, 2043}; 2044 2045static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier, 2046 struct v4l2_subdev *subdev, 2047 struct v4l2_async_connection *asd) 2048{ 2049 int err; 2050 struct v4l2_device *v4l2_dev = notifier->v4l2_dev; 2051 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev); 2052 struct video_device *vdev = &pcdev->vdev; 2053 struct v4l2_pix_format *pix = &pcdev->current_pix; 2054 struct v4l2_subdev_format format = { 2055 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 2056 }; 2057 struct v4l2_mbus_framefmt *mf = &format.format; 2058 2059 dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n", 2060 __func__); 2061 mutex_lock(&pcdev->mlock); 2062 *vdev = pxa_camera_videodev_template; 2063 vdev->v4l2_dev = v4l2_dev; 2064 vdev->lock = &pcdev->mlock; 2065 pcdev->sensor = subdev; 2066 pcdev->vdev.queue = &pcdev->vb2_vq; 2067 pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev; 2068 pcdev->vdev.ctrl_handler = subdev->ctrl_handler; 2069 video_set_drvdata(&pcdev->vdev, pcdev); 2070 2071 err = pxa_camera_build_formats(pcdev); 2072 if (err) { 2073 dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n", 2074 err); 2075 goto out; 2076 } 2077 2078 pcdev->current_fmt = pcdev->user_formats; 2079 pix->field = V4L2_FIELD_NONE; 2080 pix->width = DEFAULT_WIDTH; 2081 pix->height = DEFAULT_HEIGHT; 2082 pix->bytesperline = 2083 pxa_mbus_bytes_per_line(pix->width, 2084 pcdev->current_fmt->host_fmt); 2085 pix->sizeimage = 2086 pxa_mbus_image_size(pcdev->current_fmt->host_fmt, 2087 pix->bytesperline, pix->height); 2088 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc; 2089 v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code); 2090 2091 err = pxac_sensor_set_power(pcdev, 1); 2092 if (err) 2093 goto out; 2094 2095 err = sensor_call(pcdev, pad, set_fmt, NULL, &format); 2096 if (err) 2097 goto out_sensor_poweroff; 2098 2099 v4l2_fill_pix_format(pix, mf); 2100 pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n", 2101 __func__, pix->colorspace, pix->pixelformat); 2102 2103 err = pxa_camera_init_videobuf2(pcdev); 2104 if (err) 2105 goto out_sensor_poweroff; 2106 2107 err = video_register_device(&pcdev->vdev, VFL_TYPE_VIDEO, -1); 2108 if (err) { 2109 v4l2_err(v4l2_dev, "register video device failed: %d\n", err); 2110 pcdev->sensor = NULL; 2111 } else { 2112 dev_info(pcdev_to_dev(pcdev), 2113 "PXA Camera driver attached to camera %s\n", 2114 subdev->name); 2115 } 2116 2117out_sensor_poweroff: 2118 err = pxac_sensor_set_power(pcdev, 0); 2119out: 2120 mutex_unlock(&pcdev->mlock); 2121 return err; 2122} 2123 2124static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier, 2125 struct v4l2_subdev *subdev, 2126 struct v4l2_async_connection *asd) 2127{ 2128 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev); 2129 2130 mutex_lock(&pcdev->mlock); 2131 dev_info(pcdev_to_dev(pcdev), 2132 "PXA Camera driver detached from camera %s\n", 2133 subdev->name); 2134 2135 /* disable capture, disable interrupts */ 2136 __raw_writel(0x3ff, pcdev->base + CICR0); 2137 2138 /* Stop DMA engine */ 2139 pxa_dma_stop_channels(pcdev); 2140 2141 pxa_camera_destroy_formats(pcdev); 2142 2143 video_unregister_device(&pcdev->vdev); 2144 pcdev->sensor = NULL; 2145 2146 mutex_unlock(&pcdev->mlock); 2147} 2148 2149static const struct v4l2_async_notifier_operations pxa_camera_sensor_ops = { 2150 .bound = pxa_camera_sensor_bound, 2151 .unbind = pxa_camera_sensor_unbind, 2152}; 2153 2154/* 2155 * Driver probe, remove, suspend and resume operations 2156 */ 2157static int pxa_camera_suspend(struct device *dev) 2158{ 2159 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev); 2160 int i = 0, ret = 0; 2161 2162 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); 2163 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); 2164 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); 2165 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); 2166 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); 2167 2168 if (pcdev->sensor) 2169 ret = pxac_sensor_set_power(pcdev, 0); 2170 2171 return ret; 2172} 2173 2174static int pxa_camera_resume(struct device *dev) 2175{ 2176 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev); 2177 int i = 0, ret = 0; 2178 2179 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); 2180 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); 2181 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); 2182 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); 2183 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); 2184 2185 if (pcdev->sensor) { 2186 ret = pxac_sensor_set_power(pcdev, 1); 2187 } 2188 2189 /* Restart frame capture if active buffer exists */ 2190 if (!ret && pcdev->active) 2191 pxa_camera_start_capture(pcdev); 2192 2193 return ret; 2194} 2195 2196static int pxa_camera_pdata_from_dt(struct device *dev, 2197 struct pxa_camera_dev *pcdev) 2198{ 2199 u32 mclk_rate; 2200 struct v4l2_async_connection *asd; 2201 struct device_node *np = dev->of_node; 2202 struct v4l2_fwnode_endpoint ep = { .bus_type = 0 }; 2203 int err = of_property_read_u32(np, "clock-frequency", 2204 &mclk_rate); 2205 if (!err) { 2206 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN; 2207 pcdev->mclk = mclk_rate; 2208 } 2209 2210 np = of_graph_get_endpoint_by_regs(np, 0, -1); 2211 if (!np) { 2212 dev_err(dev, "could not find endpoint\n"); 2213 return -EINVAL; 2214 } 2215 2216 err = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep); 2217 if (err) { 2218 dev_err(dev, "could not parse endpoint\n"); 2219 goto out; 2220 } 2221 2222 switch (ep.bus.parallel.bus_width) { 2223 case 4: 2224 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4; 2225 break; 2226 case 5: 2227 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5; 2228 break; 2229 case 8: 2230 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8; 2231 break; 2232 case 9: 2233 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9; 2234 break; 2235 case 10: 2236 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; 2237 break; 2238 default: 2239 break; 2240 } 2241 2242 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER) 2243 pcdev->platform_flags |= PXA_CAMERA_MASTER; 2244 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 2245 pcdev->platform_flags |= PXA_CAMERA_HSP; 2246 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 2247 pcdev->platform_flags |= PXA_CAMERA_VSP; 2248 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 2249 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP; 2250 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) 2251 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN; 2252 2253 asd = v4l2_async_nf_add_fwnode_remote(&pcdev->notifier, 2254 of_fwnode_handle(np), 2255 struct v4l2_async_connection); 2256 if (IS_ERR(asd)) 2257 err = PTR_ERR(asd); 2258out: 2259 of_node_put(np); 2260 2261 return err; 2262} 2263 2264static int pxa_camera_probe(struct platform_device *pdev) 2265{ 2266 struct pxa_camera_dev *pcdev; 2267 struct resource *res; 2268 void __iomem *base; 2269 struct dma_slave_config config = { 2270 .src_addr_width = 0, 2271 .src_maxburst = 8, 2272 .direction = DMA_DEV_TO_MEM, 2273 }; 2274 int irq; 2275 int err = 0, i; 2276 2277 irq = platform_get_irq(pdev, 0); 2278 if (irq < 0) 2279 return -ENODEV; 2280 2281 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL); 2282 if (!pcdev) { 2283 dev_err(&pdev->dev, "Could not allocate pcdev\n"); 2284 return -ENOMEM; 2285 } 2286 2287 pcdev->clk = devm_clk_get(&pdev->dev, NULL); 2288 if (IS_ERR(pcdev->clk)) 2289 return PTR_ERR(pcdev->clk); 2290 2291 /* 2292 * Request the regions. 2293 */ 2294 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2295 if (IS_ERR(base)) 2296 return PTR_ERR(base); 2297 2298 pcdev->irq = irq; 2299 pcdev->base = base; 2300 2301 err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev); 2302 if (err) 2303 return err; 2304 2305 v4l2_async_nf_init(&pcdev->notifier, &pcdev->v4l2_dev); 2306 pcdev->res = res; 2307 pcdev->pdata = pdev->dev.platform_data; 2308 if (pcdev->pdata) { 2309 struct v4l2_async_connection *asd; 2310 2311 pcdev->platform_flags = pcdev->pdata->flags; 2312 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; 2313 asd = v4l2_async_nf_add_i2c(&pcdev->notifier, 2314 pcdev->pdata->sensor_i2c_adapter_id, 2315 pcdev->pdata->sensor_i2c_address, 2316 struct v4l2_async_connection); 2317 if (IS_ERR(asd)) 2318 err = PTR_ERR(asd); 2319 } else if (pdev->dev.of_node) { 2320 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev); 2321 } else { 2322 err = -ENODEV; 2323 } 2324 if (err < 0) 2325 goto exit_v4l2_device_unregister; 2326 2327 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | 2328 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { 2329 /* 2330 * Platform hasn't set available data widths. This is bad. 2331 * Warn and use a default. 2332 */ 2333 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available data widths, using default 10 bit\n"); 2334 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; 2335 } 2336 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8) 2337 pcdev->width_flags = 1 << 7; 2338 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9) 2339 pcdev->width_flags |= 1 << 8; 2340 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10) 2341 pcdev->width_flags |= 1 << 9; 2342 if (!pcdev->mclk) { 2343 dev_warn(&pdev->dev, 2344 "mclk == 0! Please, fix your platform data. Using default 20MHz\n"); 2345 pcdev->mclk = 20000000; 2346 } 2347 2348 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev); 2349 2350 INIT_LIST_HEAD(&pcdev->capture); 2351 spin_lock_init(&pcdev->lock); 2352 mutex_init(&pcdev->mlock); 2353 2354 /* request dma */ 2355 pcdev->dma_chans[0] = dma_request_chan(&pdev->dev, "CI_Y"); 2356 if (IS_ERR(pcdev->dma_chans[0])) { 2357 dev_err(&pdev->dev, "Can't request DMA for Y\n"); 2358 err = PTR_ERR(pcdev->dma_chans[0]); 2359 goto exit_notifier_cleanup; 2360 } 2361 2362 pcdev->dma_chans[1] = dma_request_chan(&pdev->dev, "CI_U"); 2363 if (IS_ERR(pcdev->dma_chans[1])) { 2364 dev_err(&pdev->dev, "Can't request DMA for U\n"); 2365 err = PTR_ERR(pcdev->dma_chans[1]); 2366 goto exit_free_dma_y; 2367 } 2368 2369 pcdev->dma_chans[2] = dma_request_chan(&pdev->dev, "CI_V"); 2370 if (IS_ERR(pcdev->dma_chans[2])) { 2371 dev_err(&pdev->dev, "Can't request DMA for V\n"); 2372 err = PTR_ERR(pcdev->dma_chans[2]); 2373 goto exit_free_dma_u; 2374 } 2375 2376 for (i = 0; i < 3; i++) { 2377 config.src_addr = pcdev->res->start + CIBR0 + i * 8; 2378 err = dmaengine_slave_config(pcdev->dma_chans[i], &config); 2379 if (err < 0) { 2380 dev_err(&pdev->dev, "dma slave config failed: %d\n", 2381 err); 2382 goto exit_free_dma; 2383 } 2384 } 2385 2386 tasklet_setup(&pcdev->task_eof, pxa_camera_eof); 2387 2388 pxa_camera_activate(pcdev); 2389 2390 platform_set_drvdata(pdev, pcdev); 2391 2392 err = pxa_camera_init_videobuf2(pcdev); 2393 if (err) 2394 goto exit_deactivate; 2395 2396 /* request irq */ 2397 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0, 2398 PXA_CAM_DRV_NAME, pcdev); 2399 if (err) { 2400 dev_err(&pdev->dev, "Camera interrupt register failed\n"); 2401 goto exit_deactivate; 2402 } 2403 2404 pcdev->notifier.ops = &pxa_camera_sensor_ops; 2405 err = v4l2_async_nf_register(&pcdev->notifier); 2406 if (err) 2407 goto exit_deactivate; 2408 2409 return 0; 2410exit_deactivate: 2411 pxa_camera_deactivate(pcdev); 2412 tasklet_kill(&pcdev->task_eof); 2413exit_free_dma: 2414 dma_release_channel(pcdev->dma_chans[2]); 2415exit_free_dma_u: 2416 dma_release_channel(pcdev->dma_chans[1]); 2417exit_free_dma_y: 2418 dma_release_channel(pcdev->dma_chans[0]); 2419exit_notifier_cleanup: 2420 v4l2_async_nf_cleanup(&pcdev->notifier); 2421exit_v4l2_device_unregister: 2422 v4l2_device_unregister(&pcdev->v4l2_dev); 2423 return err; 2424} 2425 2426static void pxa_camera_remove(struct platform_device *pdev) 2427{ 2428 struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev); 2429 2430 pxa_camera_deactivate(pcdev); 2431 tasklet_kill(&pcdev->task_eof); 2432 dma_release_channel(pcdev->dma_chans[0]); 2433 dma_release_channel(pcdev->dma_chans[1]); 2434 dma_release_channel(pcdev->dma_chans[2]); 2435 2436 v4l2_async_nf_unregister(&pcdev->notifier); 2437 v4l2_async_nf_cleanup(&pcdev->notifier); 2438 2439 v4l2_device_unregister(&pcdev->v4l2_dev); 2440 2441 dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); 2442} 2443 2444static const struct dev_pm_ops pxa_camera_pm = { 2445 .suspend = pxa_camera_suspend, 2446 .resume = pxa_camera_resume, 2447}; 2448 2449static const struct of_device_id pxa_camera_of_match[] = { 2450 { .compatible = "marvell,pxa270-qci", }, 2451 {}, 2452}; 2453MODULE_DEVICE_TABLE(of, pxa_camera_of_match); 2454 2455static struct platform_driver pxa_camera_driver = { 2456 .driver = { 2457 .name = PXA_CAM_DRV_NAME, 2458 .pm = &pxa_camera_pm, 2459 .of_match_table = pxa_camera_of_match, 2460 }, 2461 .probe = pxa_camera_probe, 2462 .remove_new = pxa_camera_remove, 2463}; 2464 2465module_platform_driver(pxa_camera_driver); 2466 2467MODULE_DESCRIPTION("PXA27x Camera Driver"); 2468MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); 2469MODULE_LICENSE("GPL"); 2470MODULE_VERSION(PXA_CAM_VERSION); 2471MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME); 2472