1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * rt5659.c -- RT5659/RT5658 ALSA SoC audio codec driver 4 * 5 * Copyright 2015 Realtek Semiconductor Corp. 6 * Author: Bard Liao <bardliao@realtek.com> 7 */ 8 9#include <linux/clk.h> 10#include <linux/module.h> 11#include <linux/moduleparam.h> 12#include <linux/init.h> 13#include <linux/delay.h> 14#include <linux/pm.h> 15#include <linux/i2c.h> 16#include <linux/platform_device.h> 17#include <linux/spi/spi.h> 18#include <linux/acpi.h> 19#include <linux/gpio/consumer.h> 20#include <sound/core.h> 21#include <sound/pcm.h> 22#include <sound/pcm_params.h> 23#include <sound/jack.h> 24#include <sound/soc.h> 25#include <sound/soc-dapm.h> 26#include <sound/initval.h> 27#include <sound/tlv.h> 28#include <sound/rt5659.h> 29 30#include "rl6231.h" 31#include "rt5659.h" 32 33static const struct reg_default rt5659_reg[] = { 34 { 0x0000, 0x0000 }, 35 { 0x0001, 0x4848 }, 36 { 0x0002, 0x8080 }, 37 { 0x0003, 0xc8c8 }, 38 { 0x0004, 0xc80a }, 39 { 0x0005, 0x0000 }, 40 { 0x0006, 0x0000 }, 41 { 0x0007, 0x0103 }, 42 { 0x0008, 0x0080 }, 43 { 0x0009, 0x0000 }, 44 { 0x000a, 0x0000 }, 45 { 0x000c, 0x0000 }, 46 { 0x000d, 0x0000 }, 47 { 0x000f, 0x0808 }, 48 { 0x0010, 0x3080 }, 49 { 0x0011, 0x4a00 }, 50 { 0x0012, 0x4e00 }, 51 { 0x0015, 0x42c1 }, 52 { 0x0016, 0x0000 }, 53 { 0x0018, 0x000b }, 54 { 0x0019, 0xafaf }, 55 { 0x001a, 0xafaf }, 56 { 0x001b, 0x0011 }, 57 { 0x001c, 0x2f2f }, 58 { 0x001d, 0x2f2f }, 59 { 0x001e, 0x2f2f }, 60 { 0x001f, 0x0000 }, 61 { 0x0020, 0x0000 }, 62 { 0x0021, 0x0000 }, 63 { 0x0022, 0x5757 }, 64 { 0x0023, 0x0039 }, 65 { 0x0026, 0xc060 }, 66 { 0x0027, 0xd8d8 }, 67 { 0x0029, 0x8080 }, 68 { 0x002a, 0xaaaa }, 69 { 0x002b, 0xaaaa }, 70 { 0x002c, 0x00af }, 71 { 0x002d, 0x0000 }, 72 { 0x002f, 0x1002 }, 73 { 0x0031, 0x5000 }, 74 { 0x0032, 0x0000 }, 75 { 0x0033, 0x0000 }, 76 { 0x0034, 0x0000 }, 77 { 0x0035, 0x0000 }, 78 { 0x0036, 0x0000 }, 79 { 0x003a, 0x0000 }, 80 { 0x003b, 0x0000 }, 81 { 0x003c, 0x007f }, 82 { 0x003d, 0x0000 }, 83 { 0x003e, 0x007f }, 84 { 0x0040, 0x0808 }, 85 { 0x0046, 0x001f }, 86 { 0x0047, 0x001f }, 87 { 0x0048, 0x0003 }, 88 { 0x0049, 0xe061 }, 89 { 0x004a, 0x0000 }, 90 { 0x004b, 0x031f }, 91 { 0x004d, 0x0000 }, 92 { 0x004e, 0x001f }, 93 { 0x004f, 0x0000 }, 94 { 0x0050, 0x001f }, 95 { 0x0052, 0xf000 }, 96 { 0x0053, 0x0111 }, 97 { 0x0054, 0x0064 }, 98 { 0x0055, 0x0080 }, 99 { 0x0056, 0xef0e }, 100 { 0x0057, 0xf0f0 }, 101 { 0x0058, 0xef0e }, 102 { 0x0059, 0xf0f0 }, 103 { 0x005a, 0xef0e }, 104 { 0x005b, 0xf0f0 }, 105 { 0x005c, 0xf000 }, 106 { 0x005d, 0x0000 }, 107 { 0x005e, 0x1f2c }, 108 { 0x005f, 0x1f2c }, 109 { 0x0060, 0x2717 }, 110 { 0x0061, 0x0000 }, 111 { 0x0062, 0x0000 }, 112 { 0x0063, 0x003e }, 113 { 0x0064, 0x0000 }, 114 { 0x0065, 0x0000 }, 115 { 0x0066, 0x0000 }, 116 { 0x0067, 0x0000 }, 117 { 0x006a, 0x0000 }, 118 { 0x006b, 0x0000 }, 119 { 0x006c, 0x0000 }, 120 { 0x006e, 0x0000 }, 121 { 0x006f, 0x0000 }, 122 { 0x0070, 0x8000 }, 123 { 0x0071, 0x8000 }, 124 { 0x0072, 0x8000 }, 125 { 0x0073, 0x1110 }, 126 { 0x0074, 0xfe00 }, 127 { 0x0075, 0x2409 }, 128 { 0x0076, 0x000a }, 129 { 0x0077, 0x00f0 }, 130 { 0x0078, 0x0000 }, 131 { 0x0079, 0x0000 }, 132 { 0x007a, 0x0123 }, 133 { 0x007b, 0x8003 }, 134 { 0x0080, 0x0000 }, 135 { 0x0081, 0x0000 }, 136 { 0x0082, 0x0000 }, 137 { 0x0083, 0x0000 }, 138 { 0x0084, 0x0000 }, 139 { 0x0085, 0x0000 }, 140 { 0x0086, 0x0008 }, 141 { 0x0087, 0x0000 }, 142 { 0x0088, 0x0000 }, 143 { 0x0089, 0x0000 }, 144 { 0x008a, 0x0000 }, 145 { 0x008b, 0x0000 }, 146 { 0x008c, 0x0003 }, 147 { 0x008e, 0x0000 }, 148 { 0x008f, 0x1000 }, 149 { 0x0090, 0x0646 }, 150 { 0x0091, 0x0c16 }, 151 { 0x0092, 0x0073 }, 152 { 0x0093, 0x0000 }, 153 { 0x0094, 0x0080 }, 154 { 0x0097, 0x0000 }, 155 { 0x0098, 0x0000 }, 156 { 0x0099, 0x0000 }, 157 { 0x009a, 0x0000 }, 158 { 0x009b, 0x0000 }, 159 { 0x009c, 0x007f }, 160 { 0x009d, 0x0000 }, 161 { 0x009e, 0x007f }, 162 { 0x009f, 0x0000 }, 163 { 0x00a0, 0x0060 }, 164 { 0x00a1, 0x90a1 }, 165 { 0x00ae, 0x2000 }, 166 { 0x00af, 0x0000 }, 167 { 0x00b0, 0x2000 }, 168 { 0x00b1, 0x0000 }, 169 { 0x00b2, 0x0000 }, 170 { 0x00b6, 0x0000 }, 171 { 0x00b7, 0x0000 }, 172 { 0x00b8, 0x0000 }, 173 { 0x00b9, 0x0000 }, 174 { 0x00ba, 0x0000 }, 175 { 0x00bb, 0x0000 }, 176 { 0x00be, 0x0000 }, 177 { 0x00bf, 0x0000 }, 178 { 0x00c0, 0x0000 }, 179 { 0x00c1, 0x0000 }, 180 { 0x00c2, 0x0000 }, 181 { 0x00c3, 0x0000 }, 182 { 0x00c4, 0x0003 }, 183 { 0x00c5, 0x0000 }, 184 { 0x00cb, 0xa02f }, 185 { 0x00cc, 0x0000 }, 186 { 0x00cd, 0x0e02 }, 187 { 0x00d6, 0x0000 }, 188 { 0x00d7, 0x2244 }, 189 { 0x00d9, 0x0809 }, 190 { 0x00da, 0x0000 }, 191 { 0x00db, 0x0008 }, 192 { 0x00dc, 0x00c0 }, 193 { 0x00dd, 0x6724 }, 194 { 0x00de, 0x3131 }, 195 { 0x00df, 0x0008 }, 196 { 0x00e0, 0x4000 }, 197 { 0x00e1, 0x3131 }, 198 { 0x00e4, 0x400c }, 199 { 0x00e5, 0x8031 }, 200 { 0x00ea, 0xb320 }, 201 { 0x00eb, 0x0000 }, 202 { 0x00ec, 0xb300 }, 203 { 0x00ed, 0x0000 }, 204 { 0x00f0, 0x0000 }, 205 { 0x00f1, 0x0202 }, 206 { 0x00f2, 0x0ddd }, 207 { 0x00f3, 0x0ddd }, 208 { 0x00f4, 0x0ddd }, 209 { 0x00f6, 0x0000 }, 210 { 0x00f7, 0x0000 }, 211 { 0x00f8, 0x0000 }, 212 { 0x00f9, 0x0000 }, 213 { 0x00fa, 0x8000 }, 214 { 0x00fb, 0x0000 }, 215 { 0x00fc, 0x0000 }, 216 { 0x00fd, 0x0001 }, 217 { 0x00fe, 0x10ec }, 218 { 0x00ff, 0x6311 }, 219 { 0x0100, 0xaaaa }, 220 { 0x010a, 0xaaaa }, 221 { 0x010b, 0x00a0 }, 222 { 0x010c, 0xaeae }, 223 { 0x010d, 0xaaaa }, 224 { 0x010e, 0xaaa8 }, 225 { 0x010f, 0xa0aa }, 226 { 0x0110, 0xe02a }, 227 { 0x0111, 0xa702 }, 228 { 0x0112, 0xaaaa }, 229 { 0x0113, 0x2800 }, 230 { 0x0116, 0x0000 }, 231 { 0x0117, 0x0f00 }, 232 { 0x011a, 0x0020 }, 233 { 0x011b, 0x0011 }, 234 { 0x011c, 0x0150 }, 235 { 0x011d, 0x0000 }, 236 { 0x011e, 0x0000 }, 237 { 0x011f, 0x0000 }, 238 { 0x0120, 0x0000 }, 239 { 0x0121, 0x009b }, 240 { 0x0122, 0x5014 }, 241 { 0x0123, 0x0421 }, 242 { 0x0124, 0x7cea }, 243 { 0x0125, 0x0420 }, 244 { 0x0126, 0x5550 }, 245 { 0x0132, 0x0000 }, 246 { 0x0133, 0x0000 }, 247 { 0x0137, 0x5055 }, 248 { 0x0138, 0x3700 }, 249 { 0x0139, 0x79a1 }, 250 { 0x013a, 0x2020 }, 251 { 0x013b, 0x2020 }, 252 { 0x013c, 0x2005 }, 253 { 0x013e, 0x1f00 }, 254 { 0x013f, 0x0000 }, 255 { 0x0145, 0x0002 }, 256 { 0x0146, 0x0000 }, 257 { 0x0147, 0x0000 }, 258 { 0x0148, 0x0000 }, 259 { 0x0150, 0x1813 }, 260 { 0x0151, 0x0690 }, 261 { 0x0152, 0x1c17 }, 262 { 0x0153, 0x6883 }, 263 { 0x0154, 0xd3ce }, 264 { 0x0155, 0x352d }, 265 { 0x0156, 0x00eb }, 266 { 0x0157, 0x3717 }, 267 { 0x0158, 0x4c6a }, 268 { 0x0159, 0xe41b }, 269 { 0x015a, 0x2a13 }, 270 { 0x015b, 0xb600 }, 271 { 0x015c, 0xc730 }, 272 { 0x015d, 0x35d4 }, 273 { 0x015e, 0x00bf }, 274 { 0x0160, 0x0ec0 }, 275 { 0x0161, 0x0020 }, 276 { 0x0162, 0x0080 }, 277 { 0x0163, 0x0800 }, 278 { 0x0164, 0x0000 }, 279 { 0x0165, 0x0000 }, 280 { 0x0166, 0x0000 }, 281 { 0x0167, 0x001f }, 282 { 0x0170, 0x4e80 }, 283 { 0x0171, 0x0020 }, 284 { 0x0172, 0x0080 }, 285 { 0x0173, 0x0800 }, 286 { 0x0174, 0x000c }, 287 { 0x0175, 0x0000 }, 288 { 0x0190, 0x3300 }, 289 { 0x0191, 0x2200 }, 290 { 0x0192, 0x0000 }, 291 { 0x01b0, 0x4b38 }, 292 { 0x01b1, 0x0000 }, 293 { 0x01b2, 0x0000 }, 294 { 0x01b3, 0x0000 }, 295 { 0x01c0, 0x0045 }, 296 { 0x01c1, 0x0540 }, 297 { 0x01c2, 0x0000 }, 298 { 0x01c3, 0x0030 }, 299 { 0x01c7, 0x0000 }, 300 { 0x01c8, 0x5757 }, 301 { 0x01c9, 0x5757 }, 302 { 0x01ca, 0x5757 }, 303 { 0x01cb, 0x5757 }, 304 { 0x01cc, 0x5757 }, 305 { 0x01cd, 0x5757 }, 306 { 0x01ce, 0x006f }, 307 { 0x01da, 0x0000 }, 308 { 0x01db, 0x0000 }, 309 { 0x01de, 0x7d00 }, 310 { 0x01df, 0x10c0 }, 311 { 0x01e0, 0x06a1 }, 312 { 0x01e1, 0x0000 }, 313 { 0x01e2, 0x0000 }, 314 { 0x01e3, 0x0000 }, 315 { 0x01e4, 0x0001 }, 316 { 0x01e6, 0x0000 }, 317 { 0x01e7, 0x0000 }, 318 { 0x01e8, 0x0000 }, 319 { 0x01ea, 0x0000 }, 320 { 0x01eb, 0x0000 }, 321 { 0x01ec, 0x0000 }, 322 { 0x01ed, 0x0000 }, 323 { 0x01ee, 0x0000 }, 324 { 0x01ef, 0x0000 }, 325 { 0x01f0, 0x0000 }, 326 { 0x01f1, 0x0000 }, 327 { 0x01f2, 0x0000 }, 328 { 0x01f6, 0x1e04 }, 329 { 0x01f7, 0x01a1 }, 330 { 0x01f8, 0x0000 }, 331 { 0x01f9, 0x0000 }, 332 { 0x01fa, 0x0002 }, 333 { 0x01fb, 0x0000 }, 334 { 0x01fc, 0x0000 }, 335 { 0x01fd, 0x0000 }, 336 { 0x01fe, 0x0000 }, 337 { 0x0200, 0x066c }, 338 { 0x0201, 0x7fff }, 339 { 0x0202, 0x7fff }, 340 { 0x0203, 0x0000 }, 341 { 0x0204, 0x0000 }, 342 { 0x0205, 0x0000 }, 343 { 0x0206, 0x0000 }, 344 { 0x0207, 0x0000 }, 345 { 0x0208, 0x0000 }, 346 { 0x0256, 0x0000 }, 347 { 0x0257, 0x0000 }, 348 { 0x0258, 0x0000 }, 349 { 0x0259, 0x0000 }, 350 { 0x025a, 0x0000 }, 351 { 0x025b, 0x3333 }, 352 { 0x025c, 0x3333 }, 353 { 0x025d, 0x3333 }, 354 { 0x025e, 0x0000 }, 355 { 0x025f, 0x0000 }, 356 { 0x0260, 0x0000 }, 357 { 0x0261, 0x0022 }, 358 { 0x0262, 0x0300 }, 359 { 0x0265, 0x1e80 }, 360 { 0x0266, 0x0131 }, 361 { 0x0267, 0x0003 }, 362 { 0x0268, 0x0000 }, 363 { 0x0269, 0x0000 }, 364 { 0x026a, 0x0000 }, 365 { 0x026b, 0x0000 }, 366 { 0x026c, 0x0000 }, 367 { 0x026d, 0x0000 }, 368 { 0x026e, 0x0000 }, 369 { 0x026f, 0x0000 }, 370 { 0x0270, 0x0000 }, 371 { 0x0271, 0x0000 }, 372 { 0x0272, 0x0000 }, 373 { 0x0273, 0x0000 }, 374 { 0x0280, 0x0000 }, 375 { 0x0281, 0x0000 }, 376 { 0x0282, 0x0418 }, 377 { 0x0283, 0x7fff }, 378 { 0x0284, 0x7000 }, 379 { 0x0290, 0x01d0 }, 380 { 0x0291, 0x0100 }, 381 { 0x02fa, 0x0000 }, 382 { 0x02fb, 0x0000 }, 383 { 0x02fc, 0x0000 }, 384 { 0x0300, 0x001f }, 385 { 0x0301, 0x032c }, 386 { 0x0302, 0x5f21 }, 387 { 0x0303, 0x4000 }, 388 { 0x0304, 0x4000 }, 389 { 0x0305, 0x0600 }, 390 { 0x0306, 0x8000 }, 391 { 0x0307, 0x0700 }, 392 { 0x0308, 0x001f }, 393 { 0x0309, 0x032c }, 394 { 0x030a, 0x5f21 }, 395 { 0x030b, 0x4000 }, 396 { 0x030c, 0x4000 }, 397 { 0x030d, 0x0600 }, 398 { 0x030e, 0x8000 }, 399 { 0x030f, 0x0700 }, 400 { 0x0310, 0x4560 }, 401 { 0x0311, 0xa4a8 }, 402 { 0x0312, 0x7418 }, 403 { 0x0313, 0x0000 }, 404 { 0x0314, 0x0006 }, 405 { 0x0315, 0x00ff }, 406 { 0x0316, 0xc400 }, 407 { 0x0317, 0x4560 }, 408 { 0x0318, 0xa4a8 }, 409 { 0x0319, 0x7418 }, 410 { 0x031a, 0x0000 }, 411 { 0x031b, 0x0006 }, 412 { 0x031c, 0x00ff }, 413 { 0x031d, 0xc400 }, 414 { 0x0320, 0x0f20 }, 415 { 0x0321, 0x8700 }, 416 { 0x0322, 0x7dc2 }, 417 { 0x0323, 0xa178 }, 418 { 0x0324, 0x5383 }, 419 { 0x0325, 0x7dc2 }, 420 { 0x0326, 0xa178 }, 421 { 0x0327, 0x5383 }, 422 { 0x0328, 0x003e }, 423 { 0x0329, 0x02c1 }, 424 { 0x032a, 0xd37d }, 425 { 0x0330, 0x00a6 }, 426 { 0x0331, 0x04c3 }, 427 { 0x0332, 0x27c8 }, 428 { 0x0333, 0xbf50 }, 429 { 0x0334, 0x0045 }, 430 { 0x0335, 0x2007 }, 431 { 0x0336, 0x7418 }, 432 { 0x0337, 0x0501 }, 433 { 0x0338, 0x0000 }, 434 { 0x0339, 0x0010 }, 435 { 0x033a, 0x1010 }, 436 { 0x0340, 0x0800 }, 437 { 0x0341, 0x0800 }, 438 { 0x0342, 0x0800 }, 439 { 0x0343, 0x0800 }, 440 { 0x0344, 0x0000 }, 441 { 0x0345, 0x0000 }, 442 { 0x0346, 0x0000 }, 443 { 0x0347, 0x0000 }, 444 { 0x0348, 0x0000 }, 445 { 0x0349, 0x0000 }, 446 { 0x034a, 0x0000 }, 447 { 0x034b, 0x0000 }, 448 { 0x034c, 0x0000 }, 449 { 0x034d, 0x0000 }, 450 { 0x034e, 0x0000 }, 451 { 0x034f, 0x0000 }, 452 { 0x0350, 0x0000 }, 453 { 0x0351, 0x0000 }, 454 { 0x0352, 0x0000 }, 455 { 0x0353, 0x0000 }, 456 { 0x0354, 0x0000 }, 457 { 0x0355, 0x0000 }, 458 { 0x0356, 0x0000 }, 459 { 0x0357, 0x0000 }, 460 { 0x0358, 0x0000 }, 461 { 0x0359, 0x0000 }, 462 { 0x035a, 0x0000 }, 463 { 0x035b, 0x0000 }, 464 { 0x035c, 0x0000 }, 465 { 0x035d, 0x0000 }, 466 { 0x035e, 0x2000 }, 467 { 0x035f, 0x0000 }, 468 { 0x0360, 0x2000 }, 469 { 0x0361, 0x2000 }, 470 { 0x0362, 0x0000 }, 471 { 0x0363, 0x2000 }, 472 { 0x0364, 0x0200 }, 473 { 0x0365, 0x0000 }, 474 { 0x0366, 0x0000 }, 475 { 0x0367, 0x0000 }, 476 { 0x0368, 0x0000 }, 477 { 0x0369, 0x0000 }, 478 { 0x036a, 0x0000 }, 479 { 0x036b, 0x0000 }, 480 { 0x036c, 0x0000 }, 481 { 0x036d, 0x0000 }, 482 { 0x036e, 0x0200 }, 483 { 0x036f, 0x0000 }, 484 { 0x0370, 0x0000 }, 485 { 0x0371, 0x0000 }, 486 { 0x0372, 0x0000 }, 487 { 0x0373, 0x0000 }, 488 { 0x0374, 0x0000 }, 489 { 0x0375, 0x0000 }, 490 { 0x0376, 0x0000 }, 491 { 0x0377, 0x0000 }, 492 { 0x03d0, 0x0000 }, 493 { 0x03d1, 0x0000 }, 494 { 0x03d2, 0x0000 }, 495 { 0x03d3, 0x0000 }, 496 { 0x03d4, 0x2000 }, 497 { 0x03d5, 0x2000 }, 498 { 0x03d6, 0x0000 }, 499 { 0x03d7, 0x0000 }, 500 { 0x03d8, 0x2000 }, 501 { 0x03d9, 0x2000 }, 502 { 0x03da, 0x2000 }, 503 { 0x03db, 0x2000 }, 504 { 0x03dc, 0x0000 }, 505 { 0x03dd, 0x0000 }, 506 { 0x03de, 0x0000 }, 507 { 0x03df, 0x2000 }, 508 { 0x03e0, 0x0000 }, 509 { 0x03e1, 0x0000 }, 510 { 0x03e2, 0x0000 }, 511 { 0x03e3, 0x0000 }, 512 { 0x03e4, 0x0000 }, 513 { 0x03e5, 0x0000 }, 514 { 0x03e6, 0x0000 }, 515 { 0x03e7, 0x0000 }, 516 { 0x03e8, 0x0000 }, 517 { 0x03e9, 0x0000 }, 518 { 0x03ea, 0x0000 }, 519 { 0x03eb, 0x0000 }, 520 { 0x03ec, 0x0000 }, 521 { 0x03ed, 0x0000 }, 522 { 0x03ee, 0x0000 }, 523 { 0x03ef, 0x0000 }, 524 { 0x03f0, 0x0800 }, 525 { 0x03f1, 0x0800 }, 526 { 0x03f2, 0x0800 }, 527 { 0x03f3, 0x0800 }, 528}; 529 530static bool rt5659_volatile_register(struct device *dev, unsigned int reg) 531{ 532 switch (reg) { 533 case RT5659_RESET: 534 case RT5659_EJD_CTRL_2: 535 case RT5659_SILENCE_CTRL: 536 case RT5659_DAC2_DIG_VOL: 537 case RT5659_HP_IMP_GAIN_2: 538 case RT5659_PDM_OUT_CTRL: 539 case RT5659_PDM_DATA_CTRL_1: 540 case RT5659_PDM_DATA_CTRL_4: 541 case RT5659_HAPTIC_GEN_CTRL_1: 542 case RT5659_HAPTIC_GEN_CTRL_3: 543 case RT5659_HAPTIC_LPF_CTRL_3: 544 case RT5659_CLK_DET: 545 case RT5659_MICBIAS_1: 546 case RT5659_ASRC_11: 547 case RT5659_ADC_EQ_CTRL_1: 548 case RT5659_DAC_EQ_CTRL_1: 549 case RT5659_INT_ST_1: 550 case RT5659_INT_ST_2: 551 case RT5659_GPIO_STA: 552 case RT5659_SINE_GEN_CTRL_1: 553 case RT5659_IL_CMD_1: 554 case RT5659_4BTN_IL_CMD_1: 555 case RT5659_PSV_IL_CMD_1: 556 case RT5659_AJD1_CTRL: 557 case RT5659_AJD2_AJD3_CTRL: 558 case RT5659_JD_CTRL_3: 559 case RT5659_VENDOR_ID: 560 case RT5659_VENDOR_ID_1: 561 case RT5659_DEVICE_ID: 562 case RT5659_MEMORY_TEST: 563 case RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL: 564 case RT5659_VOL_TEST: 565 case RT5659_STO_NG2_CTRL_1: 566 case RT5659_STO_NG2_CTRL_5: 567 case RT5659_STO_NG2_CTRL_6: 568 case RT5659_STO_NG2_CTRL_7: 569 case RT5659_MONO_NG2_CTRL_1: 570 case RT5659_MONO_NG2_CTRL_5: 571 case RT5659_MONO_NG2_CTRL_6: 572 case RT5659_HP_IMP_SENS_CTRL_1: 573 case RT5659_HP_IMP_SENS_CTRL_3: 574 case RT5659_HP_IMP_SENS_CTRL_4: 575 case RT5659_HP_CALIB_CTRL_1: 576 case RT5659_HP_CALIB_CTRL_9: 577 case RT5659_HP_CALIB_STA_1: 578 case RT5659_HP_CALIB_STA_2: 579 case RT5659_HP_CALIB_STA_3: 580 case RT5659_HP_CALIB_STA_4: 581 case RT5659_HP_CALIB_STA_5: 582 case RT5659_HP_CALIB_STA_6: 583 case RT5659_HP_CALIB_STA_7: 584 case RT5659_HP_CALIB_STA_8: 585 case RT5659_HP_CALIB_STA_9: 586 case RT5659_MONO_AMP_CALIB_CTRL_1: 587 case RT5659_MONO_AMP_CALIB_CTRL_3: 588 case RT5659_MONO_AMP_CALIB_STA_1: 589 case RT5659_MONO_AMP_CALIB_STA_2: 590 case RT5659_MONO_AMP_CALIB_STA_3: 591 case RT5659_MONO_AMP_CALIB_STA_4: 592 case RT5659_SPK_PWR_LMT_STA_1: 593 case RT5659_SPK_PWR_LMT_STA_2: 594 case RT5659_SPK_PWR_LMT_STA_3: 595 case RT5659_SPK_PWR_LMT_STA_4: 596 case RT5659_SPK_PWR_LMT_STA_5: 597 case RT5659_SPK_PWR_LMT_STA_6: 598 case RT5659_SPK_DC_CAILB_CTRL_1: 599 case RT5659_SPK_DC_CAILB_STA_1: 600 case RT5659_SPK_DC_CAILB_STA_2: 601 case RT5659_SPK_DC_CAILB_STA_3: 602 case RT5659_SPK_DC_CAILB_STA_4: 603 case RT5659_SPK_DC_CAILB_STA_5: 604 case RT5659_SPK_DC_CAILB_STA_6: 605 case RT5659_SPK_DC_CAILB_STA_7: 606 case RT5659_SPK_DC_CAILB_STA_8: 607 case RT5659_SPK_DC_CAILB_STA_9: 608 case RT5659_SPK_DC_CAILB_STA_10: 609 case RT5659_SPK_VDD_STA_1: 610 case RT5659_SPK_VDD_STA_2: 611 case RT5659_SPK_DC_DET_CTRL_1: 612 case RT5659_PURE_DC_DET_CTRL_1: 613 case RT5659_PURE_DC_DET_CTRL_2: 614 case RT5659_DRC1_PRIV_1: 615 case RT5659_DRC1_PRIV_4: 616 case RT5659_DRC1_PRIV_5: 617 case RT5659_DRC1_PRIV_6: 618 case RT5659_DRC1_PRIV_7: 619 case RT5659_DRC2_PRIV_1: 620 case RT5659_DRC2_PRIV_4: 621 case RT5659_DRC2_PRIV_5: 622 case RT5659_DRC2_PRIV_6: 623 case RT5659_DRC2_PRIV_7: 624 case RT5659_ALC_PGA_STA_1: 625 case RT5659_ALC_PGA_STA_2: 626 case RT5659_ALC_PGA_STA_3: 627 return true; 628 default: 629 return false; 630 } 631} 632 633static bool rt5659_readable_register(struct device *dev, unsigned int reg) 634{ 635 switch (reg) { 636 case RT5659_RESET: 637 case RT5659_SPO_VOL: 638 case RT5659_HP_VOL: 639 case RT5659_LOUT: 640 case RT5659_MONO_OUT: 641 case RT5659_HPL_GAIN: 642 case RT5659_HPR_GAIN: 643 case RT5659_MONO_GAIN: 644 case RT5659_SPDIF_CTRL_1: 645 case RT5659_SPDIF_CTRL_2: 646 case RT5659_CAL_BST_CTRL: 647 case RT5659_IN1_IN2: 648 case RT5659_IN3_IN4: 649 case RT5659_INL1_INR1_VOL: 650 case RT5659_EJD_CTRL_1: 651 case RT5659_EJD_CTRL_2: 652 case RT5659_EJD_CTRL_3: 653 case RT5659_SILENCE_CTRL: 654 case RT5659_PSV_CTRL: 655 case RT5659_SIDETONE_CTRL: 656 case RT5659_DAC1_DIG_VOL: 657 case RT5659_DAC2_DIG_VOL: 658 case RT5659_DAC_CTRL: 659 case RT5659_STO1_ADC_DIG_VOL: 660 case RT5659_MONO_ADC_DIG_VOL: 661 case RT5659_STO2_ADC_DIG_VOL: 662 case RT5659_STO1_BOOST: 663 case RT5659_MONO_BOOST: 664 case RT5659_STO2_BOOST: 665 case RT5659_HP_IMP_GAIN_1: 666 case RT5659_HP_IMP_GAIN_2: 667 case RT5659_STO1_ADC_MIXER: 668 case RT5659_MONO_ADC_MIXER: 669 case RT5659_AD_DA_MIXER: 670 case RT5659_STO_DAC_MIXER: 671 case RT5659_MONO_DAC_MIXER: 672 case RT5659_DIG_MIXER: 673 case RT5659_A_DAC_MUX: 674 case RT5659_DIG_INF23_DATA: 675 case RT5659_PDM_OUT_CTRL: 676 case RT5659_PDM_DATA_CTRL_1: 677 case RT5659_PDM_DATA_CTRL_2: 678 case RT5659_PDM_DATA_CTRL_3: 679 case RT5659_PDM_DATA_CTRL_4: 680 case RT5659_SPDIF_CTRL: 681 case RT5659_REC1_GAIN: 682 case RT5659_REC1_L1_MIXER: 683 case RT5659_REC1_L2_MIXER: 684 case RT5659_REC1_R1_MIXER: 685 case RT5659_REC1_R2_MIXER: 686 case RT5659_CAL_REC: 687 case RT5659_REC2_L1_MIXER: 688 case RT5659_REC2_L2_MIXER: 689 case RT5659_REC2_R1_MIXER: 690 case RT5659_REC2_R2_MIXER: 691 case RT5659_SPK_L_MIXER: 692 case RT5659_SPK_R_MIXER: 693 case RT5659_SPO_AMP_GAIN: 694 case RT5659_ALC_BACK_GAIN: 695 case RT5659_MONOMIX_GAIN: 696 case RT5659_MONOMIX_IN_GAIN: 697 case RT5659_OUT_L_GAIN: 698 case RT5659_OUT_L_MIXER: 699 case RT5659_OUT_R_GAIN: 700 case RT5659_OUT_R_MIXER: 701 case RT5659_LOUT_MIXER: 702 case RT5659_HAPTIC_GEN_CTRL_1: 703 case RT5659_HAPTIC_GEN_CTRL_2: 704 case RT5659_HAPTIC_GEN_CTRL_3: 705 case RT5659_HAPTIC_GEN_CTRL_4: 706 case RT5659_HAPTIC_GEN_CTRL_5: 707 case RT5659_HAPTIC_GEN_CTRL_6: 708 case RT5659_HAPTIC_GEN_CTRL_7: 709 case RT5659_HAPTIC_GEN_CTRL_8: 710 case RT5659_HAPTIC_GEN_CTRL_9: 711 case RT5659_HAPTIC_GEN_CTRL_10: 712 case RT5659_HAPTIC_GEN_CTRL_11: 713 case RT5659_HAPTIC_LPF_CTRL_1: 714 case RT5659_HAPTIC_LPF_CTRL_2: 715 case RT5659_HAPTIC_LPF_CTRL_3: 716 case RT5659_PWR_DIG_1: 717 case RT5659_PWR_DIG_2: 718 case RT5659_PWR_ANLG_1: 719 case RT5659_PWR_ANLG_2: 720 case RT5659_PWR_ANLG_3: 721 case RT5659_PWR_MIXER: 722 case RT5659_PWR_VOL: 723 case RT5659_PRIV_INDEX: 724 case RT5659_CLK_DET: 725 case RT5659_PRIV_DATA: 726 case RT5659_PRE_DIV_1: 727 case RT5659_PRE_DIV_2: 728 case RT5659_I2S1_SDP: 729 case RT5659_I2S2_SDP: 730 case RT5659_I2S3_SDP: 731 case RT5659_ADDA_CLK_1: 732 case RT5659_ADDA_CLK_2: 733 case RT5659_DMIC_CTRL_1: 734 case RT5659_DMIC_CTRL_2: 735 case RT5659_TDM_CTRL_1: 736 case RT5659_TDM_CTRL_2: 737 case RT5659_TDM_CTRL_3: 738 case RT5659_TDM_CTRL_4: 739 case RT5659_TDM_CTRL_5: 740 case RT5659_GLB_CLK: 741 case RT5659_PLL_CTRL_1: 742 case RT5659_PLL_CTRL_2: 743 case RT5659_ASRC_1: 744 case RT5659_ASRC_2: 745 case RT5659_ASRC_3: 746 case RT5659_ASRC_4: 747 case RT5659_ASRC_5: 748 case RT5659_ASRC_6: 749 case RT5659_ASRC_7: 750 case RT5659_ASRC_8: 751 case RT5659_ASRC_9: 752 case RT5659_ASRC_10: 753 case RT5659_DEPOP_1: 754 case RT5659_DEPOP_2: 755 case RT5659_DEPOP_3: 756 case RT5659_HP_CHARGE_PUMP_1: 757 case RT5659_HP_CHARGE_PUMP_2: 758 case RT5659_MICBIAS_1: 759 case RT5659_MICBIAS_2: 760 case RT5659_ASRC_11: 761 case RT5659_ASRC_12: 762 case RT5659_ASRC_13: 763 case RT5659_REC_M1_M2_GAIN_CTRL: 764 case RT5659_RC_CLK_CTRL: 765 case RT5659_CLASSD_CTRL_1: 766 case RT5659_CLASSD_CTRL_2: 767 case RT5659_ADC_EQ_CTRL_1: 768 case RT5659_ADC_EQ_CTRL_2: 769 case RT5659_DAC_EQ_CTRL_1: 770 case RT5659_DAC_EQ_CTRL_2: 771 case RT5659_DAC_EQ_CTRL_3: 772 case RT5659_IRQ_CTRL_1: 773 case RT5659_IRQ_CTRL_2: 774 case RT5659_IRQ_CTRL_3: 775 case RT5659_IRQ_CTRL_4: 776 case RT5659_IRQ_CTRL_5: 777 case RT5659_IRQ_CTRL_6: 778 case RT5659_INT_ST_1: 779 case RT5659_INT_ST_2: 780 case RT5659_GPIO_CTRL_1: 781 case RT5659_GPIO_CTRL_2: 782 case RT5659_GPIO_CTRL_3: 783 case RT5659_GPIO_CTRL_4: 784 case RT5659_GPIO_CTRL_5: 785 case RT5659_GPIO_STA: 786 case RT5659_SINE_GEN_CTRL_1: 787 case RT5659_SINE_GEN_CTRL_2: 788 case RT5659_SINE_GEN_CTRL_3: 789 case RT5659_HP_AMP_DET_CTRL_1: 790 case RT5659_HP_AMP_DET_CTRL_2: 791 case RT5659_SV_ZCD_1: 792 case RT5659_SV_ZCD_2: 793 case RT5659_IL_CMD_1: 794 case RT5659_IL_CMD_2: 795 case RT5659_IL_CMD_3: 796 case RT5659_IL_CMD_4: 797 case RT5659_4BTN_IL_CMD_1: 798 case RT5659_4BTN_IL_CMD_2: 799 case RT5659_4BTN_IL_CMD_3: 800 case RT5659_PSV_IL_CMD_1: 801 case RT5659_PSV_IL_CMD_2: 802 case RT5659_ADC_STO1_HP_CTRL_1: 803 case RT5659_ADC_STO1_HP_CTRL_2: 804 case RT5659_ADC_MONO_HP_CTRL_1: 805 case RT5659_ADC_MONO_HP_CTRL_2: 806 case RT5659_AJD1_CTRL: 807 case RT5659_AJD2_AJD3_CTRL: 808 case RT5659_JD1_THD: 809 case RT5659_JD2_THD: 810 case RT5659_JD3_THD: 811 case RT5659_JD_CTRL_1: 812 case RT5659_JD_CTRL_2: 813 case RT5659_JD_CTRL_3: 814 case RT5659_JD_CTRL_4: 815 case RT5659_DIG_MISC: 816 case RT5659_DUMMY_2: 817 case RT5659_DUMMY_3: 818 case RT5659_VENDOR_ID: 819 case RT5659_VENDOR_ID_1: 820 case RT5659_DEVICE_ID: 821 case RT5659_DAC_ADC_DIG_VOL: 822 case RT5659_BIAS_CUR_CTRL_1: 823 case RT5659_BIAS_CUR_CTRL_2: 824 case RT5659_BIAS_CUR_CTRL_3: 825 case RT5659_BIAS_CUR_CTRL_4: 826 case RT5659_BIAS_CUR_CTRL_5: 827 case RT5659_BIAS_CUR_CTRL_6: 828 case RT5659_BIAS_CUR_CTRL_7: 829 case RT5659_BIAS_CUR_CTRL_8: 830 case RT5659_BIAS_CUR_CTRL_9: 831 case RT5659_BIAS_CUR_CTRL_10: 832 case RT5659_MEMORY_TEST: 833 case RT5659_VREF_REC_OP_FB_CAP_CTRL: 834 case RT5659_CLASSD_0: 835 case RT5659_CLASSD_1: 836 case RT5659_CLASSD_2: 837 case RT5659_CLASSD_3: 838 case RT5659_CLASSD_4: 839 case RT5659_CLASSD_5: 840 case RT5659_CLASSD_6: 841 case RT5659_CLASSD_7: 842 case RT5659_CLASSD_8: 843 case RT5659_CLASSD_9: 844 case RT5659_CLASSD_10: 845 case RT5659_CHARGE_PUMP_1: 846 case RT5659_CHARGE_PUMP_2: 847 case RT5659_DIG_IN_CTRL_1: 848 case RT5659_DIG_IN_CTRL_2: 849 case RT5659_PAD_DRIVING_CTRL: 850 case RT5659_SOFT_RAMP_DEPOP: 851 case RT5659_PLL: 852 case RT5659_CHOP_DAC: 853 case RT5659_CHOP_ADC: 854 case RT5659_CALIB_ADC_CTRL: 855 case RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL: 856 case RT5659_VOL_TEST: 857 case RT5659_TEST_MODE_CTRL_1: 858 case RT5659_TEST_MODE_CTRL_2: 859 case RT5659_TEST_MODE_CTRL_3: 860 case RT5659_TEST_MODE_CTRL_4: 861 case RT5659_BASSBACK_CTRL: 862 case RT5659_MP3_PLUS_CTRL_1: 863 case RT5659_MP3_PLUS_CTRL_2: 864 case RT5659_MP3_HPF_A1: 865 case RT5659_MP3_HPF_A2: 866 case RT5659_MP3_HPF_H0: 867 case RT5659_MP3_LPF_H0: 868 case RT5659_3D_SPK_CTRL: 869 case RT5659_3D_SPK_COEF_1: 870 case RT5659_3D_SPK_COEF_2: 871 case RT5659_3D_SPK_COEF_3: 872 case RT5659_3D_SPK_COEF_4: 873 case RT5659_3D_SPK_COEF_5: 874 case RT5659_3D_SPK_COEF_6: 875 case RT5659_3D_SPK_COEF_7: 876 case RT5659_STO_NG2_CTRL_1: 877 case RT5659_STO_NG2_CTRL_2: 878 case RT5659_STO_NG2_CTRL_3: 879 case RT5659_STO_NG2_CTRL_4: 880 case RT5659_STO_NG2_CTRL_5: 881 case RT5659_STO_NG2_CTRL_6: 882 case RT5659_STO_NG2_CTRL_7: 883 case RT5659_STO_NG2_CTRL_8: 884 case RT5659_MONO_NG2_CTRL_1: 885 case RT5659_MONO_NG2_CTRL_2: 886 case RT5659_MONO_NG2_CTRL_3: 887 case RT5659_MONO_NG2_CTRL_4: 888 case RT5659_MONO_NG2_CTRL_5: 889 case RT5659_MONO_NG2_CTRL_6: 890 case RT5659_MID_HP_AMP_DET: 891 case RT5659_LOW_HP_AMP_DET: 892 case RT5659_LDO_CTRL: 893 case RT5659_HP_DECROSS_CTRL_1: 894 case RT5659_HP_DECROSS_CTRL_2: 895 case RT5659_HP_DECROSS_CTRL_3: 896 case RT5659_HP_DECROSS_CTRL_4: 897 case RT5659_HP_IMP_SENS_CTRL_1: 898 case RT5659_HP_IMP_SENS_CTRL_2: 899 case RT5659_HP_IMP_SENS_CTRL_3: 900 case RT5659_HP_IMP_SENS_CTRL_4: 901 case RT5659_HP_IMP_SENS_MAP_1: 902 case RT5659_HP_IMP_SENS_MAP_2: 903 case RT5659_HP_IMP_SENS_MAP_3: 904 case RT5659_HP_IMP_SENS_MAP_4: 905 case RT5659_HP_IMP_SENS_MAP_5: 906 case RT5659_HP_IMP_SENS_MAP_6: 907 case RT5659_HP_IMP_SENS_MAP_7: 908 case RT5659_HP_IMP_SENS_MAP_8: 909 case RT5659_HP_LOGIC_CTRL_1: 910 case RT5659_HP_LOGIC_CTRL_2: 911 case RT5659_HP_CALIB_CTRL_1: 912 case RT5659_HP_CALIB_CTRL_2: 913 case RT5659_HP_CALIB_CTRL_3: 914 case RT5659_HP_CALIB_CTRL_4: 915 case RT5659_HP_CALIB_CTRL_5: 916 case RT5659_HP_CALIB_CTRL_6: 917 case RT5659_HP_CALIB_CTRL_7: 918 case RT5659_HP_CALIB_CTRL_9: 919 case RT5659_HP_CALIB_CTRL_10: 920 case RT5659_HP_CALIB_CTRL_11: 921 case RT5659_HP_CALIB_STA_1: 922 case RT5659_HP_CALIB_STA_2: 923 case RT5659_HP_CALIB_STA_3: 924 case RT5659_HP_CALIB_STA_4: 925 case RT5659_HP_CALIB_STA_5: 926 case RT5659_HP_CALIB_STA_6: 927 case RT5659_HP_CALIB_STA_7: 928 case RT5659_HP_CALIB_STA_8: 929 case RT5659_HP_CALIB_STA_9: 930 case RT5659_MONO_AMP_CALIB_CTRL_1: 931 case RT5659_MONO_AMP_CALIB_CTRL_2: 932 case RT5659_MONO_AMP_CALIB_CTRL_3: 933 case RT5659_MONO_AMP_CALIB_CTRL_4: 934 case RT5659_MONO_AMP_CALIB_CTRL_5: 935 case RT5659_MONO_AMP_CALIB_STA_1: 936 case RT5659_MONO_AMP_CALIB_STA_2: 937 case RT5659_MONO_AMP_CALIB_STA_3: 938 case RT5659_MONO_AMP_CALIB_STA_4: 939 case RT5659_SPK_PWR_LMT_CTRL_1: 940 case RT5659_SPK_PWR_LMT_CTRL_2: 941 case RT5659_SPK_PWR_LMT_CTRL_3: 942 case RT5659_SPK_PWR_LMT_STA_1: 943 case RT5659_SPK_PWR_LMT_STA_2: 944 case RT5659_SPK_PWR_LMT_STA_3: 945 case RT5659_SPK_PWR_LMT_STA_4: 946 case RT5659_SPK_PWR_LMT_STA_5: 947 case RT5659_SPK_PWR_LMT_STA_6: 948 case RT5659_FLEX_SPK_BST_CTRL_1: 949 case RT5659_FLEX_SPK_BST_CTRL_2: 950 case RT5659_FLEX_SPK_BST_CTRL_3: 951 case RT5659_FLEX_SPK_BST_CTRL_4: 952 case RT5659_SPK_EX_LMT_CTRL_1: 953 case RT5659_SPK_EX_LMT_CTRL_2: 954 case RT5659_SPK_EX_LMT_CTRL_3: 955 case RT5659_SPK_EX_LMT_CTRL_4: 956 case RT5659_SPK_EX_LMT_CTRL_5: 957 case RT5659_SPK_EX_LMT_CTRL_6: 958 case RT5659_SPK_EX_LMT_CTRL_7: 959 case RT5659_ADJ_HPF_CTRL_1: 960 case RT5659_ADJ_HPF_CTRL_2: 961 case RT5659_SPK_DC_CAILB_CTRL_1: 962 case RT5659_SPK_DC_CAILB_CTRL_2: 963 case RT5659_SPK_DC_CAILB_CTRL_3: 964 case RT5659_SPK_DC_CAILB_CTRL_4: 965 case RT5659_SPK_DC_CAILB_CTRL_5: 966 case RT5659_SPK_DC_CAILB_STA_1: 967 case RT5659_SPK_DC_CAILB_STA_2: 968 case RT5659_SPK_DC_CAILB_STA_3: 969 case RT5659_SPK_DC_CAILB_STA_4: 970 case RT5659_SPK_DC_CAILB_STA_5: 971 case RT5659_SPK_DC_CAILB_STA_6: 972 case RT5659_SPK_DC_CAILB_STA_7: 973 case RT5659_SPK_DC_CAILB_STA_8: 974 case RT5659_SPK_DC_CAILB_STA_9: 975 case RT5659_SPK_DC_CAILB_STA_10: 976 case RT5659_SPK_VDD_STA_1: 977 case RT5659_SPK_VDD_STA_2: 978 case RT5659_SPK_DC_DET_CTRL_1: 979 case RT5659_SPK_DC_DET_CTRL_2: 980 case RT5659_SPK_DC_DET_CTRL_3: 981 case RT5659_PURE_DC_DET_CTRL_1: 982 case RT5659_PURE_DC_DET_CTRL_2: 983 case RT5659_DUMMY_4: 984 case RT5659_DUMMY_5: 985 case RT5659_DUMMY_6: 986 case RT5659_DRC1_CTRL_1: 987 case RT5659_DRC1_CTRL_2: 988 case RT5659_DRC1_CTRL_3: 989 case RT5659_DRC1_CTRL_4: 990 case RT5659_DRC1_CTRL_5: 991 case RT5659_DRC1_CTRL_6: 992 case RT5659_DRC1_HARD_LMT_CTRL_1: 993 case RT5659_DRC1_HARD_LMT_CTRL_2: 994 case RT5659_DRC2_CTRL_1: 995 case RT5659_DRC2_CTRL_2: 996 case RT5659_DRC2_CTRL_3: 997 case RT5659_DRC2_CTRL_4: 998 case RT5659_DRC2_CTRL_5: 999 case RT5659_DRC2_CTRL_6: 1000 case RT5659_DRC2_HARD_LMT_CTRL_1: 1001 case RT5659_DRC2_HARD_LMT_CTRL_2: 1002 case RT5659_DRC1_PRIV_1: 1003 case RT5659_DRC1_PRIV_2: 1004 case RT5659_DRC1_PRIV_3: 1005 case RT5659_DRC1_PRIV_4: 1006 case RT5659_DRC1_PRIV_5: 1007 case RT5659_DRC1_PRIV_6: 1008 case RT5659_DRC1_PRIV_7: 1009 case RT5659_DRC2_PRIV_1: 1010 case RT5659_DRC2_PRIV_2: 1011 case RT5659_DRC2_PRIV_3: 1012 case RT5659_DRC2_PRIV_4: 1013 case RT5659_DRC2_PRIV_5: 1014 case RT5659_DRC2_PRIV_6: 1015 case RT5659_DRC2_PRIV_7: 1016 case RT5659_MULTI_DRC_CTRL: 1017 case RT5659_CROSS_OVER_1: 1018 case RT5659_CROSS_OVER_2: 1019 case RT5659_CROSS_OVER_3: 1020 case RT5659_CROSS_OVER_4: 1021 case RT5659_CROSS_OVER_5: 1022 case RT5659_CROSS_OVER_6: 1023 case RT5659_CROSS_OVER_7: 1024 case RT5659_CROSS_OVER_8: 1025 case RT5659_CROSS_OVER_9: 1026 case RT5659_CROSS_OVER_10: 1027 case RT5659_ALC_PGA_CTRL_1: 1028 case RT5659_ALC_PGA_CTRL_2: 1029 case RT5659_ALC_PGA_CTRL_3: 1030 case RT5659_ALC_PGA_CTRL_4: 1031 case RT5659_ALC_PGA_CTRL_5: 1032 case RT5659_ALC_PGA_CTRL_6: 1033 case RT5659_ALC_PGA_CTRL_7: 1034 case RT5659_ALC_PGA_CTRL_8: 1035 case RT5659_ALC_PGA_STA_1: 1036 case RT5659_ALC_PGA_STA_2: 1037 case RT5659_ALC_PGA_STA_3: 1038 case RT5659_DAC_L_EQ_PRE_VOL: 1039 case RT5659_DAC_R_EQ_PRE_VOL: 1040 case RT5659_DAC_L_EQ_POST_VOL: 1041 case RT5659_DAC_R_EQ_POST_VOL: 1042 case RT5659_DAC_L_EQ_LPF1_A1: 1043 case RT5659_DAC_L_EQ_LPF1_H0: 1044 case RT5659_DAC_R_EQ_LPF1_A1: 1045 case RT5659_DAC_R_EQ_LPF1_H0: 1046 case RT5659_DAC_L_EQ_BPF2_A1: 1047 case RT5659_DAC_L_EQ_BPF2_A2: 1048 case RT5659_DAC_L_EQ_BPF2_H0: 1049 case RT5659_DAC_R_EQ_BPF2_A1: 1050 case RT5659_DAC_R_EQ_BPF2_A2: 1051 case RT5659_DAC_R_EQ_BPF2_H0: 1052 case RT5659_DAC_L_EQ_BPF3_A1: 1053 case RT5659_DAC_L_EQ_BPF3_A2: 1054 case RT5659_DAC_L_EQ_BPF3_H0: 1055 case RT5659_DAC_R_EQ_BPF3_A1: 1056 case RT5659_DAC_R_EQ_BPF3_A2: 1057 case RT5659_DAC_R_EQ_BPF3_H0: 1058 case RT5659_DAC_L_EQ_BPF4_A1: 1059 case RT5659_DAC_L_EQ_BPF4_A2: 1060 case RT5659_DAC_L_EQ_BPF4_H0: 1061 case RT5659_DAC_R_EQ_BPF4_A1: 1062 case RT5659_DAC_R_EQ_BPF4_A2: 1063 case RT5659_DAC_R_EQ_BPF4_H0: 1064 case RT5659_DAC_L_EQ_HPF1_A1: 1065 case RT5659_DAC_L_EQ_HPF1_H0: 1066 case RT5659_DAC_R_EQ_HPF1_A1: 1067 case RT5659_DAC_R_EQ_HPF1_H0: 1068 case RT5659_DAC_L_EQ_HPF2_A1: 1069 case RT5659_DAC_L_EQ_HPF2_A2: 1070 case RT5659_DAC_L_EQ_HPF2_H0: 1071 case RT5659_DAC_R_EQ_HPF2_A1: 1072 case RT5659_DAC_R_EQ_HPF2_A2: 1073 case RT5659_DAC_R_EQ_HPF2_H0: 1074 case RT5659_DAC_L_BI_EQ_BPF1_H0_1: 1075 case RT5659_DAC_L_BI_EQ_BPF1_H0_2: 1076 case RT5659_DAC_L_BI_EQ_BPF1_B1_1: 1077 case RT5659_DAC_L_BI_EQ_BPF1_B1_2: 1078 case RT5659_DAC_L_BI_EQ_BPF1_B2_1: 1079 case RT5659_DAC_L_BI_EQ_BPF1_B2_2: 1080 case RT5659_DAC_L_BI_EQ_BPF1_A1_1: 1081 case RT5659_DAC_L_BI_EQ_BPF1_A1_2: 1082 case RT5659_DAC_L_BI_EQ_BPF1_A2_1: 1083 case RT5659_DAC_L_BI_EQ_BPF1_A2_2: 1084 case RT5659_DAC_R_BI_EQ_BPF1_H0_1: 1085 case RT5659_DAC_R_BI_EQ_BPF1_H0_2: 1086 case RT5659_DAC_R_BI_EQ_BPF1_B1_1: 1087 case RT5659_DAC_R_BI_EQ_BPF1_B1_2: 1088 case RT5659_DAC_R_BI_EQ_BPF1_B2_1: 1089 case RT5659_DAC_R_BI_EQ_BPF1_B2_2: 1090 case RT5659_DAC_R_BI_EQ_BPF1_A1_1: 1091 case RT5659_DAC_R_BI_EQ_BPF1_A1_2: 1092 case RT5659_DAC_R_BI_EQ_BPF1_A2_1: 1093 case RT5659_DAC_R_BI_EQ_BPF1_A2_2: 1094 case RT5659_ADC_L_EQ_LPF1_A1: 1095 case RT5659_ADC_R_EQ_LPF1_A1: 1096 case RT5659_ADC_L_EQ_LPF1_H0: 1097 case RT5659_ADC_R_EQ_LPF1_H0: 1098 case RT5659_ADC_L_EQ_BPF1_A1: 1099 case RT5659_ADC_R_EQ_BPF1_A1: 1100 case RT5659_ADC_L_EQ_BPF1_A2: 1101 case RT5659_ADC_R_EQ_BPF1_A2: 1102 case RT5659_ADC_L_EQ_BPF1_H0: 1103 case RT5659_ADC_R_EQ_BPF1_H0: 1104 case RT5659_ADC_L_EQ_BPF2_A1: 1105 case RT5659_ADC_R_EQ_BPF2_A1: 1106 case RT5659_ADC_L_EQ_BPF2_A2: 1107 case RT5659_ADC_R_EQ_BPF2_A2: 1108 case RT5659_ADC_L_EQ_BPF2_H0: 1109 case RT5659_ADC_R_EQ_BPF2_H0: 1110 case RT5659_ADC_L_EQ_BPF3_A1: 1111 case RT5659_ADC_R_EQ_BPF3_A1: 1112 case RT5659_ADC_L_EQ_BPF3_A2: 1113 case RT5659_ADC_R_EQ_BPF3_A2: 1114 case RT5659_ADC_L_EQ_BPF3_H0: 1115 case RT5659_ADC_R_EQ_BPF3_H0: 1116 case RT5659_ADC_L_EQ_BPF4_A1: 1117 case RT5659_ADC_R_EQ_BPF4_A1: 1118 case RT5659_ADC_L_EQ_BPF4_A2: 1119 case RT5659_ADC_R_EQ_BPF4_A2: 1120 case RT5659_ADC_L_EQ_BPF4_H0: 1121 case RT5659_ADC_R_EQ_BPF4_H0: 1122 case RT5659_ADC_L_EQ_HPF1_A1: 1123 case RT5659_ADC_R_EQ_HPF1_A1: 1124 case RT5659_ADC_L_EQ_HPF1_H0: 1125 case RT5659_ADC_R_EQ_HPF1_H0: 1126 case RT5659_ADC_L_EQ_PRE_VOL: 1127 case RT5659_ADC_R_EQ_PRE_VOL: 1128 case RT5659_ADC_L_EQ_POST_VOL: 1129 case RT5659_ADC_R_EQ_POST_VOL: 1130 return true; 1131 default: 1132 return false; 1133 } 1134} 1135 1136static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2325, 75, 0); 1137static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); 1138static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0); 1139static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); 1140static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0); 1141static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 1142static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0); 1143 1144/* Interface data select */ 1145static const char * const rt5659_data_select[] = { 1146 "L/R", "R/L", "L/L", "R/R" 1147}; 1148 1149static SOC_ENUM_SINGLE_DECL(rt5659_if1_01_adc_enum, 1150 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT01_SFT, rt5659_data_select); 1151 1152static SOC_ENUM_SINGLE_DECL(rt5659_if1_23_adc_enum, 1153 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT23_SFT, rt5659_data_select); 1154 1155static SOC_ENUM_SINGLE_DECL(rt5659_if1_45_adc_enum, 1156 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT45_SFT, rt5659_data_select); 1157 1158static SOC_ENUM_SINGLE_DECL(rt5659_if1_67_adc_enum, 1159 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT67_SFT, rt5659_data_select); 1160 1161static SOC_ENUM_SINGLE_DECL(rt5659_if2_dac_enum, 1162 RT5659_DIG_INF23_DATA, RT5659_IF2_DAC_SEL_SFT, rt5659_data_select); 1163 1164static SOC_ENUM_SINGLE_DECL(rt5659_if2_adc_enum, 1165 RT5659_DIG_INF23_DATA, RT5659_IF2_ADC_SEL_SFT, rt5659_data_select); 1166 1167static SOC_ENUM_SINGLE_DECL(rt5659_if3_dac_enum, 1168 RT5659_DIG_INF23_DATA, RT5659_IF3_DAC_SEL_SFT, rt5659_data_select); 1169 1170static SOC_ENUM_SINGLE_DECL(rt5659_if3_adc_enum, 1171 RT5659_DIG_INF23_DATA, RT5659_IF3_ADC_SEL_SFT, rt5659_data_select); 1172 1173static const struct snd_kcontrol_new rt5659_if1_01_adc_swap_mux = 1174 SOC_DAPM_ENUM("IF1 01 ADC Swap Source", rt5659_if1_01_adc_enum); 1175 1176static const struct snd_kcontrol_new rt5659_if1_23_adc_swap_mux = 1177 SOC_DAPM_ENUM("IF1 23 ADC1 Swap Source", rt5659_if1_23_adc_enum); 1178 1179static const struct snd_kcontrol_new rt5659_if1_45_adc_swap_mux = 1180 SOC_DAPM_ENUM("IF1 45 ADC1 Swap Source", rt5659_if1_45_adc_enum); 1181 1182static const struct snd_kcontrol_new rt5659_if1_67_adc_swap_mux = 1183 SOC_DAPM_ENUM("IF1 67 ADC1 Swap Source", rt5659_if1_67_adc_enum); 1184 1185static const struct snd_kcontrol_new rt5659_if2_dac_swap_mux = 1186 SOC_DAPM_ENUM("IF2 DAC Swap Source", rt5659_if2_dac_enum); 1187 1188static const struct snd_kcontrol_new rt5659_if2_adc_swap_mux = 1189 SOC_DAPM_ENUM("IF2 ADC Swap Source", rt5659_if2_adc_enum); 1190 1191static const struct snd_kcontrol_new rt5659_if3_dac_swap_mux = 1192 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5659_if3_dac_enum); 1193 1194static const struct snd_kcontrol_new rt5659_if3_adc_swap_mux = 1195 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5659_if3_adc_enum); 1196 1197static int rt5659_hp_vol_put(struct snd_kcontrol *kcontrol, 1198 struct snd_ctl_elem_value *ucontrol) 1199{ 1200 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1201 int ret = snd_soc_put_volsw(kcontrol, ucontrol); 1202 1203 if (snd_soc_component_read(component, RT5659_STO_NG2_CTRL_1) & RT5659_NG2_EN) { 1204 snd_soc_component_update_bits(component, RT5659_STO_NG2_CTRL_1, 1205 RT5659_NG2_EN_MASK, RT5659_NG2_DIS); 1206 snd_soc_component_update_bits(component, RT5659_STO_NG2_CTRL_1, 1207 RT5659_NG2_EN_MASK, RT5659_NG2_EN); 1208 } 1209 1210 return ret; 1211} 1212 1213static void rt5659_enable_push_button_irq(struct snd_soc_component *component, 1214 bool enable) 1215{ 1216 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1217 1218 if (enable) { 1219 snd_soc_component_write(component, RT5659_4BTN_IL_CMD_1, 0x000b); 1220 1221 /* MICBIAS1 and Mic Det Power for button detect*/ 1222 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); 1223 snd_soc_dapm_force_enable_pin(dapm, 1224 "Mic Det Power"); 1225 snd_soc_dapm_sync(dapm); 1226 1227 snd_soc_component_update_bits(component, RT5659_PWR_ANLG_2, 1228 RT5659_PWR_MB1, RT5659_PWR_MB1); 1229 snd_soc_component_update_bits(component, RT5659_PWR_VOL, 1230 RT5659_PWR_MIC_DET, RT5659_PWR_MIC_DET); 1231 1232 snd_soc_component_update_bits(component, RT5659_IRQ_CTRL_2, 1233 RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_EN); 1234 snd_soc_component_update_bits(component, RT5659_4BTN_IL_CMD_2, 1235 RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_EN); 1236 } else { 1237 snd_soc_component_update_bits(component, RT5659_4BTN_IL_CMD_2, 1238 RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_DIS); 1239 snd_soc_component_update_bits(component, RT5659_IRQ_CTRL_2, 1240 RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_DIS); 1241 /* MICBIAS1 and Mic Det Power for button detect*/ 1242 snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 1243 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 1244 snd_soc_dapm_sync(dapm); 1245 } 1246} 1247 1248/** 1249 * rt5659_headset_detect - Detect headset. 1250 * @component: SoC audio component device. 1251 * @jack_insert: Jack insert or not. 1252 * 1253 * Detect whether is headset or not when jack inserted. 1254 * 1255 * Returns detect status. 1256 */ 1257 1258static int rt5659_headset_detect(struct snd_soc_component *component, int jack_insert) 1259{ 1260 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1261 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30}; 1262 int reg_63; 1263 1264 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component); 1265 1266 if (jack_insert) { 1267 snd_soc_dapm_force_enable_pin(dapm, 1268 "Mic Det Power"); 1269 snd_soc_dapm_sync(dapm); 1270 reg_63 = snd_soc_component_read(component, RT5659_PWR_ANLG_1); 1271 1272 snd_soc_component_update_bits(component, RT5659_PWR_ANLG_1, 1273 RT5659_PWR_VREF2 | RT5659_PWR_MB, 1274 RT5659_PWR_VREF2 | RT5659_PWR_MB); 1275 msleep(20); 1276 snd_soc_component_update_bits(component, RT5659_PWR_ANLG_1, 1277 RT5659_PWR_FV2, RT5659_PWR_FV2); 1278 1279 snd_soc_component_write(component, RT5659_EJD_CTRL_2, 0x4160); 1280 snd_soc_component_update_bits(component, RT5659_EJD_CTRL_1, 1281 0x20, 0x0); 1282 msleep(20); 1283 snd_soc_component_update_bits(component, RT5659_EJD_CTRL_1, 1284 0x20, 0x20); 1285 1286 while (i < 5) { 1287 msleep(sleep_time[i]); 1288 val = snd_soc_component_read(component, RT5659_EJD_CTRL_2) & 0x0003; 1289 i++; 1290 if (val == 0x1 || val == 0x2 || val == 0x3) 1291 break; 1292 } 1293 1294 switch (val) { 1295 case 1: 1296 rt5659->jack_type = SND_JACK_HEADSET; 1297 rt5659_enable_push_button_irq(component, true); 1298 break; 1299 default: 1300 snd_soc_component_write(component, RT5659_PWR_ANLG_1, reg_63); 1301 rt5659->jack_type = SND_JACK_HEADPHONE; 1302 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 1303 snd_soc_dapm_sync(dapm); 1304 break; 1305 } 1306 } else { 1307 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 1308 snd_soc_dapm_sync(dapm); 1309 if (rt5659->jack_type == SND_JACK_HEADSET) 1310 rt5659_enable_push_button_irq(component, false); 1311 rt5659->jack_type = 0; 1312 } 1313 1314 dev_dbg(component->dev, "jack_type = %d\n", rt5659->jack_type); 1315 return rt5659->jack_type; 1316} 1317 1318static int rt5659_button_detect(struct snd_soc_component *component) 1319{ 1320 int btn_type, val; 1321 1322 val = snd_soc_component_read(component, RT5659_4BTN_IL_CMD_1); 1323 btn_type = val & 0xfff0; 1324 snd_soc_component_write(component, RT5659_4BTN_IL_CMD_1, val); 1325 1326 return btn_type; 1327} 1328 1329static irqreturn_t rt5659_irq(int irq, void *data) 1330{ 1331 struct rt5659_priv *rt5659 = data; 1332 1333 queue_delayed_work(system_power_efficient_wq, 1334 &rt5659->jack_detect_work, msecs_to_jiffies(250)); 1335 1336 return IRQ_HANDLED; 1337} 1338 1339int rt5659_set_jack_detect(struct snd_soc_component *component, 1340 struct snd_soc_jack *hs_jack) 1341{ 1342 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component); 1343 1344 rt5659->hs_jack = hs_jack; 1345 1346 rt5659_irq(0, rt5659); 1347 1348 return 0; 1349} 1350EXPORT_SYMBOL_GPL(rt5659_set_jack_detect); 1351 1352static void rt5659_jack_detect_work(struct work_struct *work) 1353{ 1354 struct rt5659_priv *rt5659 = 1355 container_of(work, struct rt5659_priv, jack_detect_work.work); 1356 int val, btn_type, report = 0; 1357 1358 if (!rt5659->component) 1359 return; 1360 1361 val = snd_soc_component_read(rt5659->component, RT5659_INT_ST_1) & 0x0080; 1362 if (!val) { 1363 /* jack in */ 1364 if (rt5659->jack_type == 0) { 1365 /* jack was out, report jack type */ 1366 report = rt5659_headset_detect(rt5659->component, 1); 1367 } else { 1368 /* jack is already in, report button event */ 1369 report = SND_JACK_HEADSET; 1370 btn_type = rt5659_button_detect(rt5659->component); 1371 /** 1372 * rt5659 can report three kinds of button behavior, 1373 * one click, double click and hold. However, 1374 * currently we will report button pressed/released 1375 * event. So all the three button behaviors are 1376 * treated as button pressed. 1377 */ 1378 switch (btn_type) { 1379 case 0x8000: 1380 case 0x4000: 1381 case 0x2000: 1382 report |= SND_JACK_BTN_0; 1383 break; 1384 case 0x1000: 1385 case 0x0800: 1386 case 0x0400: 1387 report |= SND_JACK_BTN_1; 1388 break; 1389 case 0x0200: 1390 case 0x0100: 1391 case 0x0080: 1392 report |= SND_JACK_BTN_2; 1393 break; 1394 case 0x0040: 1395 case 0x0020: 1396 case 0x0010: 1397 report |= SND_JACK_BTN_3; 1398 break; 1399 case 0x0000: /* unpressed */ 1400 break; 1401 default: 1402 btn_type = 0; 1403 dev_err(rt5659->component->dev, 1404 "Unexpected button code 0x%04x\n", 1405 btn_type); 1406 break; 1407 } 1408 1409 /* button release or spurious interrput*/ 1410 if (btn_type == 0) 1411 report = rt5659->jack_type; 1412 } 1413 } else { 1414 /* jack out */ 1415 report = rt5659_headset_detect(rt5659->component, 0); 1416 } 1417 1418 snd_soc_jack_report(rt5659->hs_jack, report, SND_JACK_HEADSET | 1419 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1420 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1421} 1422 1423static void rt5659_jack_detect_intel_hd_header(struct work_struct *work) 1424{ 1425 struct rt5659_priv *rt5659 = 1426 container_of(work, struct rt5659_priv, jack_detect_work.work); 1427 unsigned int value; 1428 bool hp_flag, mic_flag; 1429 1430 if (!rt5659->hs_jack) 1431 return; 1432 1433 /* headphone jack */ 1434 regmap_read(rt5659->regmap, RT5659_GPIO_STA, &value); 1435 hp_flag = (!(value & 0x8)) ? true : false; 1436 1437 if (hp_flag != rt5659->hda_hp_plugged) { 1438 rt5659->hda_hp_plugged = hp_flag; 1439 1440 if (hp_flag) { 1441 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1, 1442 0x10, 0x0); 1443 rt5659->jack_type |= SND_JACK_HEADPHONE; 1444 } else { 1445 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1, 1446 0x10, 0x10); 1447 rt5659->jack_type = rt5659->jack_type & 1448 (~SND_JACK_HEADPHONE); 1449 } 1450 1451 snd_soc_jack_report(rt5659->hs_jack, rt5659->jack_type, 1452 SND_JACK_HEADPHONE); 1453 } 1454 1455 /* mic jack */ 1456 regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value); 1457 regmap_write(rt5659->regmap, RT5659_4BTN_IL_CMD_1, value); 1458 mic_flag = (value & 0x2000) ? true : false; 1459 1460 if (mic_flag != rt5659->hda_mic_plugged) { 1461 rt5659->hda_mic_plugged = mic_flag; 1462 if (mic_flag) { 1463 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2, 1464 0x2, 0x2); 1465 rt5659->jack_type |= SND_JACK_MICROPHONE; 1466 } else { 1467 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2, 1468 0x2, 0x0); 1469 rt5659->jack_type = rt5659->jack_type 1470 & (~SND_JACK_MICROPHONE); 1471 } 1472 1473 snd_soc_jack_report(rt5659->hs_jack, rt5659->jack_type, 1474 SND_JACK_MICROPHONE); 1475 } 1476} 1477 1478static const struct snd_kcontrol_new rt5659_snd_controls[] = { 1479 /* Speaker Output Volume */ 1480 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5659_SPO_VOL, 1481 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 39, 1, out_vol_tlv), 1482 1483 /* Headphone Output Volume */ 1484 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5659_HPL_GAIN, 1485 RT5659_HPR_GAIN, RT5659_G_HP_SFT, 31, 1, snd_soc_get_volsw, 1486 rt5659_hp_vol_put, hp_vol_tlv), 1487 1488 /* Mono Output Volume */ 1489 SOC_SINGLE_TLV("Mono Playback Volume", RT5659_MONO_OUT, 1490 RT5659_L_VOL_SFT, 39, 1, out_vol_tlv), 1491 1492 /* Output Volume */ 1493 SOC_DOUBLE_TLV("OUT Playback Volume", RT5659_LOUT, 1494 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 39, 1, out_vol_tlv), 1495 1496 /* DAC Digital Volume */ 1497 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5659_DAC1_DIG_VOL, 1498 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 175, 0, dac_vol_tlv), 1499 SOC_DOUBLE("DAC1 Playback Switch", RT5659_AD_DA_MIXER, 1500 RT5659_M_DAC1_L_SFT, RT5659_M_DAC1_R_SFT, 1, 1), 1501 1502 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5659_DAC2_DIG_VOL, 1503 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 175, 0, dac_vol_tlv), 1504 SOC_DOUBLE("DAC2 Playback Switch", RT5659_DAC_CTRL, 1505 RT5659_M_DAC2_L_VOL_SFT, RT5659_M_DAC2_R_VOL_SFT, 1, 1), 1506 1507 /* IN1/IN2/IN3/IN4 Volume */ 1508 SOC_SINGLE_TLV("IN1 Boost Volume", RT5659_IN1_IN2, 1509 RT5659_BST1_SFT, 69, 0, in_bst_tlv), 1510 SOC_SINGLE_TLV("IN2 Boost Volume", RT5659_IN1_IN2, 1511 RT5659_BST2_SFT, 69, 0, in_bst_tlv), 1512 SOC_SINGLE_TLV("IN3 Boost Volume", RT5659_IN3_IN4, 1513 RT5659_BST3_SFT, 69, 0, in_bst_tlv), 1514 SOC_SINGLE_TLV("IN4 Boost Volume", RT5659_IN3_IN4, 1515 RT5659_BST4_SFT, 69, 0, in_bst_tlv), 1516 1517 /* INL/INR Volume Control */ 1518 SOC_DOUBLE_TLV("IN Capture Volume", RT5659_INL1_INR1_VOL, 1519 RT5659_INL_VOL_SFT, RT5659_INR_VOL_SFT, 31, 1, in_vol_tlv), 1520 1521 /* ADC Digital Volume Control */ 1522 SOC_DOUBLE("STO1 ADC Capture Switch", RT5659_STO1_ADC_DIG_VOL, 1523 RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1), 1524 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5659_STO1_ADC_DIG_VOL, 1525 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv), 1526 SOC_DOUBLE("Mono ADC Capture Switch", RT5659_MONO_ADC_DIG_VOL, 1527 RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1), 1528 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5659_MONO_ADC_DIG_VOL, 1529 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv), 1530 SOC_DOUBLE("STO2 ADC Capture Switch", RT5659_STO2_ADC_DIG_VOL, 1531 RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1), 1532 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5659_STO2_ADC_DIG_VOL, 1533 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv), 1534 1535 /* ADC Boost Volume Control */ 1536 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5659_STO1_BOOST, 1537 RT5659_STO1_ADC_L_BST_SFT, RT5659_STO1_ADC_R_BST_SFT, 1538 3, 0, adc_bst_tlv), 1539 1540 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5659_MONO_BOOST, 1541 RT5659_MONO_ADC_L_BST_SFT, RT5659_MONO_ADC_R_BST_SFT, 1542 3, 0, adc_bst_tlv), 1543 1544 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5659_STO2_BOOST, 1545 RT5659_STO2_ADC_L_BST_SFT, RT5659_STO2_ADC_R_BST_SFT, 1546 3, 0, adc_bst_tlv), 1547 1548 SOC_SINGLE("DAC IF1 DAC1 L Data Switch", RT5659_TDM_CTRL_4, 12, 7, 0), 1549 SOC_SINGLE("DAC IF1 DAC1 R Data Switch", RT5659_TDM_CTRL_4, 8, 7, 0), 1550 SOC_SINGLE("DAC IF1 DAC2 L Data Switch", RT5659_TDM_CTRL_4, 4, 7, 0), 1551 SOC_SINGLE("DAC IF1 DAC2 R Data Switch", RT5659_TDM_CTRL_4, 0, 7, 0), 1552}; 1553 1554/** 1555 * set_dmic_clk - Set parameter of dmic. 1556 * 1557 * @w: DAPM widget. 1558 * @kcontrol: The kcontrol of this widget. 1559 * @event: Event id. 1560 * 1561 * Choose dmic clock between 1MHz and 3MHz. 1562 * It is better for clock to approximate 3MHz. 1563 */ 1564static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1565 struct snd_kcontrol *kcontrol, int event) 1566{ 1567 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1568 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component); 1569 int pd, idx; 1570 1571 pd = rl6231_get_pre_div(rt5659->regmap, 1572 RT5659_ADDA_CLK_1, RT5659_I2S_PD1_SFT); 1573 idx = rl6231_calc_dmic_clk(rt5659->sysclk / pd); 1574 1575 if (idx < 0) 1576 dev_err(component->dev, "Failed to set DMIC clock\n"); 1577 else { 1578 snd_soc_component_update_bits(component, RT5659_DMIC_CTRL_1, 1579 RT5659_DMIC_CLK_MASK, idx << RT5659_DMIC_CLK_SFT); 1580 } 1581 return idx; 1582} 1583 1584static int set_adc1_clk(struct snd_soc_dapm_widget *w, 1585 struct snd_kcontrol *kcontrol, int event) 1586{ 1587 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1588 1589 switch (event) { 1590 case SND_SOC_DAPM_POST_PMU: 1591 snd_soc_component_update_bits(component, RT5659_CHOP_ADC, 1592 RT5659_CKXEN_ADC1_MASK | RT5659_CKGEN_ADC1_MASK, 1593 RT5659_CKXEN_ADC1_MASK | RT5659_CKGEN_ADC1_MASK); 1594 break; 1595 1596 case SND_SOC_DAPM_PRE_PMD: 1597 snd_soc_component_update_bits(component, RT5659_CHOP_ADC, 1598 RT5659_CKXEN_ADC1_MASK | RT5659_CKGEN_ADC1_MASK, 0); 1599 break; 1600 1601 default: 1602 return 0; 1603 } 1604 1605 return 0; 1606 1607} 1608 1609static int set_adc2_clk(struct snd_soc_dapm_widget *w, 1610 struct snd_kcontrol *kcontrol, int event) 1611{ 1612 struct snd_soc_component *component = 1613 snd_soc_dapm_to_component(w->dapm); 1614 1615 switch (event) { 1616 case SND_SOC_DAPM_POST_PMU: 1617 snd_soc_component_update_bits(component, RT5659_CHOP_ADC, 1618 RT5659_CKXEN_ADC2_MASK | RT5659_CKGEN_ADC2_MASK, 1619 RT5659_CKXEN_ADC2_MASK | RT5659_CKGEN_ADC2_MASK); 1620 break; 1621 1622 case SND_SOC_DAPM_PRE_PMD: 1623 snd_soc_component_update_bits(component, RT5659_CHOP_ADC, 1624 RT5659_CKXEN_ADC2_MASK | RT5659_CKGEN_ADC2_MASK, 0); 1625 break; 1626 1627 default: 1628 return 0; 1629 } 1630 1631 return 0; 1632 1633} 1634 1635static int rt5659_charge_pump_event(struct snd_soc_dapm_widget *w, 1636 struct snd_kcontrol *kcontrol, int event) 1637{ 1638 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1639 1640 switch (event) { 1641 case SND_SOC_DAPM_PRE_PMU: 1642 /* Depop */ 1643 snd_soc_component_write(component, RT5659_DEPOP_1, 0x0009); 1644 break; 1645 case SND_SOC_DAPM_POST_PMD: 1646 snd_soc_component_write(component, RT5659_HP_CHARGE_PUMP_1, 0x0c16); 1647 break; 1648 default: 1649 return 0; 1650 } 1651 1652 return 0; 1653} 1654 1655static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w, 1656 struct snd_soc_dapm_widget *sink) 1657{ 1658 unsigned int val; 1659 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1660 1661 val = snd_soc_component_read(component, RT5659_GLB_CLK); 1662 val &= RT5659_SCLK_SRC_MASK; 1663 if (val == RT5659_SCLK_SRC_PLL1) 1664 return 1; 1665 else 1666 return 0; 1667} 1668 1669static int is_using_asrc(struct snd_soc_dapm_widget *w, 1670 struct snd_soc_dapm_widget *sink) 1671{ 1672 unsigned int reg, shift, val; 1673 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1674 1675 switch (w->shift) { 1676 case RT5659_ADC_MONO_R_ASRC_SFT: 1677 reg = RT5659_ASRC_3; 1678 shift = RT5659_AD_MONO_R_T_SFT; 1679 break; 1680 case RT5659_ADC_MONO_L_ASRC_SFT: 1681 reg = RT5659_ASRC_3; 1682 shift = RT5659_AD_MONO_L_T_SFT; 1683 break; 1684 case RT5659_ADC_STO1_ASRC_SFT: 1685 reg = RT5659_ASRC_2; 1686 shift = RT5659_AD_STO1_T_SFT; 1687 break; 1688 case RT5659_DAC_MONO_R_ASRC_SFT: 1689 reg = RT5659_ASRC_2; 1690 shift = RT5659_DA_MONO_R_T_SFT; 1691 break; 1692 case RT5659_DAC_MONO_L_ASRC_SFT: 1693 reg = RT5659_ASRC_2; 1694 shift = RT5659_DA_MONO_L_T_SFT; 1695 break; 1696 case RT5659_DAC_STO_ASRC_SFT: 1697 reg = RT5659_ASRC_2; 1698 shift = RT5659_DA_STO_T_SFT; 1699 break; 1700 default: 1701 return 0; 1702 } 1703 1704 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 1705 switch (val) { 1706 case 1: 1707 case 2: 1708 case 3: 1709 /* I2S_Pre_Div1 should be 1 in asrc mode */ 1710 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1, 1711 RT5659_I2S_PD1_MASK, RT5659_I2S_PD1_2); 1712 return 1; 1713 default: 1714 return 0; 1715 } 1716 1717} 1718 1719/* Digital Mixer */ 1720static const struct snd_kcontrol_new rt5659_sto1_adc_l_mix[] = { 1721 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_STO1_ADC_MIXER, 1722 RT5659_M_STO1_ADC_L1_SFT, 1, 1), 1723 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_STO1_ADC_MIXER, 1724 RT5659_M_STO1_ADC_L2_SFT, 1, 1), 1725}; 1726 1727static const struct snd_kcontrol_new rt5659_sto1_adc_r_mix[] = { 1728 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_STO1_ADC_MIXER, 1729 RT5659_M_STO1_ADC_R1_SFT, 1, 1), 1730 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_STO1_ADC_MIXER, 1731 RT5659_M_STO1_ADC_R2_SFT, 1, 1), 1732}; 1733 1734static const struct snd_kcontrol_new rt5659_mono_adc_l_mix[] = { 1735 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_MONO_ADC_MIXER, 1736 RT5659_M_MONO_ADC_L1_SFT, 1, 1), 1737 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_MONO_ADC_MIXER, 1738 RT5659_M_MONO_ADC_L2_SFT, 1, 1), 1739}; 1740 1741static const struct snd_kcontrol_new rt5659_mono_adc_r_mix[] = { 1742 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_MONO_ADC_MIXER, 1743 RT5659_M_MONO_ADC_R1_SFT, 1, 1), 1744 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_MONO_ADC_MIXER, 1745 RT5659_M_MONO_ADC_R2_SFT, 1, 1), 1746}; 1747 1748static const struct snd_kcontrol_new rt5659_dac_l_mix[] = { 1749 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER, 1750 RT5659_M_ADCMIX_L_SFT, 1, 1), 1751 SOC_DAPM_SINGLE("DAC1 Switch", RT5659_AD_DA_MIXER, 1752 RT5659_M_DAC1_L_SFT, 1, 1), 1753}; 1754 1755static const struct snd_kcontrol_new rt5659_dac_r_mix[] = { 1756 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER, 1757 RT5659_M_ADCMIX_R_SFT, 1, 1), 1758 SOC_DAPM_SINGLE("DAC1 Switch", RT5659_AD_DA_MIXER, 1759 RT5659_M_DAC1_R_SFT, 1, 1), 1760}; 1761 1762static const struct snd_kcontrol_new rt5659_sto_dac_l_mix[] = { 1763 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_STO_DAC_MIXER, 1764 RT5659_M_DAC_L1_STO_L_SFT, 1, 1), 1765 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_STO_DAC_MIXER, 1766 RT5659_M_DAC_R1_STO_L_SFT, 1, 1), 1767 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_STO_DAC_MIXER, 1768 RT5659_M_DAC_L2_STO_L_SFT, 1, 1), 1769 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_STO_DAC_MIXER, 1770 RT5659_M_DAC_R2_STO_L_SFT, 1, 1), 1771}; 1772 1773static const struct snd_kcontrol_new rt5659_sto_dac_r_mix[] = { 1774 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_STO_DAC_MIXER, 1775 RT5659_M_DAC_L1_STO_R_SFT, 1, 1), 1776 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_STO_DAC_MIXER, 1777 RT5659_M_DAC_R1_STO_R_SFT, 1, 1), 1778 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_STO_DAC_MIXER, 1779 RT5659_M_DAC_L2_STO_R_SFT, 1, 1), 1780 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_STO_DAC_MIXER, 1781 RT5659_M_DAC_R2_STO_R_SFT, 1, 1), 1782}; 1783 1784static const struct snd_kcontrol_new rt5659_mono_dac_l_mix[] = { 1785 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_MONO_DAC_MIXER, 1786 RT5659_M_DAC_L1_MONO_L_SFT, 1, 1), 1787 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_MONO_DAC_MIXER, 1788 RT5659_M_DAC_R1_MONO_L_SFT, 1, 1), 1789 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONO_DAC_MIXER, 1790 RT5659_M_DAC_L2_MONO_L_SFT, 1, 1), 1791 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONO_DAC_MIXER, 1792 RT5659_M_DAC_R2_MONO_L_SFT, 1, 1), 1793}; 1794 1795static const struct snd_kcontrol_new rt5659_mono_dac_r_mix[] = { 1796 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_MONO_DAC_MIXER, 1797 RT5659_M_DAC_L1_MONO_R_SFT, 1, 1), 1798 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_MONO_DAC_MIXER, 1799 RT5659_M_DAC_R1_MONO_R_SFT, 1, 1), 1800 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONO_DAC_MIXER, 1801 RT5659_M_DAC_L2_MONO_R_SFT, 1, 1), 1802 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONO_DAC_MIXER, 1803 RT5659_M_DAC_R2_MONO_R_SFT, 1, 1), 1804}; 1805 1806/* Analog Input Mixer */ 1807static const struct snd_kcontrol_new rt5659_rec1_l_mix[] = { 1808 SOC_DAPM_SINGLE("SPKVOLL Switch", RT5659_REC1_L2_MIXER, 1809 RT5659_M_SPKVOLL_RM1_L_SFT, 1, 1), 1810 SOC_DAPM_SINGLE("INL Switch", RT5659_REC1_L2_MIXER, 1811 RT5659_M_INL_RM1_L_SFT, 1, 1), 1812 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC1_L2_MIXER, 1813 RT5659_M_BST4_RM1_L_SFT, 1, 1), 1814 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC1_L2_MIXER, 1815 RT5659_M_BST3_RM1_L_SFT, 1, 1), 1816 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC1_L2_MIXER, 1817 RT5659_M_BST2_RM1_L_SFT, 1, 1), 1818 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC1_L2_MIXER, 1819 RT5659_M_BST1_RM1_L_SFT, 1, 1), 1820}; 1821 1822static const struct snd_kcontrol_new rt5659_rec1_r_mix[] = { 1823 SOC_DAPM_SINGLE("HPOVOLR Switch", RT5659_REC1_L2_MIXER, 1824 RT5659_M_HPOVOLR_RM1_R_SFT, 1, 1), 1825 SOC_DAPM_SINGLE("INR Switch", RT5659_REC1_R2_MIXER, 1826 RT5659_M_INR_RM1_R_SFT, 1, 1), 1827 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC1_R2_MIXER, 1828 RT5659_M_BST4_RM1_R_SFT, 1, 1), 1829 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC1_R2_MIXER, 1830 RT5659_M_BST3_RM1_R_SFT, 1, 1), 1831 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC1_R2_MIXER, 1832 RT5659_M_BST2_RM1_R_SFT, 1, 1), 1833 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC1_R2_MIXER, 1834 RT5659_M_BST1_RM1_R_SFT, 1, 1), 1835}; 1836 1837static const struct snd_kcontrol_new rt5659_rec2_l_mix[] = { 1838 SOC_DAPM_SINGLE("SPKVOLL Switch", RT5659_REC2_L2_MIXER, 1839 RT5659_M_SPKVOL_RM2_L_SFT, 1, 1), 1840 SOC_DAPM_SINGLE("OUTVOLL Switch", RT5659_REC2_L2_MIXER, 1841 RT5659_M_OUTVOLL_RM2_L_SFT, 1, 1), 1842 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC2_L2_MIXER, 1843 RT5659_M_BST4_RM2_L_SFT, 1, 1), 1844 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC2_L2_MIXER, 1845 RT5659_M_BST3_RM2_L_SFT, 1, 1), 1846 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC2_L2_MIXER, 1847 RT5659_M_BST2_RM2_L_SFT, 1, 1), 1848 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC2_L2_MIXER, 1849 RT5659_M_BST1_RM2_L_SFT, 1, 1), 1850}; 1851 1852static const struct snd_kcontrol_new rt5659_rec2_r_mix[] = { 1853 SOC_DAPM_SINGLE("MONOVOL Switch", RT5659_REC2_R2_MIXER, 1854 RT5659_M_MONOVOL_RM2_R_SFT, 1, 1), 1855 SOC_DAPM_SINGLE("OUTVOLR Switch", RT5659_REC2_R2_MIXER, 1856 RT5659_M_OUTVOLR_RM2_R_SFT, 1, 1), 1857 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC2_R2_MIXER, 1858 RT5659_M_BST4_RM2_R_SFT, 1, 1), 1859 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC2_R2_MIXER, 1860 RT5659_M_BST3_RM2_R_SFT, 1, 1), 1861 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC2_R2_MIXER, 1862 RT5659_M_BST2_RM2_R_SFT, 1, 1), 1863 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC2_R2_MIXER, 1864 RT5659_M_BST1_RM2_R_SFT, 1, 1), 1865}; 1866 1867static const struct snd_kcontrol_new rt5659_spk_l_mix[] = { 1868 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_SPK_L_MIXER, 1869 RT5659_M_DAC_L2_SM_L_SFT, 1, 1), 1870 SOC_DAPM_SINGLE("BST1 Switch", RT5659_SPK_L_MIXER, 1871 RT5659_M_BST1_SM_L_SFT, 1, 1), 1872 SOC_DAPM_SINGLE("INL Switch", RT5659_SPK_L_MIXER, 1873 RT5659_M_IN_L_SM_L_SFT, 1, 1), 1874 SOC_DAPM_SINGLE("INR Switch", RT5659_SPK_L_MIXER, 1875 RT5659_M_IN_R_SM_L_SFT, 1, 1), 1876 SOC_DAPM_SINGLE("BST3 Switch", RT5659_SPK_L_MIXER, 1877 RT5659_M_BST3_SM_L_SFT, 1, 1), 1878}; 1879 1880static const struct snd_kcontrol_new rt5659_spk_r_mix[] = { 1881 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_SPK_R_MIXER, 1882 RT5659_M_DAC_R2_SM_R_SFT, 1, 1), 1883 SOC_DAPM_SINGLE("BST4 Switch", RT5659_SPK_R_MIXER, 1884 RT5659_M_BST4_SM_R_SFT, 1, 1), 1885 SOC_DAPM_SINGLE("INL Switch", RT5659_SPK_R_MIXER, 1886 RT5659_M_IN_L_SM_R_SFT, 1, 1), 1887 SOC_DAPM_SINGLE("INR Switch", RT5659_SPK_R_MIXER, 1888 RT5659_M_IN_R_SM_R_SFT, 1, 1), 1889 SOC_DAPM_SINGLE("BST3 Switch", RT5659_SPK_R_MIXER, 1890 RT5659_M_BST3_SM_R_SFT, 1, 1), 1891}; 1892 1893static const struct snd_kcontrol_new rt5659_monovol_mix[] = { 1894 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONOMIX_IN_GAIN, 1895 RT5659_M_DAC_L2_MM_SFT, 1, 1), 1896 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONOMIX_IN_GAIN, 1897 RT5659_M_DAC_R2_MM_SFT, 1, 1), 1898 SOC_DAPM_SINGLE("BST1 Switch", RT5659_MONOMIX_IN_GAIN, 1899 RT5659_M_BST1_MM_SFT, 1, 1), 1900 SOC_DAPM_SINGLE("BST2 Switch", RT5659_MONOMIX_IN_GAIN, 1901 RT5659_M_BST2_MM_SFT, 1, 1), 1902 SOC_DAPM_SINGLE("BST3 Switch", RT5659_MONOMIX_IN_GAIN, 1903 RT5659_M_BST3_MM_SFT, 1, 1), 1904}; 1905 1906static const struct snd_kcontrol_new rt5659_out_l_mix[] = { 1907 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_OUT_L_MIXER, 1908 RT5659_M_DAC_L2_OM_L_SFT, 1, 1), 1909 SOC_DAPM_SINGLE("INL Switch", RT5659_OUT_L_MIXER, 1910 RT5659_M_IN_L_OM_L_SFT, 1, 1), 1911 SOC_DAPM_SINGLE("BST1 Switch", RT5659_OUT_L_MIXER, 1912 RT5659_M_BST1_OM_L_SFT, 1, 1), 1913 SOC_DAPM_SINGLE("BST2 Switch", RT5659_OUT_L_MIXER, 1914 RT5659_M_BST2_OM_L_SFT, 1, 1), 1915 SOC_DAPM_SINGLE("BST3 Switch", RT5659_OUT_L_MIXER, 1916 RT5659_M_BST3_OM_L_SFT, 1, 1), 1917}; 1918 1919static const struct snd_kcontrol_new rt5659_out_r_mix[] = { 1920 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_OUT_R_MIXER, 1921 RT5659_M_DAC_R2_OM_R_SFT, 1, 1), 1922 SOC_DAPM_SINGLE("INR Switch", RT5659_OUT_R_MIXER, 1923 RT5659_M_IN_R_OM_R_SFT, 1, 1), 1924 SOC_DAPM_SINGLE("BST2 Switch", RT5659_OUT_R_MIXER, 1925 RT5659_M_BST2_OM_R_SFT, 1, 1), 1926 SOC_DAPM_SINGLE("BST3 Switch", RT5659_OUT_R_MIXER, 1927 RT5659_M_BST3_OM_R_SFT, 1, 1), 1928 SOC_DAPM_SINGLE("BST4 Switch", RT5659_OUT_R_MIXER, 1929 RT5659_M_BST4_OM_R_SFT, 1, 1), 1930}; 1931 1932static const struct snd_kcontrol_new rt5659_spo_l_mix[] = { 1933 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_SPO_AMP_GAIN, 1934 RT5659_M_DAC_L2_SPKOMIX_SFT, 1, 0), 1935 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5659_SPO_AMP_GAIN, 1936 RT5659_M_SPKVOLL_SPKOMIX_SFT, 1, 0), 1937}; 1938 1939static const struct snd_kcontrol_new rt5659_spo_r_mix[] = { 1940 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_SPO_AMP_GAIN, 1941 RT5659_M_DAC_R2_SPKOMIX_SFT, 1, 0), 1942 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5659_SPO_AMP_GAIN, 1943 RT5659_M_SPKVOLR_SPKOMIX_SFT, 1, 0), 1944}; 1945 1946static const struct snd_kcontrol_new rt5659_mono_mix[] = { 1947 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONOMIX_IN_GAIN, 1948 RT5659_M_DAC_L2_MA_SFT, 1, 1), 1949 SOC_DAPM_SINGLE("MONOVOL Switch", RT5659_MONOMIX_IN_GAIN, 1950 RT5659_M_MONOVOL_MA_SFT, 1, 1), 1951}; 1952 1953static const struct snd_kcontrol_new rt5659_lout_l_mix[] = { 1954 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_LOUT_MIXER, 1955 RT5659_M_DAC_L2_LM_SFT, 1, 1), 1956 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5659_LOUT_MIXER, 1957 RT5659_M_OV_L_LM_SFT, 1, 1), 1958}; 1959 1960static const struct snd_kcontrol_new rt5659_lout_r_mix[] = { 1961 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_LOUT_MIXER, 1962 RT5659_M_DAC_R2_LM_SFT, 1, 1), 1963 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5659_LOUT_MIXER, 1964 RT5659_M_OV_R_LM_SFT, 1, 1), 1965}; 1966 1967/*DAC L2, DAC R2*/ 1968/*MX-1B [6:4], MX-1B [2:0]*/ 1969static const char * const rt5659_dac2_src[] = { 1970 "IF1 DAC2", "IF2 DAC", "IF3 DAC", "Mono ADC MIX" 1971}; 1972 1973static SOC_ENUM_SINGLE_DECL( 1974 rt5659_dac_l2_enum, RT5659_DAC_CTRL, 1975 RT5659_DAC_L2_SEL_SFT, rt5659_dac2_src); 1976 1977static const struct snd_kcontrol_new rt5659_dac_l2_mux = 1978 SOC_DAPM_ENUM("DAC L2 Source", rt5659_dac_l2_enum); 1979 1980static SOC_ENUM_SINGLE_DECL( 1981 rt5659_dac_r2_enum, RT5659_DAC_CTRL, 1982 RT5659_DAC_R2_SEL_SFT, rt5659_dac2_src); 1983 1984static const struct snd_kcontrol_new rt5659_dac_r2_mux = 1985 SOC_DAPM_ENUM("DAC R2 Source", rt5659_dac_r2_enum); 1986 1987 1988/* STO1 ADC1 Source */ 1989/* MX-26 [13] */ 1990static const char * const rt5659_sto1_adc1_src[] = { 1991 "DAC MIX", "ADC" 1992}; 1993 1994static SOC_ENUM_SINGLE_DECL( 1995 rt5659_sto1_adc1_enum, RT5659_STO1_ADC_MIXER, 1996 RT5659_STO1_ADC1_SRC_SFT, rt5659_sto1_adc1_src); 1997 1998static const struct snd_kcontrol_new rt5659_sto1_adc1_mux = 1999 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5659_sto1_adc1_enum); 2000 2001/* STO1 ADC Source */ 2002/* MX-26 [12] */ 2003static const char * const rt5659_sto1_adc_src[] = { 2004 "ADC1", "ADC2" 2005}; 2006 2007static SOC_ENUM_SINGLE_DECL( 2008 rt5659_sto1_adc_enum, RT5659_STO1_ADC_MIXER, 2009 RT5659_STO1_ADC_SRC_SFT, rt5659_sto1_adc_src); 2010 2011static const struct snd_kcontrol_new rt5659_sto1_adc_mux = 2012 SOC_DAPM_ENUM("Stereo1 ADC Source", rt5659_sto1_adc_enum); 2013 2014/* STO1 ADC2 Source */ 2015/* MX-26 [11] */ 2016static const char * const rt5659_sto1_adc2_src[] = { 2017 "DAC MIX", "DMIC" 2018}; 2019 2020static SOC_ENUM_SINGLE_DECL( 2021 rt5659_sto1_adc2_enum, RT5659_STO1_ADC_MIXER, 2022 RT5659_STO1_ADC2_SRC_SFT, rt5659_sto1_adc2_src); 2023 2024static const struct snd_kcontrol_new rt5659_sto1_adc2_mux = 2025 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5659_sto1_adc2_enum); 2026 2027/* STO1 DMIC Source */ 2028/* MX-26 [8] */ 2029static const char * const rt5659_sto1_dmic_src[] = { 2030 "DMIC1", "DMIC2" 2031}; 2032 2033static SOC_ENUM_SINGLE_DECL( 2034 rt5659_sto1_dmic_enum, RT5659_STO1_ADC_MIXER, 2035 RT5659_STO1_DMIC_SRC_SFT, rt5659_sto1_dmic_src); 2036 2037static const struct snd_kcontrol_new rt5659_sto1_dmic_mux = 2038 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5659_sto1_dmic_enum); 2039 2040 2041/* MONO ADC L2 Source */ 2042/* MX-27 [12] */ 2043static const char * const rt5659_mono_adc_l2_src[] = { 2044 "Mono DAC MIXL", "DMIC" 2045}; 2046 2047static SOC_ENUM_SINGLE_DECL( 2048 rt5659_mono_adc_l2_enum, RT5659_MONO_ADC_MIXER, 2049 RT5659_MONO_ADC_L2_SRC_SFT, rt5659_mono_adc_l2_src); 2050 2051static const struct snd_kcontrol_new rt5659_mono_adc_l2_mux = 2052 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5659_mono_adc_l2_enum); 2053 2054 2055/* MONO ADC L1 Source */ 2056/* MX-27 [11] */ 2057static const char * const rt5659_mono_adc_l1_src[] = { 2058 "Mono DAC MIXL", "ADC" 2059}; 2060 2061static SOC_ENUM_SINGLE_DECL( 2062 rt5659_mono_adc_l1_enum, RT5659_MONO_ADC_MIXER, 2063 RT5659_MONO_ADC_L1_SRC_SFT, rt5659_mono_adc_l1_src); 2064 2065static const struct snd_kcontrol_new rt5659_mono_adc_l1_mux = 2066 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5659_mono_adc_l1_enum); 2067 2068/* MONO ADC L Source, MONO ADC R Source*/ 2069/* MX-27 [10:9], MX-27 [2:1] */ 2070static const char * const rt5659_mono_adc_src[] = { 2071 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R" 2072}; 2073 2074static SOC_ENUM_SINGLE_DECL( 2075 rt5659_mono_adc_l_enum, RT5659_MONO_ADC_MIXER, 2076 RT5659_MONO_ADC_L_SRC_SFT, rt5659_mono_adc_src); 2077 2078static const struct snd_kcontrol_new rt5659_mono_adc_l_mux = 2079 SOC_DAPM_ENUM("Mono ADC L Source", rt5659_mono_adc_l_enum); 2080 2081static SOC_ENUM_SINGLE_DECL( 2082 rt5659_mono_adcr_enum, RT5659_MONO_ADC_MIXER, 2083 RT5659_MONO_ADC_R_SRC_SFT, rt5659_mono_adc_src); 2084 2085static const struct snd_kcontrol_new rt5659_mono_adc_r_mux = 2086 SOC_DAPM_ENUM("Mono ADC R Source", rt5659_mono_adcr_enum); 2087 2088/* MONO DMIC L Source */ 2089/* MX-27 [8] */ 2090static const char * const rt5659_mono_dmic_l_src[] = { 2091 "DMIC1 L", "DMIC2 L" 2092}; 2093 2094static SOC_ENUM_SINGLE_DECL( 2095 rt5659_mono_dmic_l_enum, RT5659_MONO_ADC_MIXER, 2096 RT5659_MONO_DMIC_L_SRC_SFT, rt5659_mono_dmic_l_src); 2097 2098static const struct snd_kcontrol_new rt5659_mono_dmic_l_mux = 2099 SOC_DAPM_ENUM("Mono DMIC L Source", rt5659_mono_dmic_l_enum); 2100 2101/* MONO ADC R2 Source */ 2102/* MX-27 [4] */ 2103static const char * const rt5659_mono_adc_r2_src[] = { 2104 "Mono DAC MIXR", "DMIC" 2105}; 2106 2107static SOC_ENUM_SINGLE_DECL( 2108 rt5659_mono_adc_r2_enum, RT5659_MONO_ADC_MIXER, 2109 RT5659_MONO_ADC_R2_SRC_SFT, rt5659_mono_adc_r2_src); 2110 2111static const struct snd_kcontrol_new rt5659_mono_adc_r2_mux = 2112 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5659_mono_adc_r2_enum); 2113 2114/* MONO ADC R1 Source */ 2115/* MX-27 [3] */ 2116static const char * const rt5659_mono_adc_r1_src[] = { 2117 "Mono DAC MIXR", "ADC" 2118}; 2119 2120static SOC_ENUM_SINGLE_DECL( 2121 rt5659_mono_adc_r1_enum, RT5659_MONO_ADC_MIXER, 2122 RT5659_MONO_ADC_R1_SRC_SFT, rt5659_mono_adc_r1_src); 2123 2124static const struct snd_kcontrol_new rt5659_mono_adc_r1_mux = 2125 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5659_mono_adc_r1_enum); 2126 2127/* MONO DMIC R Source */ 2128/* MX-27 [0] */ 2129static const char * const rt5659_mono_dmic_r_src[] = { 2130 "DMIC1 R", "DMIC2 R" 2131}; 2132 2133static SOC_ENUM_SINGLE_DECL( 2134 rt5659_mono_dmic_r_enum, RT5659_MONO_ADC_MIXER, 2135 RT5659_MONO_DMIC_R_SRC_SFT, rt5659_mono_dmic_r_src); 2136 2137static const struct snd_kcontrol_new rt5659_mono_dmic_r_mux = 2138 SOC_DAPM_ENUM("Mono DMIC R Source", rt5659_mono_dmic_r_enum); 2139 2140 2141/* DAC R1 Source, DAC L1 Source*/ 2142/* MX-29 [11:10], MX-29 [9:8]*/ 2143static const char * const rt5659_dac1_src[] = { 2144 "IF1 DAC1", "IF2 DAC", "IF3 DAC" 2145}; 2146 2147static SOC_ENUM_SINGLE_DECL( 2148 rt5659_dac_r1_enum, RT5659_AD_DA_MIXER, 2149 RT5659_DAC1_R_SEL_SFT, rt5659_dac1_src); 2150 2151static const struct snd_kcontrol_new rt5659_dac_r1_mux = 2152 SOC_DAPM_ENUM("DAC R1 Source", rt5659_dac_r1_enum); 2153 2154static SOC_ENUM_SINGLE_DECL( 2155 rt5659_dac_l1_enum, RT5659_AD_DA_MIXER, 2156 RT5659_DAC1_L_SEL_SFT, rt5659_dac1_src); 2157 2158static const struct snd_kcontrol_new rt5659_dac_l1_mux = 2159 SOC_DAPM_ENUM("DAC L1 Source", rt5659_dac_l1_enum); 2160 2161/* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/ 2162/* MX-2C [6], MX-2C [4]*/ 2163static const char * const rt5659_dig_dac_mix_src[] = { 2164 "Stereo DAC Mixer", "Mono DAC Mixer" 2165}; 2166 2167static SOC_ENUM_SINGLE_DECL( 2168 rt5659_dig_dac_mixl_enum, RT5659_DIG_MIXER, 2169 RT5659_DAC_MIX_L_SFT, rt5659_dig_dac_mix_src); 2170 2171static const struct snd_kcontrol_new rt5659_dig_dac_mixl_mux = 2172 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5659_dig_dac_mixl_enum); 2173 2174static SOC_ENUM_SINGLE_DECL( 2175 rt5659_dig_dac_mixr_enum, RT5659_DIG_MIXER, 2176 RT5659_DAC_MIX_R_SFT, rt5659_dig_dac_mix_src); 2177 2178static const struct snd_kcontrol_new rt5659_dig_dac_mixr_mux = 2179 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5659_dig_dac_mixr_enum); 2180 2181/* Analog DAC L1 Source, Analog DAC R1 Source*/ 2182/* MX-2D [3], MX-2D [2]*/ 2183static const char * const rt5659_alg_dac1_src[] = { 2184 "DAC", "Stereo DAC Mixer" 2185}; 2186 2187static SOC_ENUM_SINGLE_DECL( 2188 rt5659_alg_dac_l1_enum, RT5659_A_DAC_MUX, 2189 RT5659_A_DACL1_SFT, rt5659_alg_dac1_src); 2190 2191static const struct snd_kcontrol_new rt5659_alg_dac_l1_mux = 2192 SOC_DAPM_ENUM("Analog DACL1 Source", rt5659_alg_dac_l1_enum); 2193 2194static SOC_ENUM_SINGLE_DECL( 2195 rt5659_alg_dac_r1_enum, RT5659_A_DAC_MUX, 2196 RT5659_A_DACR1_SFT, rt5659_alg_dac1_src); 2197 2198static const struct snd_kcontrol_new rt5659_alg_dac_r1_mux = 2199 SOC_DAPM_ENUM("Analog DACR1 Source", rt5659_alg_dac_r1_enum); 2200 2201/* Analog DAC LR Source, Analog DAC R2 Source*/ 2202/* MX-2D [1], MX-2D [0]*/ 2203static const char * const rt5659_alg_dac2_src[] = { 2204 "Stereo DAC Mixer", "Mono DAC Mixer" 2205}; 2206 2207static SOC_ENUM_SINGLE_DECL( 2208 rt5659_alg_dac_l2_enum, RT5659_A_DAC_MUX, 2209 RT5659_A_DACL2_SFT, rt5659_alg_dac2_src); 2210 2211static const struct snd_kcontrol_new rt5659_alg_dac_l2_mux = 2212 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5659_alg_dac_l2_enum); 2213 2214static SOC_ENUM_SINGLE_DECL( 2215 rt5659_alg_dac_r2_enum, RT5659_A_DAC_MUX, 2216 RT5659_A_DACR2_SFT, rt5659_alg_dac2_src); 2217 2218static const struct snd_kcontrol_new rt5659_alg_dac_r2_mux = 2219 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5659_alg_dac_r2_enum); 2220 2221/* Interface2 ADC Data Input*/ 2222/* MX-2F [13:12] */ 2223static const char * const rt5659_if2_adc_in_src[] = { 2224 "IF_ADC1", "IF_ADC2", "DAC_REF", "IF_ADC3" 2225}; 2226 2227static SOC_ENUM_SINGLE_DECL( 2228 rt5659_if2_adc_in_enum, RT5659_DIG_INF23_DATA, 2229 RT5659_IF2_ADC_IN_SFT, rt5659_if2_adc_in_src); 2230 2231static const struct snd_kcontrol_new rt5659_if2_adc_in_mux = 2232 SOC_DAPM_ENUM("IF2 ADC IN Source", rt5659_if2_adc_in_enum); 2233 2234/* Interface3 ADC Data Input*/ 2235/* MX-2F [1:0] */ 2236static const char * const rt5659_if3_adc_in_src[] = { 2237 "IF_ADC1", "IF_ADC2", "DAC_REF", "Stereo2_ADC_L/R" 2238}; 2239 2240static SOC_ENUM_SINGLE_DECL( 2241 rt5659_if3_adc_in_enum, RT5659_DIG_INF23_DATA, 2242 RT5659_IF3_ADC_IN_SFT, rt5659_if3_adc_in_src); 2243 2244static const struct snd_kcontrol_new rt5659_if3_adc_in_mux = 2245 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5659_if3_adc_in_enum); 2246 2247/* PDM 1 L/R*/ 2248/* MX-31 [15] [13] */ 2249static const char * const rt5659_pdm_src[] = { 2250 "Mono DAC", "Stereo DAC" 2251}; 2252 2253static SOC_ENUM_SINGLE_DECL( 2254 rt5659_pdm_l_enum, RT5659_PDM_OUT_CTRL, 2255 RT5659_PDM1_L_SFT, rt5659_pdm_src); 2256 2257static const struct snd_kcontrol_new rt5659_pdm_l_mux = 2258 SOC_DAPM_ENUM("PDM L Source", rt5659_pdm_l_enum); 2259 2260static SOC_ENUM_SINGLE_DECL( 2261 rt5659_pdm_r_enum, RT5659_PDM_OUT_CTRL, 2262 RT5659_PDM1_R_SFT, rt5659_pdm_src); 2263 2264static const struct snd_kcontrol_new rt5659_pdm_r_mux = 2265 SOC_DAPM_ENUM("PDM R Source", rt5659_pdm_r_enum); 2266 2267/* SPDIF Output source*/ 2268/* MX-36 [1:0] */ 2269static const char * const rt5659_spdif_src[] = { 2270 "IF1_DAC1", "IF1_DAC2", "IF2_DAC", "IF3_DAC" 2271}; 2272 2273static SOC_ENUM_SINGLE_DECL( 2274 rt5659_spdif_enum, RT5659_SPDIF_CTRL, 2275 RT5659_SPDIF_SEL_SFT, rt5659_spdif_src); 2276 2277static const struct snd_kcontrol_new rt5659_spdif_mux = 2278 SOC_DAPM_ENUM("SPDIF Source", rt5659_spdif_enum); 2279 2280/* I2S1 TDM ADCDAT Source */ 2281/* MX-78[4:0] */ 2282static const char * const rt5659_rx_adc_data_src[] = { 2283 "AD1:AD2:DAC:NUL", "AD1:AD2:NUL:DAC", "AD1:DAC:AD2:NUL", 2284 "AD1:DAC:NUL:AD2", "AD1:NUL:DAC:AD2", "AD1:NUL:AD2:DAC", 2285 "AD2:AD1:DAC:NUL", "AD2:AD1:NUL:DAC", "AD2:DAC:AD1:NUL", 2286 "AD2:DAC:NUL:AD1", "AD2:NUL:DAC:AD1", "AD1:NUL:AD1:DAC", 2287 "DAC:AD1:AD2:NUL", "DAC:AD1:NUL:AD2", "DAC:AD2:AD1:NUL", 2288 "DAC:AD2:NUL:AD1", "DAC:NUL:DAC:AD2", "DAC:NUL:AD2:DAC", 2289 "NUL:AD1:AD2:DAC", "NUL:AD1:DAC:AD2", "NUL:AD2:AD1:DAC", 2290 "NUL:AD2:DAC:AD1", "NUL:DAC:DAC:AD2", "NUL:DAC:AD2:DAC" 2291}; 2292 2293static SOC_ENUM_SINGLE_DECL( 2294 rt5659_rx_adc_data_enum, RT5659_TDM_CTRL_2, 2295 RT5659_ADCDAT_SRC_SFT, rt5659_rx_adc_data_src); 2296 2297static const struct snd_kcontrol_new rt5659_rx_adc_dac_mux = 2298 SOC_DAPM_ENUM("TDM ADCDAT Source", rt5659_rx_adc_data_enum); 2299 2300/* Out Volume Switch */ 2301static const struct snd_kcontrol_new spkvol_l_switch = 2302 SOC_DAPM_SINGLE("Switch", RT5659_SPO_VOL, RT5659_VOL_L_SFT, 1, 1); 2303 2304static const struct snd_kcontrol_new spkvol_r_switch = 2305 SOC_DAPM_SINGLE("Switch", RT5659_SPO_VOL, RT5659_VOL_R_SFT, 1, 1); 2306 2307static const struct snd_kcontrol_new monovol_switch = 2308 SOC_DAPM_SINGLE("Switch", RT5659_MONO_OUT, RT5659_VOL_L_SFT, 1, 1); 2309 2310static const struct snd_kcontrol_new outvol_l_switch = 2311 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_VOL_L_SFT, 1, 1); 2312 2313static const struct snd_kcontrol_new outvol_r_switch = 2314 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_VOL_R_SFT, 1, 1); 2315 2316/* Out Switch */ 2317static const struct snd_kcontrol_new spo_switch = 2318 SOC_DAPM_SINGLE("Switch", RT5659_CLASSD_2, RT5659_M_RF_DIG_SFT, 1, 1); 2319 2320static const struct snd_kcontrol_new mono_switch = 2321 SOC_DAPM_SINGLE("Switch", RT5659_MONO_OUT, RT5659_L_MUTE_SFT, 1, 1); 2322 2323static const struct snd_kcontrol_new hpo_l_switch = 2324 SOC_DAPM_SINGLE("Switch", RT5659_HP_VOL, RT5659_L_MUTE_SFT, 1, 1); 2325 2326static const struct snd_kcontrol_new hpo_r_switch = 2327 SOC_DAPM_SINGLE("Switch", RT5659_HP_VOL, RT5659_R_MUTE_SFT, 1, 1); 2328 2329static const struct snd_kcontrol_new lout_l_switch = 2330 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_L_MUTE_SFT, 1, 1); 2331 2332static const struct snd_kcontrol_new lout_r_switch = 2333 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_R_MUTE_SFT, 1, 1); 2334 2335static const struct snd_kcontrol_new pdm_l_switch = 2336 SOC_DAPM_SINGLE("Switch", RT5659_PDM_OUT_CTRL, RT5659_M_PDM1_L_SFT, 1, 2337 1); 2338 2339static const struct snd_kcontrol_new pdm_r_switch = 2340 SOC_DAPM_SINGLE("Switch", RT5659_PDM_OUT_CTRL, RT5659_M_PDM1_R_SFT, 1, 2341 1); 2342 2343static int rt5659_spk_event(struct snd_soc_dapm_widget *w, 2344 struct snd_kcontrol *kcontrol, int event) 2345{ 2346 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2347 2348 switch (event) { 2349 case SND_SOC_DAPM_PRE_PMU: 2350 snd_soc_component_update_bits(component, RT5659_CLASSD_CTRL_1, 2351 RT5659_POW_CLSD_DB_MASK, RT5659_POW_CLSD_DB_EN); 2352 snd_soc_component_update_bits(component, RT5659_CLASSD_2, 2353 RT5659_M_RI_DIG, RT5659_M_RI_DIG); 2354 snd_soc_component_write(component, RT5659_CLASSD_1, 0x0803); 2355 snd_soc_component_write(component, RT5659_SPK_DC_CAILB_CTRL_3, 0x0000); 2356 break; 2357 2358 case SND_SOC_DAPM_POST_PMD: 2359 snd_soc_component_write(component, RT5659_CLASSD_1, 0x0011); 2360 snd_soc_component_update_bits(component, RT5659_CLASSD_2, 2361 RT5659_M_RI_DIG, 0x0); 2362 snd_soc_component_write(component, RT5659_SPK_DC_CAILB_CTRL_3, 0x0003); 2363 snd_soc_component_update_bits(component, RT5659_CLASSD_CTRL_1, 2364 RT5659_POW_CLSD_DB_MASK, RT5659_POW_CLSD_DB_DIS); 2365 break; 2366 2367 default: 2368 return 0; 2369 } 2370 2371 return 0; 2372 2373} 2374 2375static int rt5659_mono_event(struct snd_soc_dapm_widget *w, 2376 struct snd_kcontrol *kcontrol, int event) 2377{ 2378 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2379 2380 switch (event) { 2381 case SND_SOC_DAPM_PRE_PMU: 2382 snd_soc_component_write(component, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e00); 2383 break; 2384 2385 case SND_SOC_DAPM_POST_PMD: 2386 snd_soc_component_write(component, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e04); 2387 break; 2388 2389 default: 2390 return 0; 2391 } 2392 2393 return 0; 2394 2395} 2396 2397static int rt5659_hp_event(struct snd_soc_dapm_widget *w, 2398 struct snd_kcontrol *kcontrol, int event) 2399{ 2400 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2401 2402 switch (event) { 2403 case SND_SOC_DAPM_POST_PMU: 2404 snd_soc_component_write(component, RT5659_HP_CHARGE_PUMP_1, 0x0e1e); 2405 snd_soc_component_update_bits(component, RT5659_DEPOP_1, 0x0010, 0x0010); 2406 break; 2407 2408 case SND_SOC_DAPM_PRE_PMD: 2409 snd_soc_component_write(component, RT5659_DEPOP_1, 0x0000); 2410 break; 2411 2412 default: 2413 return 0; 2414 } 2415 2416 return 0; 2417} 2418 2419static int set_dmic_power(struct snd_soc_dapm_widget *w, 2420 struct snd_kcontrol *kcontrol, int event) 2421{ 2422 switch (event) { 2423 case SND_SOC_DAPM_POST_PMU: 2424 /*Add delay to avoid pop noise*/ 2425 msleep(450); 2426 break; 2427 2428 default: 2429 return 0; 2430 } 2431 2432 return 0; 2433} 2434 2435static const struct snd_soc_dapm_widget rt5659_particular_dapm_widgets[] = { 2436 SND_SOC_DAPM_SUPPLY("LDO2", RT5659_PWR_ANLG_3, RT5659_PWR_LDO2_BIT, 0, 2437 NULL, 0), 2438 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5659_PWR_ANLG_2, RT5659_PWR_MB1_BIT, 2439 0, NULL, 0), 2440 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5659_PWR_VOL, 2441 RT5659_PWR_MIC_DET_BIT, 0, NULL, 0), 2442}; 2443 2444static const struct snd_soc_dapm_widget rt5659_dapm_widgets[] = { 2445 SND_SOC_DAPM_SUPPLY("PLL", RT5659_PWR_ANLG_3, RT5659_PWR_PLL_BIT, 0, 2446 NULL, 0), 2447 SND_SOC_DAPM_SUPPLY("Mono Vref", RT5659_PWR_ANLG_1, 2448 RT5659_PWR_VREF3_BIT, 0, NULL, 0), 2449 2450 /* ASRC */ 2451 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5659_ASRC_1, 2452 RT5659_I2S1_ASRC_SFT, 0, NULL, 0), 2453 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5659_ASRC_1, 2454 RT5659_I2S2_ASRC_SFT, 0, NULL, 0), 2455 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5659_ASRC_1, 2456 RT5659_I2S3_ASRC_SFT, 0, NULL, 0), 2457 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5659_ASRC_1, 2458 RT5659_DAC_STO_ASRC_SFT, 0, NULL, 0), 2459 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5659_ASRC_1, 2460 RT5659_DAC_MONO_L_ASRC_SFT, 0, NULL, 0), 2461 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5659_ASRC_1, 2462 RT5659_DAC_MONO_R_ASRC_SFT, 0, NULL, 0), 2463 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5659_ASRC_1, 2464 RT5659_ADC_STO1_ASRC_SFT, 0, NULL, 0), 2465 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5659_ASRC_1, 2466 RT5659_ADC_MONO_L_ASRC_SFT, 0, NULL, 0), 2467 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5659_ASRC_1, 2468 RT5659_ADC_MONO_R_ASRC_SFT, 0, NULL, 0), 2469 2470 /* Input Side */ 2471 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5659_PWR_ANLG_2, RT5659_PWR_MB2_BIT, 2472 0, NULL, 0), 2473 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5659_PWR_ANLG_2, RT5659_PWR_MB3_BIT, 2474 0, NULL, 0), 2475 2476 /* Input Lines */ 2477 SND_SOC_DAPM_INPUT("DMIC L1"), 2478 SND_SOC_DAPM_INPUT("DMIC R1"), 2479 SND_SOC_DAPM_INPUT("DMIC L2"), 2480 SND_SOC_DAPM_INPUT("DMIC R2"), 2481 2482 SND_SOC_DAPM_INPUT("IN1P"), 2483 SND_SOC_DAPM_INPUT("IN1N"), 2484 SND_SOC_DAPM_INPUT("IN2P"), 2485 SND_SOC_DAPM_INPUT("IN2N"), 2486 SND_SOC_DAPM_INPUT("IN3P"), 2487 SND_SOC_DAPM_INPUT("IN3N"), 2488 SND_SOC_DAPM_INPUT("IN4P"), 2489 SND_SOC_DAPM_INPUT("IN4N"), 2490 2491 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2492 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2493 2494 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 2495 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 2496 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5659_DMIC_CTRL_1, 2497 RT5659_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), 2498 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5659_DMIC_CTRL_1, 2499 RT5659_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), 2500 2501 /* Boost */ 2502 SND_SOC_DAPM_PGA("BST1", RT5659_PWR_ANLG_2, 2503 RT5659_PWR_BST1_P_BIT, 0, NULL, 0), 2504 SND_SOC_DAPM_PGA("BST2", RT5659_PWR_ANLG_2, 2505 RT5659_PWR_BST2_P_BIT, 0, NULL, 0), 2506 SND_SOC_DAPM_PGA("BST3", RT5659_PWR_ANLG_2, 2507 RT5659_PWR_BST3_P_BIT, 0, NULL, 0), 2508 SND_SOC_DAPM_PGA("BST4", RT5659_PWR_ANLG_2, 2509 RT5659_PWR_BST4_P_BIT, 0, NULL, 0), 2510 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5659_PWR_ANLG_2, 2511 RT5659_PWR_BST1_BIT, 0, NULL, 0), 2512 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5659_PWR_ANLG_2, 2513 RT5659_PWR_BST2_BIT, 0, NULL, 0), 2514 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5659_PWR_ANLG_2, 2515 RT5659_PWR_BST3_BIT, 0, NULL, 0), 2516 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5659_PWR_ANLG_2, 2517 RT5659_PWR_BST4_BIT, 0, NULL, 0), 2518 2519 2520 /* Input Volume */ 2521 SND_SOC_DAPM_PGA("INL VOL", RT5659_PWR_VOL, RT5659_PWR_IN_L_BIT, 2522 0, NULL, 0), 2523 SND_SOC_DAPM_PGA("INR VOL", RT5659_PWR_VOL, RT5659_PWR_IN_R_BIT, 2524 0, NULL, 0), 2525 2526 /* REC Mixer */ 2527 SND_SOC_DAPM_MIXER("RECMIX1L", RT5659_PWR_MIXER, RT5659_PWR_RM1_L_BIT, 2528 0, rt5659_rec1_l_mix, ARRAY_SIZE(rt5659_rec1_l_mix)), 2529 SND_SOC_DAPM_MIXER("RECMIX1R", RT5659_PWR_MIXER, RT5659_PWR_RM1_R_BIT, 2530 0, rt5659_rec1_r_mix, ARRAY_SIZE(rt5659_rec1_r_mix)), 2531 SND_SOC_DAPM_MIXER("RECMIX2L", RT5659_PWR_MIXER, RT5659_PWR_RM2_L_BIT, 2532 0, rt5659_rec2_l_mix, ARRAY_SIZE(rt5659_rec2_l_mix)), 2533 SND_SOC_DAPM_MIXER("RECMIX2R", RT5659_PWR_MIXER, RT5659_PWR_RM2_R_BIT, 2534 0, rt5659_rec2_r_mix, ARRAY_SIZE(rt5659_rec2_r_mix)), 2535 2536 /* ADCs */ 2537 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 2538 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 2539 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0), 2540 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0), 2541 2542 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5659_PWR_DIG_1, 2543 RT5659_PWR_ADC_L1_BIT, 0, NULL, 0), 2544 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5659_PWR_DIG_1, 2545 RT5659_PWR_ADC_R1_BIT, 0, NULL, 0), 2546 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5659_PWR_DIG_1, 2547 RT5659_PWR_ADC_L2_BIT, 0, NULL, 0), 2548 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5659_PWR_DIG_1, 2549 RT5659_PWR_ADC_R2_BIT, 0, NULL, 0), 2550 SND_SOC_DAPM_SUPPLY("ADC1 clock", SND_SOC_NOPM, 0, 0, set_adc1_clk, 2551 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2552 SND_SOC_DAPM_SUPPLY("ADC2 clock", SND_SOC_NOPM, 0, 0, set_adc2_clk, 2553 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2554 2555 /* ADC Mux */ 2556 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0, 2557 &rt5659_sto1_dmic_mux), 2558 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0, 2559 &rt5659_sto1_dmic_mux), 2560 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 2561 &rt5659_sto1_adc1_mux), 2562 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 2563 &rt5659_sto1_adc1_mux), 2564 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 2565 &rt5659_sto1_adc2_mux), 2566 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 2567 &rt5659_sto1_adc2_mux), 2568 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 2569 &rt5659_sto1_adc_mux), 2570 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 2571 &rt5659_sto1_adc_mux), 2572 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0, 2573 &rt5659_mono_adc_l2_mux), 2574 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0, 2575 &rt5659_mono_adc_r2_mux), 2576 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0, 2577 &rt5659_mono_adc_l1_mux), 2578 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0, 2579 &rt5659_mono_adc_r1_mux), 2580 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 2581 &rt5659_mono_dmic_l_mux), 2582 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 2583 &rt5659_mono_dmic_r_mux), 2584 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0, 2585 &rt5659_mono_adc_l_mux), 2586 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0, 2587 &rt5659_mono_adc_r_mux), 2588 /* ADC Mixer */ 2589 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5659_PWR_DIG_2, 2590 RT5659_PWR_ADC_S1F_BIT, 0, NULL, 0), 2591 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5659_PWR_DIG_2, 2592 RT5659_PWR_ADC_S2F_BIT, 0, NULL, 0), 2593 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 2594 0, 0, rt5659_sto1_adc_l_mix, 2595 ARRAY_SIZE(rt5659_sto1_adc_l_mix)), 2596 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 2597 0, 0, rt5659_sto1_adc_r_mix, 2598 ARRAY_SIZE(rt5659_sto1_adc_r_mix)), 2599 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5659_PWR_DIG_2, 2600 RT5659_PWR_ADC_MF_L_BIT, 0, NULL, 0), 2601 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5659_MONO_ADC_DIG_VOL, 2602 RT5659_L_MUTE_SFT, 1, rt5659_mono_adc_l_mix, 2603 ARRAY_SIZE(rt5659_mono_adc_l_mix)), 2604 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5659_PWR_DIG_2, 2605 RT5659_PWR_ADC_MF_R_BIT, 0, NULL, 0), 2606 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5659_MONO_ADC_DIG_VOL, 2607 RT5659_R_MUTE_SFT, 1, rt5659_mono_adc_r_mix, 2608 ARRAY_SIZE(rt5659_mono_adc_r_mix)), 2609 2610 /* ADC PGA */ 2611 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2612 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2613 SND_SOC_DAPM_PGA("IF_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2614 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2615 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2616 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2617 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2618 SND_SOC_DAPM_PGA("Stereo2 ADC LR", SND_SOC_NOPM, 0, 0, NULL, 0), 2619 2620 SND_SOC_DAPM_PGA("Stereo1 ADC Volume L", RT5659_STO1_ADC_DIG_VOL, 2621 RT5659_L_MUTE_SFT, 1, NULL, 0), 2622 SND_SOC_DAPM_PGA("Stereo1 ADC Volume R", RT5659_STO1_ADC_DIG_VOL, 2623 RT5659_R_MUTE_SFT, 1, NULL, 0), 2624 2625 /* Digital Interface */ 2626 SND_SOC_DAPM_SUPPLY("I2S1", RT5659_PWR_DIG_1, RT5659_PWR_I2S1_BIT, 2627 0, NULL, 0), 2628 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2629 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2630 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 2631 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 2632 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0), 2633 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0), 2634 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2635 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2636 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2637 SND_SOC_DAPM_SUPPLY("I2S2", RT5659_PWR_DIG_1, RT5659_PWR_I2S2_BIT, 0, 2638 NULL, 0), 2639 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2640 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2641 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2642 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2643 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2644 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2645 SND_SOC_DAPM_SUPPLY("I2S3", RT5659_PWR_DIG_1, RT5659_PWR_I2S3_BIT, 0, 2646 NULL, 0), 2647 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2648 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2649 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2650 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2651 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2652 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2653 2654 /* Digital Interface Select */ 2655 SND_SOC_DAPM_PGA("TDM AD1:AD2:DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2656 SND_SOC_DAPM_PGA("TDM AD2:DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2657 SND_SOC_DAPM_MUX("TDM Data Mux", SND_SOC_NOPM, 0, 0, 2658 &rt5659_rx_adc_dac_mux), 2659 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 0, 0, 2660 &rt5659_if2_adc_in_mux), 2661 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0, 2662 &rt5659_if3_adc_in_mux), 2663 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2664 &rt5659_if1_01_adc_swap_mux), 2665 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2666 &rt5659_if1_23_adc_swap_mux), 2667 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2668 &rt5659_if1_45_adc_swap_mux), 2669 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2670 &rt5659_if1_67_adc_swap_mux), 2671 SND_SOC_DAPM_MUX("IF2 DAC Swap Mux", SND_SOC_NOPM, 0, 0, 2672 &rt5659_if2_dac_swap_mux), 2673 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2674 &rt5659_if2_adc_swap_mux), 2675 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0, 2676 &rt5659_if3_dac_swap_mux), 2677 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 2678 &rt5659_if3_adc_swap_mux), 2679 2680 /* Audio Interface */ 2681 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 2682 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 2683 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 2684 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 2685 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 2686 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 2687 2688 /* Output Side */ 2689 /* DAC mixer before sound effect */ 2690 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 2691 rt5659_dac_l_mix, ARRAY_SIZE(rt5659_dac_l_mix)), 2692 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 2693 rt5659_dac_r_mix, ARRAY_SIZE(rt5659_dac_r_mix)), 2694 2695 /* DAC channel Mux */ 2696 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_l1_mux), 2697 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_r1_mux), 2698 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_l2_mux), 2699 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_r2_mux), 2700 2701 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 2702 &rt5659_alg_dac_l1_mux), 2703 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 2704 &rt5659_alg_dac_r1_mux), 2705 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0, 2706 &rt5659_alg_dac_l2_mux), 2707 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0, 2708 &rt5659_alg_dac_r2_mux), 2709 2710 /* DAC Mixer */ 2711 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5659_PWR_DIG_2, 2712 RT5659_PWR_DAC_S1F_BIT, 0, NULL, 0), 2713 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5659_PWR_DIG_2, 2714 RT5659_PWR_DAC_MF_L_BIT, 0, NULL, 0), 2715 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5659_PWR_DIG_2, 2716 RT5659_PWR_DAC_MF_R_BIT, 0, NULL, 0), 2717 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 2718 rt5659_sto_dac_l_mix, ARRAY_SIZE(rt5659_sto_dac_l_mix)), 2719 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 2720 rt5659_sto_dac_r_mix, ARRAY_SIZE(rt5659_sto_dac_r_mix)), 2721 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 2722 rt5659_mono_dac_l_mix, ARRAY_SIZE(rt5659_mono_dac_l_mix)), 2723 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 2724 rt5659_mono_dac_r_mix, ARRAY_SIZE(rt5659_mono_dac_r_mix)), 2725 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0, 2726 &rt5659_dig_dac_mixl_mux), 2727 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0, 2728 &rt5659_dig_dac_mixr_mux), 2729 2730 /* DACs */ 2731 SND_SOC_DAPM_SUPPLY_S("DAC L1 Power", 1, RT5659_PWR_DIG_1, 2732 RT5659_PWR_DAC_L1_BIT, 0, NULL, 0), 2733 SND_SOC_DAPM_SUPPLY_S("DAC R1 Power", 1, RT5659_PWR_DIG_1, 2734 RT5659_PWR_DAC_R1_BIT, 0, NULL, 0), 2735 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0), 2736 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0), 2737 2738 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5659_PWR_DIG_1, 2739 RT5659_PWR_DAC_L2_BIT, 0, NULL, 0), 2740 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5659_PWR_DIG_1, 2741 RT5659_PWR_DAC_R2_BIT, 0, NULL, 0), 2742 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0), 2743 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0), 2744 SND_SOC_DAPM_PGA("DAC_REF", SND_SOC_NOPM, 0, 0, NULL, 0), 2745 2746 /* OUT Mixer */ 2747 SND_SOC_DAPM_MIXER("SPK MIXL", RT5659_PWR_MIXER, RT5659_PWR_SM_L_BIT, 2748 0, rt5659_spk_l_mix, ARRAY_SIZE(rt5659_spk_l_mix)), 2749 SND_SOC_DAPM_MIXER("SPK MIXR", RT5659_PWR_MIXER, RT5659_PWR_SM_R_BIT, 2750 0, rt5659_spk_r_mix, ARRAY_SIZE(rt5659_spk_r_mix)), 2751 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5659_PWR_MIXER, RT5659_PWR_MM_BIT, 2752 0, rt5659_monovol_mix, ARRAY_SIZE(rt5659_monovol_mix)), 2753 SND_SOC_DAPM_MIXER("OUT MIXL", RT5659_PWR_MIXER, RT5659_PWR_OM_L_BIT, 2754 0, rt5659_out_l_mix, ARRAY_SIZE(rt5659_out_l_mix)), 2755 SND_SOC_DAPM_MIXER("OUT MIXR", RT5659_PWR_MIXER, RT5659_PWR_OM_R_BIT, 2756 0, rt5659_out_r_mix, ARRAY_SIZE(rt5659_out_r_mix)), 2757 2758 /* Output Volume */ 2759 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5659_PWR_VOL, RT5659_PWR_SV_L_BIT, 0, 2760 &spkvol_l_switch), 2761 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5659_PWR_VOL, RT5659_PWR_SV_R_BIT, 0, 2762 &spkvol_r_switch), 2763 SND_SOC_DAPM_SWITCH("MONOVOL", RT5659_PWR_VOL, RT5659_PWR_MV_BIT, 0, 2764 &monovol_switch), 2765 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5659_PWR_VOL, RT5659_PWR_OV_L_BIT, 0, 2766 &outvol_l_switch), 2767 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5659_PWR_VOL, RT5659_PWR_OV_R_BIT, 0, 2768 &outvol_r_switch), 2769 2770 /* SPO/MONO/HPO/LOUT */ 2771 SND_SOC_DAPM_MIXER("SPO L MIX", SND_SOC_NOPM, 0, 0, rt5659_spo_l_mix, 2772 ARRAY_SIZE(rt5659_spo_l_mix)), 2773 SND_SOC_DAPM_MIXER("SPO R MIX", SND_SOC_NOPM, 0, 0, rt5659_spo_r_mix, 2774 ARRAY_SIZE(rt5659_spo_r_mix)), 2775 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5659_mono_mix, 2776 ARRAY_SIZE(rt5659_mono_mix)), 2777 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5659_lout_l_mix, 2778 ARRAY_SIZE(rt5659_lout_l_mix)), 2779 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5659_lout_r_mix, 2780 ARRAY_SIZE(rt5659_lout_r_mix)), 2781 2782 SND_SOC_DAPM_PGA_S("SPK Amp", 1, RT5659_PWR_DIG_1, RT5659_PWR_CLS_D_BIT, 2783 0, rt5659_spk_event, SND_SOC_DAPM_POST_PMD | 2784 SND_SOC_DAPM_PRE_PMU), 2785 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5659_PWR_ANLG_1, RT5659_PWR_MA_BIT, 2786 0, rt5659_mono_event, SND_SOC_DAPM_POST_PMD | 2787 SND_SOC_DAPM_PRE_PMU), 2788 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5659_hp_event, 2789 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2790 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5659_PWR_ANLG_1, RT5659_PWR_LM_BIT, 2791 0, NULL, 0), 2792 2793 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0, 2794 rt5659_charge_pump_event, SND_SOC_DAPM_PRE_PMU | 2795 SND_SOC_DAPM_POST_PMD), 2796 2797 SND_SOC_DAPM_SWITCH("SPO Playback", SND_SOC_NOPM, 0, 0, &spo_switch), 2798 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0, 2799 &mono_switch), 2800 SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0, 2801 &hpo_l_switch), 2802 SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0, 2803 &hpo_r_switch), 2804 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0, 2805 &lout_l_switch), 2806 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0, 2807 &lout_r_switch), 2808 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0, 2809 &pdm_l_switch), 2810 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0, 2811 &pdm_r_switch), 2812 2813 /* PDM */ 2814 SND_SOC_DAPM_SUPPLY("PDM Power", RT5659_PWR_DIG_2, 2815 RT5659_PWR_PDM1_BIT, 0, NULL, 0), 2816 SND_SOC_DAPM_MUX("PDM L Mux", RT5659_PDM_OUT_CTRL, 2817 RT5659_M_PDM1_L_SFT, 1, &rt5659_pdm_l_mux), 2818 SND_SOC_DAPM_MUX("PDM R Mux", RT5659_PDM_OUT_CTRL, 2819 RT5659_M_PDM1_R_SFT, 1, &rt5659_pdm_r_mux), 2820 2821 /* SPDIF */ 2822 SND_SOC_DAPM_MUX("SPDIF Mux", SND_SOC_NOPM, 0, 0, &rt5659_spdif_mux), 2823 2824 SND_SOC_DAPM_SUPPLY("SYS CLK DET", RT5659_CLK_DET, 3, 0, NULL, 0), 2825 SND_SOC_DAPM_SUPPLY("CLKDET", RT5659_CLK_DET, 0, 0, NULL, 0), 2826 2827 /* Output Lines */ 2828 SND_SOC_DAPM_OUTPUT("HPOL"), 2829 SND_SOC_DAPM_OUTPUT("HPOR"), 2830 SND_SOC_DAPM_OUTPUT("SPOL"), 2831 SND_SOC_DAPM_OUTPUT("SPOR"), 2832 SND_SOC_DAPM_OUTPUT("LOUTL"), 2833 SND_SOC_DAPM_OUTPUT("LOUTR"), 2834 SND_SOC_DAPM_OUTPUT("MONOOUT"), 2835 SND_SOC_DAPM_OUTPUT("PDML"), 2836 SND_SOC_DAPM_OUTPUT("PDMR"), 2837 SND_SOC_DAPM_OUTPUT("SPDIF"), 2838}; 2839 2840static const struct snd_soc_dapm_route rt5659_dapm_routes[] = { 2841 /*PLL*/ 2842 { "ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll }, 2843 { "ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll }, 2844 { "ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll }, 2845 { "ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll }, 2846 { "DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll }, 2847 { "DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll }, 2848 { "DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll }, 2849 2850 /*ASRC*/ 2851 { "ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc }, 2852 { "ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc }, 2853 { "ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc }, 2854 { "DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc }, 2855 { "DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc }, 2856 { "DAC Stereo1 Filter", NULL, "DAC STO ASRC", is_using_asrc }, 2857 2858 { "SYS CLK DET", NULL, "CLKDET" }, 2859 2860 { "I2S1", NULL, "I2S1 ASRC" }, 2861 { "I2S2", NULL, "I2S2 ASRC" }, 2862 { "I2S3", NULL, "I2S3 ASRC" }, 2863 2864 { "DMIC1", NULL, "DMIC L1" }, 2865 { "DMIC1", NULL, "DMIC R1" }, 2866 { "DMIC2", NULL, "DMIC L2" }, 2867 { "DMIC2", NULL, "DMIC R2" }, 2868 2869 { "BST1", NULL, "IN1P" }, 2870 { "BST1", NULL, "IN1N" }, 2871 { "BST1", NULL, "BST1 Power" }, 2872 { "BST2", NULL, "IN2P" }, 2873 { "BST2", NULL, "IN2N" }, 2874 { "BST2", NULL, "BST2 Power" }, 2875 { "BST3", NULL, "IN3P" }, 2876 { "BST3", NULL, "IN3N" }, 2877 { "BST3", NULL, "BST3 Power" }, 2878 { "BST4", NULL, "IN4P" }, 2879 { "BST4", NULL, "IN4N" }, 2880 { "BST4", NULL, "BST4 Power" }, 2881 2882 { "INL VOL", NULL, "IN2P" }, 2883 { "INR VOL", NULL, "IN2N" }, 2884 2885 { "RECMIX1L", "SPKVOLL Switch", "SPKVOL L" }, 2886 { "RECMIX1L", "INL Switch", "INL VOL" }, 2887 { "RECMIX1L", "BST4 Switch", "BST4" }, 2888 { "RECMIX1L", "BST3 Switch", "BST3" }, 2889 { "RECMIX1L", "BST2 Switch", "BST2" }, 2890 { "RECMIX1L", "BST1 Switch", "BST1" }, 2891 2892 { "RECMIX1R", "HPOVOLR Switch", "HPO R Playback" }, 2893 { "RECMIX1R", "INR Switch", "INR VOL" }, 2894 { "RECMIX1R", "BST4 Switch", "BST4" }, 2895 { "RECMIX1R", "BST3 Switch", "BST3" }, 2896 { "RECMIX1R", "BST2 Switch", "BST2" }, 2897 { "RECMIX1R", "BST1 Switch", "BST1" }, 2898 2899 { "RECMIX2L", "SPKVOLL Switch", "SPKVOL L" }, 2900 { "RECMIX2L", "OUTVOLL Switch", "OUTVOL L" }, 2901 { "RECMIX2L", "BST4 Switch", "BST4" }, 2902 { "RECMIX2L", "BST3 Switch", "BST3" }, 2903 { "RECMIX2L", "BST2 Switch", "BST2" }, 2904 { "RECMIX2L", "BST1 Switch", "BST1" }, 2905 2906 { "RECMIX2R", "MONOVOL Switch", "MONOVOL" }, 2907 { "RECMIX2R", "OUTVOLR Switch", "OUTVOL R" }, 2908 { "RECMIX2R", "BST4 Switch", "BST4" }, 2909 { "RECMIX2R", "BST3 Switch", "BST3" }, 2910 { "RECMIX2R", "BST2 Switch", "BST2" }, 2911 { "RECMIX2R", "BST1 Switch", "BST1" }, 2912 2913 { "ADC1 L", NULL, "RECMIX1L" }, 2914 { "ADC1 L", NULL, "ADC1 L Power" }, 2915 { "ADC1 L", NULL, "ADC1 clock" }, 2916 { "ADC1 R", NULL, "RECMIX1R" }, 2917 { "ADC1 R", NULL, "ADC1 R Power" }, 2918 { "ADC1 R", NULL, "ADC1 clock" }, 2919 2920 { "ADC2 L", NULL, "RECMIX2L" }, 2921 { "ADC2 L", NULL, "ADC2 L Power" }, 2922 { "ADC2 L", NULL, "ADC2 clock" }, 2923 { "ADC2 R", NULL, "RECMIX2R" }, 2924 { "ADC2 R", NULL, "ADC2 R Power" }, 2925 { "ADC2 R", NULL, "ADC2 clock" }, 2926 2927 { "DMIC L1", NULL, "DMIC CLK" }, 2928 { "DMIC L1", NULL, "DMIC1 Power" }, 2929 { "DMIC R1", NULL, "DMIC CLK" }, 2930 { "DMIC R1", NULL, "DMIC1 Power" }, 2931 { "DMIC L2", NULL, "DMIC CLK" }, 2932 { "DMIC L2", NULL, "DMIC2 Power" }, 2933 { "DMIC R2", NULL, "DMIC CLK" }, 2934 { "DMIC R2", NULL, "DMIC2 Power" }, 2935 2936 { "Stereo1 DMIC L Mux", "DMIC1", "DMIC L1" }, 2937 { "Stereo1 DMIC L Mux", "DMIC2", "DMIC L2" }, 2938 2939 { "Stereo1 DMIC R Mux", "DMIC1", "DMIC R1" }, 2940 { "Stereo1 DMIC R Mux", "DMIC2", "DMIC R2" }, 2941 2942 { "Mono DMIC L Mux", "DMIC1 L", "DMIC L1" }, 2943 { "Mono DMIC L Mux", "DMIC2 L", "DMIC L2" }, 2944 2945 { "Mono DMIC R Mux", "DMIC1 R", "DMIC R1" }, 2946 { "Mono DMIC R Mux", "DMIC2 R", "DMIC R2" }, 2947 2948 { "Stereo1 ADC L Mux", "ADC1", "ADC1 L" }, 2949 { "Stereo1 ADC L Mux", "ADC2", "ADC2 L" }, 2950 { "Stereo1 ADC R Mux", "ADC1", "ADC1 R" }, 2951 { "Stereo1 ADC R Mux", "ADC2", "ADC2 R" }, 2952 2953 { "Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux" }, 2954 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" }, 2955 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux" }, 2956 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" }, 2957 2958 { "Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux" }, 2959 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" }, 2960 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux" }, 2961 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" }, 2962 2963 { "Mono ADC L Mux", "ADC1 L", "ADC1 L" }, 2964 { "Mono ADC L Mux", "ADC1 R", "ADC1 R" }, 2965 { "Mono ADC L Mux", "ADC2 L", "ADC2 L" }, 2966 { "Mono ADC L Mux", "ADC2 R", "ADC2 R" }, 2967 2968 { "Mono ADC R Mux", "ADC1 L", "ADC1 L" }, 2969 { "Mono ADC R Mux", "ADC1 R", "ADC1 R" }, 2970 { "Mono ADC R Mux", "ADC2 L", "ADC2 L" }, 2971 { "Mono ADC R Mux", "ADC2 R", "ADC2 R" }, 2972 2973 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" }, 2974 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2975 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2976 { "Mono ADC L1 Mux", "ADC", "Mono ADC L Mux" }, 2977 2978 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2979 { "Mono ADC R1 Mux", "ADC", "Mono ADC R Mux" }, 2980 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" }, 2981 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2982 2983 { "Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" }, 2984 { "Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" }, 2985 { "Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter" }, 2986 2987 { "Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" }, 2988 { "Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" }, 2989 { "Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter" }, 2990 2991 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" }, 2992 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" }, 2993 { "Mono ADC MIXL", NULL, "ADC Mono Left Filter" }, 2994 2995 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" }, 2996 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" }, 2997 { "Mono ADC MIXR", NULL, "ADC Mono Right Filter" }, 2998 2999 { "Stereo1 ADC Volume L", NULL, "Stereo1 ADC MIXL" }, 3000 { "Stereo1 ADC Volume R", NULL, "Stereo1 ADC MIXR" }, 3001 3002 { "IF_ADC1", NULL, "Stereo1 ADC Volume L" }, 3003 { "IF_ADC1", NULL, "Stereo1 ADC Volume R" }, 3004 { "IF_ADC2", NULL, "Mono ADC MIXL" }, 3005 { "IF_ADC2", NULL, "Mono ADC MIXR" }, 3006 3007 { "TDM AD1:AD2:DAC", NULL, "IF_ADC1" }, 3008 { "TDM AD1:AD2:DAC", NULL, "IF_ADC2" }, 3009 { "TDM AD1:AD2:DAC", NULL, "DAC_REF" }, 3010 { "TDM AD2:DAC", NULL, "IF_ADC2" }, 3011 { "TDM AD2:DAC", NULL, "DAC_REF" }, 3012 { "TDM Data Mux", "AD1:AD2:DAC:NUL", "TDM AD1:AD2:DAC" }, 3013 { "TDM Data Mux", "AD1:AD2:NUL:DAC", "TDM AD1:AD2:DAC" }, 3014 { "TDM Data Mux", "AD1:DAC:AD2:NUL", "TDM AD1:AD2:DAC" }, 3015 { "TDM Data Mux", "AD1:DAC:NUL:AD2", "TDM AD1:AD2:DAC" }, 3016 { "TDM Data Mux", "AD1:NUL:DAC:AD2", "TDM AD1:AD2:DAC" }, 3017 { "TDM Data Mux", "AD1:NUL:AD2:DAC", "TDM AD1:AD2:DAC" }, 3018 { "TDM Data Mux", "AD2:AD1:DAC:NUL", "TDM AD1:AD2:DAC" }, 3019 { "TDM Data Mux", "AD2:AD1:NUL:DAC", "TDM AD1:AD2:DAC" }, 3020 { "TDM Data Mux", "AD2:DAC:AD1:NUL", "TDM AD1:AD2:DAC" }, 3021 { "TDM Data Mux", "AD2:DAC:NUL:AD1", "TDM AD1:AD2:DAC" }, 3022 { "TDM Data Mux", "AD2:NUL:DAC:AD1", "TDM AD1:AD2:DAC" }, 3023 { "TDM Data Mux", "AD1:NUL:AD1:DAC", "TDM AD1:AD2:DAC" }, 3024 { "TDM Data Mux", "DAC:AD1:AD2:NUL", "TDM AD1:AD2:DAC" }, 3025 { "TDM Data Mux", "DAC:AD1:NUL:AD2", "TDM AD1:AD2:DAC" }, 3026 { "TDM Data Mux", "DAC:AD2:AD1:NUL", "TDM AD1:AD2:DAC" }, 3027 { "TDM Data Mux", "DAC:AD2:NUL:AD1", "TDM AD1:AD2:DAC" }, 3028 { "TDM Data Mux", "DAC:NUL:DAC:AD2", "TDM AD2:DAC" }, 3029 { "TDM Data Mux", "DAC:NUL:AD2:DAC", "TDM AD2:DAC" }, 3030 { "TDM Data Mux", "NUL:AD1:AD2:DAC", "TDM AD1:AD2:DAC" }, 3031 { "TDM Data Mux", "NUL:AD1:DAC:AD2", "TDM AD1:AD2:DAC" }, 3032 { "TDM Data Mux", "NUL:AD2:AD1:DAC", "TDM AD1:AD2:DAC" }, 3033 { "TDM Data Mux", "NUL:AD2:DAC:AD1", "TDM AD1:AD2:DAC" }, 3034 { "TDM Data Mux", "NUL:DAC:DAC:AD2", "TDM AD2:DAC" }, 3035 { "TDM Data Mux", "NUL:DAC:AD2:DAC", "TDM AD2:DAC" }, 3036 { "IF1 01 ADC Swap Mux", "L/R", "TDM Data Mux" }, 3037 { "IF1 01 ADC Swap Mux", "R/L", "TDM Data Mux" }, 3038 { "IF1 01 ADC Swap Mux", "L/L", "TDM Data Mux" }, 3039 { "IF1 01 ADC Swap Mux", "R/R", "TDM Data Mux" }, 3040 { "IF1 23 ADC Swap Mux", "L/R", "TDM Data Mux" }, 3041 { "IF1 23 ADC Swap Mux", "R/L", "TDM Data Mux" }, 3042 { "IF1 23 ADC Swap Mux", "L/L", "TDM Data Mux" }, 3043 { "IF1 23 ADC Swap Mux", "R/R", "TDM Data Mux" }, 3044 { "IF1 45 ADC Swap Mux", "L/R", "TDM Data Mux" }, 3045 { "IF1 45 ADC Swap Mux", "R/L", "TDM Data Mux" }, 3046 { "IF1 45 ADC Swap Mux", "L/L", "TDM Data Mux" }, 3047 { "IF1 45 ADC Swap Mux", "R/R", "TDM Data Mux" }, 3048 { "IF1 67 ADC Swap Mux", "L/R", "TDM Data Mux" }, 3049 { "IF1 67 ADC Swap Mux", "R/L", "TDM Data Mux" }, 3050 { "IF1 67 ADC Swap Mux", "L/L", "TDM Data Mux" }, 3051 { "IF1 67 ADC Swap Mux", "R/R", "TDM Data Mux" }, 3052 { "IF1 ADC", NULL, "IF1 01 ADC Swap Mux" }, 3053 { "IF1 ADC", NULL, "IF1 23 ADC Swap Mux" }, 3054 { "IF1 ADC", NULL, "IF1 45 ADC Swap Mux" }, 3055 { "IF1 ADC", NULL, "IF1 67 ADC Swap Mux" }, 3056 { "IF1 ADC", NULL, "I2S1" }, 3057 3058 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" }, 3059 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" }, 3060 { "IF2 ADC Mux", "IF_ADC3", "IF_ADC3" }, 3061 { "IF2 ADC Mux", "DAC_REF", "DAC_REF" }, 3062 { "IF2 ADC", NULL, "IF2 ADC Mux"}, 3063 { "IF2 ADC", NULL, "I2S2" }, 3064 3065 { "IF3 ADC Mux", "IF_ADC1", "IF_ADC1" }, 3066 { "IF3 ADC Mux", "IF_ADC2", "IF_ADC2" }, 3067 { "IF3 ADC Mux", "Stereo2_ADC_L/R", "Stereo2 ADC LR" }, 3068 { "IF3 ADC Mux", "DAC_REF", "DAC_REF" }, 3069 { "IF3 ADC", NULL, "IF3 ADC Mux"}, 3070 { "IF3 ADC", NULL, "I2S3" }, 3071 3072 { "AIF1TX", NULL, "IF1 ADC" }, 3073 { "IF2 ADC Swap Mux", "L/R", "IF2 ADC" }, 3074 { "IF2 ADC Swap Mux", "R/L", "IF2 ADC" }, 3075 { "IF2 ADC Swap Mux", "L/L", "IF2 ADC" }, 3076 { "IF2 ADC Swap Mux", "R/R", "IF2 ADC" }, 3077 { "AIF2TX", NULL, "IF2 ADC Swap Mux" }, 3078 { "IF3 ADC Swap Mux", "L/R", "IF3 ADC" }, 3079 { "IF3 ADC Swap Mux", "R/L", "IF3 ADC" }, 3080 { "IF3 ADC Swap Mux", "L/L", "IF3 ADC" }, 3081 { "IF3 ADC Swap Mux", "R/R", "IF3 ADC" }, 3082 { "AIF3TX", NULL, "IF3 ADC Swap Mux" }, 3083 3084 { "IF1 DAC1", NULL, "AIF1RX" }, 3085 { "IF1 DAC2", NULL, "AIF1RX" }, 3086 { "IF2 DAC Swap Mux", "L/R", "AIF2RX" }, 3087 { "IF2 DAC Swap Mux", "R/L", "AIF2RX" }, 3088 { "IF2 DAC Swap Mux", "L/L", "AIF2RX" }, 3089 { "IF2 DAC Swap Mux", "R/R", "AIF2RX" }, 3090 { "IF2 DAC", NULL, "IF2 DAC Swap Mux" }, 3091 { "IF3 DAC Swap Mux", "L/R", "AIF3RX" }, 3092 { "IF3 DAC Swap Mux", "R/L", "AIF3RX" }, 3093 { "IF3 DAC Swap Mux", "L/L", "AIF3RX" }, 3094 { "IF3 DAC Swap Mux", "R/R", "AIF3RX" }, 3095 { "IF3 DAC", NULL, "IF3 DAC Swap Mux" }, 3096 3097 { "IF1 DAC1", NULL, "I2S1" }, 3098 { "IF1 DAC2", NULL, "I2S1" }, 3099 { "IF2 DAC", NULL, "I2S2" }, 3100 { "IF3 DAC", NULL, "I2S3" }, 3101 3102 { "IF1 DAC2 L", NULL, "IF1 DAC2" }, 3103 { "IF1 DAC2 R", NULL, "IF1 DAC2" }, 3104 { "IF1 DAC1 L", NULL, "IF1 DAC1" }, 3105 { "IF1 DAC1 R", NULL, "IF1 DAC1" }, 3106 { "IF2 DAC L", NULL, "IF2 DAC" }, 3107 { "IF2 DAC R", NULL, "IF2 DAC" }, 3108 { "IF3 DAC L", NULL, "IF3 DAC" }, 3109 { "IF3 DAC R", NULL, "IF3 DAC" }, 3110 3111 { "DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L" }, 3112 { "DAC L1 Mux", "IF2 DAC", "IF2 DAC L" }, 3113 { "DAC L1 Mux", "IF3 DAC", "IF3 DAC L" }, 3114 { "DAC L1 Mux", NULL, "DAC Stereo1 Filter" }, 3115 3116 { "DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R" }, 3117 { "DAC R1 Mux", "IF2 DAC", "IF2 DAC R" }, 3118 { "DAC R1 Mux", "IF3 DAC", "IF3 DAC R" }, 3119 { "DAC R1 Mux", NULL, "DAC Stereo1 Filter" }, 3120 3121 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC Volume L" }, 3122 { "DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux" }, 3123 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC Volume R" }, 3124 { "DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux" }, 3125 3126 { "DAC_REF", NULL, "DAC1 MIXL" }, 3127 { "DAC_REF", NULL, "DAC1 MIXR" }, 3128 3129 { "DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L" }, 3130 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" }, 3131 { "DAC L2 Mux", "IF3 DAC", "IF3 DAC L" }, 3132 { "DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL" }, 3133 { "DAC L2 Mux", NULL, "DAC Mono Left Filter" }, 3134 3135 { "DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R" }, 3136 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" }, 3137 { "DAC R2 Mux", "IF3 DAC", "IF3 DAC R" }, 3138 { "DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR" }, 3139 { "DAC R2 Mux", NULL, "DAC Mono Right Filter" }, 3140 3141 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 3142 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" }, 3143 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux" }, 3144 { "Stereo DAC MIXL", "DAC R2 Switch", "DAC R2 Mux" }, 3145 3146 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 3147 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" }, 3148 { "Stereo DAC MIXR", "DAC L2 Switch", "DAC L2 Mux" }, 3149 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux" }, 3150 3151 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 3152 { "Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" }, 3153 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux" }, 3154 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux" }, 3155 { "Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" }, 3156 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 3157 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux" }, 3158 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux" }, 3159 3160 { "DAC MIXL", "Stereo DAC Mixer", "Stereo DAC MIXL" }, 3161 { "DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL" }, 3162 { "DAC MIXR", "Stereo DAC Mixer", "Stereo DAC MIXR" }, 3163 { "DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR" }, 3164 3165 { "DAC L1 Source", NULL, "DAC L1 Power" }, 3166 { "DAC L1 Source", "DAC", "DAC1 MIXL" }, 3167 { "DAC L1 Source", "Stereo DAC Mixer", "Stereo DAC MIXL" }, 3168 { "DAC R1 Source", NULL, "DAC R1 Power" }, 3169 { "DAC R1 Source", "DAC", "DAC1 MIXR" }, 3170 { "DAC R1 Source", "Stereo DAC Mixer", "Stereo DAC MIXR" }, 3171 { "DAC L2 Source", "Stereo DAC Mixer", "Stereo DAC MIXL" }, 3172 { "DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL" }, 3173 { "DAC L2 Source", NULL, "DAC L2 Power" }, 3174 { "DAC R2 Source", "Stereo DAC Mixer", "Stereo DAC MIXR" }, 3175 { "DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR" }, 3176 { "DAC R2 Source", NULL, "DAC R2 Power" }, 3177 3178 { "DAC L1", NULL, "DAC L1 Source" }, 3179 { "DAC R1", NULL, "DAC R1 Source" }, 3180 { "DAC L2", NULL, "DAC L2 Source" }, 3181 { "DAC R2", NULL, "DAC R2 Source" }, 3182 3183 { "SPK MIXL", "DAC L2 Switch", "DAC L2" }, 3184 { "SPK MIXL", "BST1 Switch", "BST1" }, 3185 { "SPK MIXL", "INL Switch", "INL VOL" }, 3186 { "SPK MIXL", "INR Switch", "INR VOL" }, 3187 { "SPK MIXL", "BST3 Switch", "BST3" }, 3188 { "SPK MIXR", "DAC R2 Switch", "DAC R2" }, 3189 { "SPK MIXR", "BST4 Switch", "BST4" }, 3190 { "SPK MIXR", "INL Switch", "INL VOL" }, 3191 { "SPK MIXR", "INR Switch", "INR VOL" }, 3192 { "SPK MIXR", "BST3 Switch", "BST3" }, 3193 3194 { "MONOVOL MIX", "DAC L2 Switch", "DAC L2" }, 3195 { "MONOVOL MIX", "DAC R2 Switch", "DAC R2" }, 3196 { "MONOVOL MIX", "BST1 Switch", "BST1" }, 3197 { "MONOVOL MIX", "BST2 Switch", "BST2" }, 3198 { "MONOVOL MIX", "BST3 Switch", "BST3" }, 3199 3200 { "OUT MIXL", "DAC L2 Switch", "DAC L2" }, 3201 { "OUT MIXL", "INL Switch", "INL VOL" }, 3202 { "OUT MIXL", "BST1 Switch", "BST1" }, 3203 { "OUT MIXL", "BST2 Switch", "BST2" }, 3204 { "OUT MIXL", "BST3 Switch", "BST3" }, 3205 { "OUT MIXR", "DAC R2 Switch", "DAC R2" }, 3206 { "OUT MIXR", "INR Switch", "INR VOL" }, 3207 { "OUT MIXR", "BST2 Switch", "BST2" }, 3208 { "OUT MIXR", "BST3 Switch", "BST3" }, 3209 { "OUT MIXR", "BST4 Switch", "BST4" }, 3210 3211 { "SPKVOL L", "Switch", "SPK MIXL" }, 3212 { "SPKVOL R", "Switch", "SPK MIXR" }, 3213 { "SPO L MIX", "DAC L2 Switch", "DAC L2" }, 3214 { "SPO L MIX", "SPKVOL L Switch", "SPKVOL L" }, 3215 { "SPO R MIX", "DAC R2 Switch", "DAC R2" }, 3216 { "SPO R MIX", "SPKVOL R Switch", "SPKVOL R" }, 3217 { "SPK Amp", NULL, "SPO L MIX" }, 3218 { "SPK Amp", NULL, "SPO R MIX" }, 3219 { "SPK Amp", NULL, "SYS CLK DET" }, 3220 { "SPO Playback", "Switch", "SPK Amp" }, 3221 { "SPOL", NULL, "SPO Playback" }, 3222 { "SPOR", NULL, "SPO Playback" }, 3223 3224 { "MONOVOL", "Switch", "MONOVOL MIX" }, 3225 { "Mono MIX", "DAC L2 Switch", "DAC L2" }, 3226 { "Mono MIX", "MONOVOL Switch", "MONOVOL" }, 3227 { "Mono Amp", NULL, "Mono MIX" }, 3228 { "Mono Amp", NULL, "Mono Vref" }, 3229 { "Mono Amp", NULL, "SYS CLK DET" }, 3230 { "Mono Playback", "Switch", "Mono Amp" }, 3231 { "MONOOUT", NULL, "Mono Playback" }, 3232 3233 { "HP Amp", NULL, "DAC L1" }, 3234 { "HP Amp", NULL, "DAC R1" }, 3235 { "HP Amp", NULL, "Charge Pump" }, 3236 { "HP Amp", NULL, "SYS CLK DET" }, 3237 { "HPO L Playback", "Switch", "HP Amp"}, 3238 { "HPO R Playback", "Switch", "HP Amp"}, 3239 { "HPOL", NULL, "HPO L Playback" }, 3240 { "HPOR", NULL, "HPO R Playback" }, 3241 3242 { "OUTVOL L", "Switch", "OUT MIXL" }, 3243 { "OUTVOL R", "Switch", "OUT MIXR" }, 3244 { "LOUT L MIX", "DAC L2 Switch", "DAC L2" }, 3245 { "LOUT L MIX", "OUTVOL L Switch", "OUTVOL L" }, 3246 { "LOUT R MIX", "DAC R2 Switch", "DAC R2" }, 3247 { "LOUT R MIX", "OUTVOL R Switch", "OUTVOL R" }, 3248 { "LOUT Amp", NULL, "LOUT L MIX" }, 3249 { "LOUT Amp", NULL, "LOUT R MIX" }, 3250 { "LOUT Amp", NULL, "Charge Pump" }, 3251 { "LOUT Amp", NULL, "SYS CLK DET" }, 3252 { "LOUT L Playback", "Switch", "LOUT Amp" }, 3253 { "LOUT R Playback", "Switch", "LOUT Amp" }, 3254 { "LOUTL", NULL, "LOUT L Playback" }, 3255 { "LOUTR", NULL, "LOUT R Playback" }, 3256 3257 { "PDM L Mux", "Mono DAC", "Mono DAC MIXL" }, 3258 { "PDM L Mux", "Stereo DAC", "Stereo DAC MIXL" }, 3259 { "PDM L Mux", NULL, "PDM Power" }, 3260 { "PDM R Mux", "Mono DAC", "Mono DAC MIXR" }, 3261 { "PDM R Mux", "Stereo DAC", "Stereo DAC MIXR" }, 3262 { "PDM R Mux", NULL, "PDM Power" }, 3263 { "PDM L Playback", "Switch", "PDM L Mux" }, 3264 { "PDM R Playback", "Switch", "PDM R Mux" }, 3265 { "PDML", NULL, "PDM L Playback" }, 3266 { "PDMR", NULL, "PDM R Playback" }, 3267 3268 { "SPDIF Mux", "IF3_DAC", "IF3 DAC" }, 3269 { "SPDIF Mux", "IF2_DAC", "IF2 DAC" }, 3270 { "SPDIF Mux", "IF1_DAC2", "IF1 DAC2" }, 3271 { "SPDIF Mux", "IF1_DAC1", "IF1 DAC1" }, 3272 { "SPDIF", NULL, "SPDIF Mux" }, 3273}; 3274 3275static int rt5659_hw_params(struct snd_pcm_substream *substream, 3276 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 3277{ 3278 struct snd_soc_component *component = dai->component; 3279 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component); 3280 unsigned int val_len = 0, val_clk, mask_clk; 3281 int pre_div, frame_size; 3282 3283 rt5659->lrck[dai->id] = params_rate(params); 3284 pre_div = rl6231_get_clk_info(rt5659->sysclk, rt5659->lrck[dai->id]); 3285 if (pre_div < 0) { 3286 dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n", 3287 rt5659->lrck[dai->id], dai->id); 3288 return -EINVAL; 3289 } 3290 frame_size = snd_soc_params_to_frame_size(params); 3291 if (frame_size < 0) { 3292 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 3293 return -EINVAL; 3294 } 3295 3296 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 3297 rt5659->lrck[dai->id], pre_div, dai->id); 3298 3299 switch (params_width(params)) { 3300 case 16: 3301 break; 3302 case 20: 3303 val_len |= RT5659_I2S_DL_20; 3304 break; 3305 case 24: 3306 val_len |= RT5659_I2S_DL_24; 3307 break; 3308 case 8: 3309 val_len |= RT5659_I2S_DL_8; 3310 break; 3311 default: 3312 return -EINVAL; 3313 } 3314 3315 switch (dai->id) { 3316 case RT5659_AIF1: 3317 mask_clk = RT5659_I2S_PD1_MASK; 3318 val_clk = pre_div << RT5659_I2S_PD1_SFT; 3319 snd_soc_component_update_bits(component, RT5659_I2S1_SDP, 3320 RT5659_I2S_DL_MASK, val_len); 3321 break; 3322 case RT5659_AIF2: 3323 mask_clk = RT5659_I2S_PD2_MASK; 3324 val_clk = pre_div << RT5659_I2S_PD2_SFT; 3325 snd_soc_component_update_bits(component, RT5659_I2S2_SDP, 3326 RT5659_I2S_DL_MASK, val_len); 3327 break; 3328 case RT5659_AIF3: 3329 mask_clk = RT5659_I2S_PD3_MASK; 3330 val_clk = pre_div << RT5659_I2S_PD3_SFT; 3331 snd_soc_component_update_bits(component, RT5659_I2S3_SDP, 3332 RT5659_I2S_DL_MASK, val_len); 3333 break; 3334 default: 3335 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 3336 return -EINVAL; 3337 } 3338 3339 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1, mask_clk, val_clk); 3340 3341 switch (rt5659->lrck[dai->id]) { 3342 case 192000: 3343 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1, 3344 RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_32); 3345 break; 3346 case 96000: 3347 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1, 3348 RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_64); 3349 break; 3350 default: 3351 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1, 3352 RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_128); 3353 break; 3354 } 3355 3356 return 0; 3357} 3358 3359static int rt5659_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 3360{ 3361 struct snd_soc_component *component = dai->component; 3362 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component); 3363 unsigned int reg_val = 0; 3364 3365 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 3366 case SND_SOC_DAIFMT_CBM_CFM: 3367 rt5659->master[dai->id] = 1; 3368 break; 3369 case SND_SOC_DAIFMT_CBS_CFS: 3370 reg_val |= RT5659_I2S_MS_S; 3371 rt5659->master[dai->id] = 0; 3372 break; 3373 default: 3374 return -EINVAL; 3375 } 3376 3377 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 3378 case SND_SOC_DAIFMT_NB_NF: 3379 break; 3380 case SND_SOC_DAIFMT_IB_NF: 3381 reg_val |= RT5659_I2S_BP_INV; 3382 break; 3383 default: 3384 return -EINVAL; 3385 } 3386 3387 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 3388 case SND_SOC_DAIFMT_I2S: 3389 break; 3390 case SND_SOC_DAIFMT_LEFT_J: 3391 reg_val |= RT5659_I2S_DF_LEFT; 3392 break; 3393 case SND_SOC_DAIFMT_DSP_A: 3394 reg_val |= RT5659_I2S_DF_PCM_A; 3395 break; 3396 case SND_SOC_DAIFMT_DSP_B: 3397 reg_val |= RT5659_I2S_DF_PCM_B; 3398 break; 3399 default: 3400 return -EINVAL; 3401 } 3402 3403 switch (dai->id) { 3404 case RT5659_AIF1: 3405 snd_soc_component_update_bits(component, RT5659_I2S1_SDP, 3406 RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK | 3407 RT5659_I2S_DF_MASK, reg_val); 3408 break; 3409 case RT5659_AIF2: 3410 snd_soc_component_update_bits(component, RT5659_I2S2_SDP, 3411 RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK | 3412 RT5659_I2S_DF_MASK, reg_val); 3413 break; 3414 case RT5659_AIF3: 3415 snd_soc_component_update_bits(component, RT5659_I2S3_SDP, 3416 RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK | 3417 RT5659_I2S_DF_MASK, reg_val); 3418 break; 3419 default: 3420 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 3421 return -EINVAL; 3422 } 3423 return 0; 3424} 3425 3426static int rt5659_set_component_sysclk(struct snd_soc_component *component, int clk_id, 3427 int source, unsigned int freq, int dir) 3428{ 3429 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component); 3430 unsigned int reg_val = 0; 3431 int ret; 3432 3433 if (freq == rt5659->sysclk && clk_id == rt5659->sysclk_src) 3434 return 0; 3435 3436 switch (clk_id) { 3437 case RT5659_SCLK_S_MCLK: 3438 ret = clk_set_rate(rt5659->mclk, freq); 3439 if (ret) 3440 return ret; 3441 3442 reg_val |= RT5659_SCLK_SRC_MCLK; 3443 break; 3444 case RT5659_SCLK_S_PLL1: 3445 reg_val |= RT5659_SCLK_SRC_PLL1; 3446 break; 3447 case RT5659_SCLK_S_RCCLK: 3448 reg_val |= RT5659_SCLK_SRC_RCCLK; 3449 break; 3450 default: 3451 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 3452 return -EINVAL; 3453 } 3454 snd_soc_component_update_bits(component, RT5659_GLB_CLK, 3455 RT5659_SCLK_SRC_MASK, reg_val); 3456 rt5659->sysclk = freq; 3457 rt5659->sysclk_src = clk_id; 3458 3459 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 3460 freq, clk_id); 3461 3462 return 0; 3463} 3464 3465static int rt5659_set_component_pll(struct snd_soc_component *component, int pll_id, 3466 int source, unsigned int freq_in, 3467 unsigned int freq_out) 3468{ 3469 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component); 3470 struct rl6231_pll_code pll_code; 3471 int ret; 3472 3473 if (source == rt5659->pll_src && freq_in == rt5659->pll_in && 3474 freq_out == rt5659->pll_out) 3475 return 0; 3476 3477 if (!freq_in || !freq_out) { 3478 dev_dbg(component->dev, "PLL disabled\n"); 3479 3480 rt5659->pll_in = 0; 3481 rt5659->pll_out = 0; 3482 snd_soc_component_update_bits(component, RT5659_GLB_CLK, 3483 RT5659_SCLK_SRC_MASK, RT5659_SCLK_SRC_MCLK); 3484 return 0; 3485 } 3486 3487 switch (source) { 3488 case RT5659_PLL1_S_MCLK: 3489 snd_soc_component_update_bits(component, RT5659_GLB_CLK, 3490 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_MCLK); 3491 break; 3492 case RT5659_PLL1_S_BCLK1: 3493 snd_soc_component_update_bits(component, RT5659_GLB_CLK, 3494 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK1); 3495 break; 3496 case RT5659_PLL1_S_BCLK2: 3497 snd_soc_component_update_bits(component, RT5659_GLB_CLK, 3498 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK2); 3499 break; 3500 case RT5659_PLL1_S_BCLK3: 3501 snd_soc_component_update_bits(component, RT5659_GLB_CLK, 3502 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK3); 3503 break; 3504 default: 3505 dev_err(component->dev, "Unknown PLL source %d\n", source); 3506 return -EINVAL; 3507 } 3508 3509 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 3510 if (ret < 0) { 3511 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 3512 return ret; 3513 } 3514 3515 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 3516 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 3517 pll_code.n_code, pll_code.k_code); 3518 3519 snd_soc_component_write(component, RT5659_PLL_CTRL_1, 3520 pll_code.n_code << RT5659_PLL_N_SFT | pll_code.k_code); 3521 snd_soc_component_write(component, RT5659_PLL_CTRL_2, 3522 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5659_PLL_M_SFT) | 3523 (pll_code.m_bp << RT5659_PLL_M_BP_SFT)); 3524 3525 rt5659->pll_in = freq_in; 3526 rt5659->pll_out = freq_out; 3527 rt5659->pll_src = source; 3528 3529 return 0; 3530} 3531 3532static int rt5659_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 3533 unsigned int rx_mask, int slots, int slot_width) 3534{ 3535 struct snd_soc_component *component = dai->component; 3536 unsigned int val = 0; 3537 3538 if (rx_mask || tx_mask) 3539 val |= (1 << 15); 3540 3541 switch (slots) { 3542 case 4: 3543 val |= (1 << 10); 3544 val |= (1 << 8); 3545 break; 3546 case 6: 3547 val |= (2 << 10); 3548 val |= (2 << 8); 3549 break; 3550 case 8: 3551 val |= (3 << 10); 3552 val |= (3 << 8); 3553 break; 3554 case 2: 3555 break; 3556 default: 3557 return -EINVAL; 3558 } 3559 3560 switch (slot_width) { 3561 case 20: 3562 val |= (1 << 6); 3563 val |= (1 << 4); 3564 break; 3565 case 24: 3566 val |= (2 << 6); 3567 val |= (2 << 4); 3568 break; 3569 case 32: 3570 val |= (3 << 6); 3571 val |= (3 << 4); 3572 break; 3573 case 16: 3574 break; 3575 default: 3576 return -EINVAL; 3577 } 3578 3579 snd_soc_component_update_bits(component, RT5659_TDM_CTRL_1, 0x8ff0, val); 3580 3581 return 0; 3582} 3583 3584static int rt5659_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 3585{ 3586 struct snd_soc_component *component = dai->component; 3587 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component); 3588 3589 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio); 3590 3591 rt5659->bclk[dai->id] = ratio; 3592 3593 if (ratio == 64) { 3594 switch (dai->id) { 3595 case RT5659_AIF2: 3596 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1, 3597 RT5659_I2S_BCLK_MS2_MASK, 3598 RT5659_I2S_BCLK_MS2_64); 3599 break; 3600 case RT5659_AIF3: 3601 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1, 3602 RT5659_I2S_BCLK_MS3_MASK, 3603 RT5659_I2S_BCLK_MS3_64); 3604 break; 3605 } 3606 } 3607 3608 return 0; 3609} 3610 3611static int rt5659_set_bias_level(struct snd_soc_component *component, 3612 enum snd_soc_bias_level level) 3613{ 3614 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3615 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component); 3616 int ret; 3617 3618 switch (level) { 3619 case SND_SOC_BIAS_PREPARE: 3620 regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC, 3621 RT5659_DIG_GATE_CTRL, RT5659_DIG_GATE_CTRL); 3622 regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1, 3623 RT5659_PWR_LDO, RT5659_PWR_LDO); 3624 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, 3625 RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2, 3626 RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2); 3627 msleep(20); 3628 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, 3629 RT5659_PWR_FV1 | RT5659_PWR_FV2, 3630 RT5659_PWR_FV1 | RT5659_PWR_FV2); 3631 break; 3632 3633 case SND_SOC_BIAS_STANDBY: 3634 if (dapm->bias_level == SND_SOC_BIAS_OFF) { 3635 ret = clk_prepare_enable(rt5659->mclk); 3636 if (ret) { 3637 dev_err(component->dev, 3638 "failed to enable MCLK: %d\n", ret); 3639 return ret; 3640 } 3641 } 3642 break; 3643 3644 case SND_SOC_BIAS_OFF: 3645 regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1, 3646 RT5659_PWR_LDO, 0); 3647 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, 3648 RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2 3649 | RT5659_PWR_FV1 | RT5659_PWR_FV2, 3650 RT5659_PWR_MB | RT5659_PWR_VREF2); 3651 regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC, 3652 RT5659_DIG_GATE_CTRL, 0); 3653 clk_disable_unprepare(rt5659->mclk); 3654 break; 3655 3656 default: 3657 break; 3658 } 3659 3660 return 0; 3661} 3662 3663static int rt5659_probe(struct snd_soc_component *component) 3664{ 3665 struct snd_soc_dapm_context *dapm = 3666 snd_soc_component_get_dapm(component); 3667 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component); 3668 3669 rt5659->component = component; 3670 3671 switch (rt5659->pdata.jd_src) { 3672 case RT5659_JD_HDA_HEADER: 3673 break; 3674 3675 default: 3676 snd_soc_dapm_new_controls(dapm, 3677 rt5659_particular_dapm_widgets, 3678 ARRAY_SIZE(rt5659_particular_dapm_widgets)); 3679 break; 3680 } 3681 3682 return 0; 3683} 3684 3685static void rt5659_remove(struct snd_soc_component *component) 3686{ 3687 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component); 3688 3689 regmap_write(rt5659->regmap, RT5659_RESET, 0); 3690} 3691 3692#ifdef CONFIG_PM 3693static int rt5659_suspend(struct snd_soc_component *component) 3694{ 3695 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component); 3696 3697 regcache_cache_only(rt5659->regmap, true); 3698 regcache_mark_dirty(rt5659->regmap); 3699 return 0; 3700} 3701 3702static int rt5659_resume(struct snd_soc_component *component) 3703{ 3704 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component); 3705 3706 regcache_cache_only(rt5659->regmap, false); 3707 regcache_sync(rt5659->regmap); 3708 3709 return 0; 3710} 3711#else 3712#define rt5659_suspend NULL 3713#define rt5659_resume NULL 3714#endif 3715 3716#define RT5659_STEREO_RATES SNDRV_PCM_RATE_8000_192000 3717#define RT5659_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 3718 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 3719 3720static const struct snd_soc_dai_ops rt5659_aif_dai_ops = { 3721 .hw_params = rt5659_hw_params, 3722 .set_fmt = rt5659_set_dai_fmt, 3723 .set_tdm_slot = rt5659_set_tdm_slot, 3724 .set_bclk_ratio = rt5659_set_bclk_ratio, 3725}; 3726 3727static struct snd_soc_dai_driver rt5659_dai[] = { 3728 { 3729 .name = "rt5659-aif1", 3730 .id = RT5659_AIF1, 3731 .playback = { 3732 .stream_name = "AIF1 Playback", 3733 .channels_min = 1, 3734 .channels_max = 2, 3735 .rates = RT5659_STEREO_RATES, 3736 .formats = RT5659_FORMATS, 3737 }, 3738 .capture = { 3739 .stream_name = "AIF1 Capture", 3740 .channels_min = 1, 3741 .channels_max = 2, 3742 .rates = RT5659_STEREO_RATES, 3743 .formats = RT5659_FORMATS, 3744 }, 3745 .ops = &rt5659_aif_dai_ops, 3746 }, 3747 { 3748 .name = "rt5659-aif2", 3749 .id = RT5659_AIF2, 3750 .playback = { 3751 .stream_name = "AIF2 Playback", 3752 .channels_min = 1, 3753 .channels_max = 2, 3754 .rates = RT5659_STEREO_RATES, 3755 .formats = RT5659_FORMATS, 3756 }, 3757 .capture = { 3758 .stream_name = "AIF2 Capture", 3759 .channels_min = 1, 3760 .channels_max = 2, 3761 .rates = RT5659_STEREO_RATES, 3762 .formats = RT5659_FORMATS, 3763 }, 3764 .ops = &rt5659_aif_dai_ops, 3765 }, 3766 { 3767 .name = "rt5659-aif3", 3768 .id = RT5659_AIF3, 3769 .playback = { 3770 .stream_name = "AIF3 Playback", 3771 .channels_min = 1, 3772 .channels_max = 2, 3773 .rates = RT5659_STEREO_RATES, 3774 .formats = RT5659_FORMATS, 3775 }, 3776 .capture = { 3777 .stream_name = "AIF3 Capture", 3778 .channels_min = 1, 3779 .channels_max = 2, 3780 .rates = RT5659_STEREO_RATES, 3781 .formats = RT5659_FORMATS, 3782 }, 3783 .ops = &rt5659_aif_dai_ops, 3784 }, 3785}; 3786 3787static const struct snd_soc_component_driver soc_component_dev_rt5659 = { 3788 .probe = rt5659_probe, 3789 .remove = rt5659_remove, 3790 .suspend = rt5659_suspend, 3791 .resume = rt5659_resume, 3792 .set_bias_level = rt5659_set_bias_level, 3793 .controls = rt5659_snd_controls, 3794 .num_controls = ARRAY_SIZE(rt5659_snd_controls), 3795 .dapm_widgets = rt5659_dapm_widgets, 3796 .num_dapm_widgets = ARRAY_SIZE(rt5659_dapm_widgets), 3797 .dapm_routes = rt5659_dapm_routes, 3798 .num_dapm_routes = ARRAY_SIZE(rt5659_dapm_routes), 3799 .set_sysclk = rt5659_set_component_sysclk, 3800 .set_pll = rt5659_set_component_pll, 3801 .use_pmdown_time = 1, 3802 .endianness = 1, 3803}; 3804 3805 3806static const struct regmap_config rt5659_regmap = { 3807 .reg_bits = 16, 3808 .val_bits = 16, 3809 .max_register = 0x0400, 3810 .volatile_reg = rt5659_volatile_register, 3811 .readable_reg = rt5659_readable_register, 3812 .cache_type = REGCACHE_RBTREE, 3813 .reg_defaults = rt5659_reg, 3814 .num_reg_defaults = ARRAY_SIZE(rt5659_reg), 3815}; 3816 3817static const struct i2c_device_id rt5659_i2c_id[] = { 3818 { "rt5658", 0 }, 3819 { "rt5659", 0 }, 3820 { } 3821}; 3822MODULE_DEVICE_TABLE(i2c, rt5659_i2c_id); 3823 3824static int rt5659_parse_dt(struct rt5659_priv *rt5659, struct device *dev) 3825{ 3826 rt5659->pdata.in1_diff = device_property_read_bool(dev, 3827 "realtek,in1-differential"); 3828 rt5659->pdata.in3_diff = device_property_read_bool(dev, 3829 "realtek,in3-differential"); 3830 rt5659->pdata.in4_diff = device_property_read_bool(dev, 3831 "realtek,in4-differential"); 3832 3833 3834 device_property_read_u32(dev, "realtek,dmic1-data-pin", 3835 &rt5659->pdata.dmic1_data_pin); 3836 device_property_read_u32(dev, "realtek,dmic2-data-pin", 3837 &rt5659->pdata.dmic2_data_pin); 3838 device_property_read_u32(dev, "realtek,jd-src", 3839 &rt5659->pdata.jd_src); 3840 3841 return 0; 3842} 3843 3844static void rt5659_calibrate(struct rt5659_priv *rt5659) 3845{ 3846 int value, count; 3847 3848 /* Calibrate HPO Start */ 3849 /* Fine tune HP Performance */ 3850 regmap_write(rt5659->regmap, RT5659_BIAS_CUR_CTRL_8, 0xa502); 3851 regmap_write(rt5659->regmap, RT5659_CHOP_DAC, 0x3030); 3852 3853 regmap_write(rt5659->regmap, RT5659_PRE_DIV_1, 0xef00); 3854 regmap_write(rt5659->regmap, RT5659_PRE_DIV_2, 0xeffc); 3855 regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0280); 3856 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0001); 3857 regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x8000); 3858 3859 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xaa7e); 3860 msleep(60); 3861 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe7e); 3862 msleep(50); 3863 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0004); 3864 regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0400); 3865 msleep(50); 3866 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0080); 3867 usleep_range(10000, 10005); 3868 regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0009); 3869 msleep(50); 3870 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0f80); 3871 msleep(50); 3872 regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0e16); 3873 msleep(50); 3874 3875 /* Enalbe K ADC Power And Clock */ 3876 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0505); 3877 msleep(50); 3878 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0184); 3879 regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x3c05); 3880 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c1); 3881 3882 /* K Headphone */ 3883 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1); 3884 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x5100); 3885 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0014); 3886 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0xd100); 3887 msleep(60); 3888 3889 /* Manual K ADC Offset */ 3890 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1); 3891 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4900); 3892 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0016); 3893 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 3894 0x8000, 0x8000); 3895 3896 count = 0; 3897 while (true) { 3898 regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value); 3899 if (value & 0x8000) 3900 usleep_range(10000, 10005); 3901 else 3902 break; 3903 3904 if (count > 30) { 3905 dev_err(rt5659->component->dev, 3906 "HP Calibration 1 Failure\n"); 3907 return; 3908 } 3909 3910 count++; 3911 } 3912 3913 /* Manual K Internal Path Offset */ 3914 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1); 3915 regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x0000); 3916 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4500); 3917 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x001f); 3918 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 3919 0x8000, 0x8000); 3920 3921 count = 0; 3922 while (true) { 3923 regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value); 3924 if (value & 0x8000) 3925 usleep_range(10000, 10005); 3926 else 3927 break; 3928 3929 if (count > 85) { 3930 dev_err(rt5659->component->dev, 3931 "HP Calibration 2 Failure\n"); 3932 return; 3933 } 3934 3935 count++; 3936 } 3937 3938 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0000); 3939 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0); 3940 /* Calibrate HPO End */ 3941 3942 /* Calibrate SPO Start */ 3943 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021); 3944 regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0260); 3945 regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x3000); 3946 regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0xc000); 3947 regmap_write(rt5659->regmap, RT5659_A_DAC_MUX, 0x000c); 3948 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x8000); 3949 regmap_write(rt5659->regmap, RT5659_SPO_VOL, 0x0808); 3950 regmap_write(rt5659->regmap, RT5659_SPK_L_MIXER, 0x001e); 3951 regmap_write(rt5659->regmap, RT5659_SPK_R_MIXER, 0x001e); 3952 regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0803); 3953 regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0554); 3954 regmap_write(rt5659->regmap, RT5659_SPO_AMP_GAIN, 0x1103); 3955 3956 /* Enalbe K ADC Power And Clock */ 3957 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0909); 3958 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x0001, 3959 0x0001); 3960 3961 /* Start Calibration */ 3962 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0000); 3963 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x0021); 3964 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1, 0x3e80); 3965 regmap_update_bits(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1, 3966 0x8000, 0x8000); 3967 3968 count = 0; 3969 while (true) { 3970 regmap_read(rt5659->regmap, 3971 RT5659_SPK_DC_CAILB_CTRL_1, &value); 3972 if (value & 0x8000) 3973 usleep_range(10000, 10005); 3974 else 3975 break; 3976 3977 if (count > 10) { 3978 dev_err(rt5659->component->dev, 3979 "SPK Calibration Failure\n"); 3980 return; 3981 } 3982 3983 count++; 3984 } 3985 /* Calibrate SPO End */ 3986 3987 /* Calibrate MONO Start */ 3988 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0000); 3989 regmap_write(rt5659->regmap, RT5659_MONOMIX_IN_GAIN, 0x021f); 3990 regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0x480a); 3991 /* MONO NG2 GAIN 5dB */ 3992 regmap_write(rt5659->regmap, RT5659_MONO_GAIN, 0x0003); 3993 regmap_write(rt5659->regmap, RT5659_MONO_NG2_CTRL_5, 0x0009); 3994 3995 /* Start Calibration */ 3996 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x000f); 3997 regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e00); 3998 regmap_update_bits(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 3999 0x8000, 0x8000); 4000 4001 count = 0; 4002 while (true) { 4003 regmap_read(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 4004 &value); 4005 if (value & 0x8000) 4006 usleep_range(10000, 10005); 4007 else 4008 break; 4009 4010 if (count > 35) { 4011 dev_err(rt5659->component->dev, 4012 "Mono Calibration Failure\n"); 4013 return; 4014 } 4015 4016 count++; 4017 } 4018 4019 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0003); 4020 /* Calibrate MONO End */ 4021 4022 /* Power Off */ 4023 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0808); 4024 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0000); 4025 regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x2005); 4026 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0); 4027 regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0000); 4028 regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0011); 4029 regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0150); 4030 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe3e); 4031 regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0xc80a); 4032 regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e04); 4033 regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x0000); 4034 regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0x0000); 4035 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0000); 4036 regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0000); 4037 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0x003e); 4038 regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0060); 4039 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021); 4040 regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x0000); 4041 regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0080); 4042 regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x8080); 4043 regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0c16); 4044} 4045 4046static void rt5659_intel_hd_header_probe_setup(struct rt5659_priv *rt5659) 4047{ 4048 int value; 4049 4050 regmap_read(rt5659->regmap, RT5659_GPIO_STA, &value); 4051 if (!(value & 0x8)) { 4052 rt5659->hda_hp_plugged = true; 4053 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1, 4054 0x10, 0x0); 4055 } else { 4056 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1, 4057 0x10, 0x10); 4058 } 4059 4060 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, 4061 RT5659_PWR_VREF2 | RT5659_PWR_MB, 4062 RT5659_PWR_VREF2 | RT5659_PWR_MB); 4063 msleep(20); 4064 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, 4065 RT5659_PWR_FV2, RT5659_PWR_FV2); 4066 4067 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_3, RT5659_PWR_LDO2, 4068 RT5659_PWR_LDO2); 4069 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_2, RT5659_PWR_MB1, 4070 RT5659_PWR_MB1); 4071 regmap_update_bits(rt5659->regmap, RT5659_PWR_VOL, RT5659_PWR_MIC_DET, 4072 RT5659_PWR_MIC_DET); 4073 msleep(20); 4074 4075 regmap_update_bits(rt5659->regmap, RT5659_4BTN_IL_CMD_2, 4076 RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_EN); 4077 regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value); 4078 regmap_write(rt5659->regmap, RT5659_4BTN_IL_CMD_1, value); 4079 regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value); 4080 4081 if (value & 0x2000) { 4082 rt5659->hda_mic_plugged = true; 4083 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2, 4084 0x2, 0x2); 4085 } else { 4086 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2, 4087 0x2, 0x0); 4088 } 4089 4090 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2, 4091 RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_EN); 4092} 4093 4094static int rt5659_i2c_probe(struct i2c_client *i2c) 4095{ 4096 struct rt5659_platform_data *pdata = dev_get_platdata(&i2c->dev); 4097 struct rt5659_priv *rt5659; 4098 int ret; 4099 unsigned int val; 4100 4101 rt5659 = devm_kzalloc(&i2c->dev, sizeof(struct rt5659_priv), 4102 GFP_KERNEL); 4103 4104 if (rt5659 == NULL) 4105 return -ENOMEM; 4106 4107 i2c_set_clientdata(i2c, rt5659); 4108 4109 if (pdata) 4110 rt5659->pdata = *pdata; 4111 else 4112 rt5659_parse_dt(rt5659, &i2c->dev); 4113 4114 rt5659->gpiod_ldo1_en = devm_gpiod_get_optional(&i2c->dev, "ldo1-en", 4115 GPIOD_OUT_HIGH); 4116 if (IS_ERR(rt5659->gpiod_ldo1_en)) 4117 dev_warn(&i2c->dev, "Request ldo1-en GPIO failed\n"); 4118 4119 rt5659->gpiod_reset = devm_gpiod_get_optional(&i2c->dev, "reset", 4120 GPIOD_OUT_HIGH); 4121 4122 /* Sleep for 300 ms miniumum */ 4123 msleep(300); 4124 4125 rt5659->regmap = devm_regmap_init_i2c(i2c, &rt5659_regmap); 4126 if (IS_ERR(rt5659->regmap)) { 4127 ret = PTR_ERR(rt5659->regmap); 4128 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 4129 ret); 4130 return ret; 4131 } 4132 4133 regmap_read(rt5659->regmap, RT5659_DEVICE_ID, &val); 4134 if (val != DEVICE_ID) { 4135 dev_err(&i2c->dev, 4136 "Device with ID register %x is not rt5659\n", val); 4137 return -ENODEV; 4138 } 4139 4140 regmap_write(rt5659->regmap, RT5659_RESET, 0); 4141 4142 /* Check if MCLK provided */ 4143 rt5659->mclk = devm_clk_get_optional(&i2c->dev, "mclk"); 4144 if (IS_ERR(rt5659->mclk)) 4145 return PTR_ERR(rt5659->mclk); 4146 4147 rt5659_calibrate(rt5659); 4148 4149 /* line in diff mode*/ 4150 if (rt5659->pdata.in1_diff) 4151 regmap_update_bits(rt5659->regmap, RT5659_IN1_IN2, 4152 RT5659_IN1_DF_MASK, RT5659_IN1_DF_MASK); 4153 if (rt5659->pdata.in3_diff) 4154 regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4, 4155 RT5659_IN3_DF_MASK, RT5659_IN3_DF_MASK); 4156 if (rt5659->pdata.in4_diff) 4157 regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4, 4158 RT5659_IN4_DF_MASK, RT5659_IN4_DF_MASK); 4159 4160 /* DMIC pin*/ 4161 if (rt5659->pdata.dmic1_data_pin != RT5659_DMIC1_NULL || 4162 rt5659->pdata.dmic2_data_pin != RT5659_DMIC2_NULL) { 4163 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, 4164 RT5659_GP2_PIN_MASK, RT5659_GP2_PIN_DMIC1_SCL); 4165 4166 switch (rt5659->pdata.dmic1_data_pin) { 4167 case RT5659_DMIC1_DATA_IN2N: 4168 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1, 4169 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_IN2N); 4170 break; 4171 4172 case RT5659_DMIC1_DATA_GPIO5: 4173 regmap_update_bits(rt5659->regmap, 4174 RT5659_GPIO_CTRL_3, 4175 RT5659_I2S2_PIN_MASK, 4176 RT5659_I2S2_PIN_GPIO); 4177 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1, 4178 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO5); 4179 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, 4180 RT5659_GP5_PIN_MASK, RT5659_GP5_PIN_DMIC1_SDA); 4181 break; 4182 4183 case RT5659_DMIC1_DATA_GPIO9: 4184 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1, 4185 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO9); 4186 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, 4187 RT5659_GP9_PIN_MASK, RT5659_GP9_PIN_DMIC1_SDA); 4188 break; 4189 4190 case RT5659_DMIC1_DATA_GPIO11: 4191 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1, 4192 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO11); 4193 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, 4194 RT5659_GP11_PIN_MASK, 4195 RT5659_GP11_PIN_DMIC1_SDA); 4196 break; 4197 4198 default: 4199 dev_dbg(&i2c->dev, "no DMIC1\n"); 4200 break; 4201 } 4202 4203 switch (rt5659->pdata.dmic2_data_pin) { 4204 case RT5659_DMIC2_DATA_IN2P: 4205 regmap_update_bits(rt5659->regmap, 4206 RT5659_DMIC_CTRL_1, 4207 RT5659_DMIC_2_DP_MASK, 4208 RT5659_DMIC_2_DP_IN2P); 4209 break; 4210 4211 case RT5659_DMIC2_DATA_GPIO6: 4212 regmap_update_bits(rt5659->regmap, 4213 RT5659_DMIC_CTRL_1, 4214 RT5659_DMIC_2_DP_MASK, 4215 RT5659_DMIC_2_DP_GPIO6); 4216 regmap_update_bits(rt5659->regmap, 4217 RT5659_GPIO_CTRL_1, 4218 RT5659_GP6_PIN_MASK, 4219 RT5659_GP6_PIN_DMIC2_SDA); 4220 break; 4221 4222 case RT5659_DMIC2_DATA_GPIO10: 4223 regmap_update_bits(rt5659->regmap, 4224 RT5659_DMIC_CTRL_1, 4225 RT5659_DMIC_2_DP_MASK, 4226 RT5659_DMIC_2_DP_GPIO10); 4227 regmap_update_bits(rt5659->regmap, 4228 RT5659_GPIO_CTRL_1, 4229 RT5659_GP10_PIN_MASK, 4230 RT5659_GP10_PIN_DMIC2_SDA); 4231 break; 4232 4233 case RT5659_DMIC2_DATA_GPIO12: 4234 regmap_update_bits(rt5659->regmap, 4235 RT5659_DMIC_CTRL_1, 4236 RT5659_DMIC_2_DP_MASK, 4237 RT5659_DMIC_2_DP_GPIO12); 4238 regmap_update_bits(rt5659->regmap, 4239 RT5659_GPIO_CTRL_1, 4240 RT5659_GP12_PIN_MASK, 4241 RT5659_GP12_PIN_DMIC2_SDA); 4242 break; 4243 4244 default: 4245 dev_dbg(&i2c->dev, "no DMIC2\n"); 4246 break; 4247 4248 } 4249 } else { 4250 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, 4251 RT5659_GP2_PIN_MASK | RT5659_GP5_PIN_MASK | 4252 RT5659_GP9_PIN_MASK | RT5659_GP11_PIN_MASK | 4253 RT5659_GP6_PIN_MASK | RT5659_GP10_PIN_MASK | 4254 RT5659_GP12_PIN_MASK, 4255 RT5659_GP2_PIN_GPIO2 | RT5659_GP5_PIN_GPIO5 | 4256 RT5659_GP9_PIN_GPIO9 | RT5659_GP11_PIN_GPIO11 | 4257 RT5659_GP6_PIN_GPIO6 | RT5659_GP10_PIN_GPIO10 | 4258 RT5659_GP12_PIN_GPIO12); 4259 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1, 4260 RT5659_DMIC_1_DP_MASK | RT5659_DMIC_2_DP_MASK, 4261 RT5659_DMIC_1_DP_IN2N | RT5659_DMIC_2_DP_IN2P); 4262 } 4263 4264 switch (rt5659->pdata.jd_src) { 4265 case RT5659_JD3: 4266 regmap_write(rt5659->regmap, RT5659_EJD_CTRL_1, 0xa880); 4267 regmap_write(rt5659->regmap, RT5659_RC_CLK_CTRL, 0x9000); 4268 regmap_write(rt5659->regmap, RT5659_GPIO_CTRL_1, 0xc800); 4269 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, 4270 RT5659_PWR_MB, RT5659_PWR_MB); 4271 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_2, 0x0001); 4272 regmap_write(rt5659->regmap, RT5659_IRQ_CTRL_2, 0x0040); 4273 INIT_DELAYED_WORK(&rt5659->jack_detect_work, 4274 rt5659_jack_detect_work); 4275 break; 4276 case RT5659_JD_HDA_HEADER: 4277 regmap_write(rt5659->regmap, RT5659_GPIO_CTRL_3, 0x8000); 4278 regmap_write(rt5659->regmap, RT5659_RC_CLK_CTRL, 0x0900); 4279 regmap_write(rt5659->regmap, RT5659_EJD_CTRL_1, 0x70c0); 4280 regmap_write(rt5659->regmap, RT5659_JD_CTRL_1, 0x2000); 4281 regmap_write(rt5659->regmap, RT5659_IRQ_CTRL_1, 0x0040); 4282 INIT_DELAYED_WORK(&rt5659->jack_detect_work, 4283 rt5659_jack_detect_intel_hd_header); 4284 rt5659_intel_hd_header_probe_setup(rt5659); 4285 break; 4286 default: 4287 break; 4288 } 4289 4290 if (i2c->irq) { 4291 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 4292 rt5659_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 4293 | IRQF_ONESHOT, "rt5659", rt5659); 4294 if (ret) 4295 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret); 4296 4297 /* Enable IRQ output for GPIO1 pin any way */ 4298 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, 4299 RT5659_GP1_PIN_MASK, RT5659_GP1_PIN_IRQ); 4300 } 4301 4302 return devm_snd_soc_register_component(&i2c->dev, 4303 &soc_component_dev_rt5659, 4304 rt5659_dai, ARRAY_SIZE(rt5659_dai)); 4305} 4306 4307static void rt5659_i2c_shutdown(struct i2c_client *client) 4308{ 4309 struct rt5659_priv *rt5659 = i2c_get_clientdata(client); 4310 4311 regmap_write(rt5659->regmap, RT5659_RESET, 0); 4312} 4313 4314#ifdef CONFIG_OF 4315static const struct of_device_id rt5659_of_match[] = { 4316 { .compatible = "realtek,rt5658", }, 4317 { .compatible = "realtek,rt5659", }, 4318 { }, 4319}; 4320MODULE_DEVICE_TABLE(of, rt5659_of_match); 4321#endif 4322 4323#ifdef CONFIG_ACPI 4324static const struct acpi_device_id rt5659_acpi_match[] = { 4325 { "10EC5658", 0, }, 4326 { "10EC5659", 0, }, 4327 { }, 4328}; 4329MODULE_DEVICE_TABLE(acpi, rt5659_acpi_match); 4330#endif 4331 4332static struct i2c_driver rt5659_i2c_driver = { 4333 .driver = { 4334 .name = "rt5659", 4335 .of_match_table = of_match_ptr(rt5659_of_match), 4336 .acpi_match_table = ACPI_PTR(rt5659_acpi_match), 4337 }, 4338 .probe = rt5659_i2c_probe, 4339 .shutdown = rt5659_i2c_shutdown, 4340 .id_table = rt5659_i2c_id, 4341}; 4342module_i2c_driver(rt5659_i2c_driver); 4343 4344MODULE_DESCRIPTION("ASoC RT5659 driver"); 4345MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 4346MODULE_LICENSE("GPL v2"); 4347