Searched refs:lanes (Results 1 - 25 of 277) sorted by path

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/linux-master/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi_common.c18 prop = of_find_property(ep, "lanes", &len);
20 u32 lanes[8]; local
22 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) {
23 dev_err(&pdev->dev, "bad number of lanes\n");
27 r = of_property_read_u32_array(ep, "lanes", lanes,
28 ARRAY_SIZE(lanes));
34 r = hdmi_phy_parse_lanes(phy, lanes);
/linux-master/drivers/gpu/drm/rockchip/
H A Dcdn-dp-reg.h460 int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip);
/linux-master/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c308 void __iomem *sw_regs, u32 lanes,
316 for (i = 0; i < lanes; i++) {
307 netcp_xgbe_check_link_status(void __iomem *serdes_regs, void __iomem *sw_regs, u32 lanes, u32 *current_state, u32 *lane_down) argument
/linux-master/drivers/staging/media/omap4iss/
H A Diss_csiphy.c21 * csiphy_lanes_config - Configuration of CSIPHY lanes.
36 reg |= (phy->lanes.data[i].pol ?
38 reg |= (phy->lanes.data[i].pos <<
44 reg |= phy->lanes.clk.pol ? CSI2_COMPLEXIO_CFG_CLOCK_POL : 0;
45 reg |= phy->lanes.clk.pos << CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT;
123 struct iss_csiphy_lanes_cfg *lanes; local
128 lanes = &subdevs->bus.csi2.lanecfg;
150 /* Enable all lanes for now */
161 /* Enable all lanes for now */
173 /* Clock and data lanes verificatio
[all...]
H A Diss_csiphy.h37 struct iss_csiphy_lanes_cfg lanes; member in struct:iss_csiphy
/linux-master/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi_common.c18 prop = of_find_property(ep, "lanes", &len);
20 u32 lanes[8]; local
22 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) {
23 dev_err(&pdev->dev, "bad number of lanes\n");
27 r = of_property_read_u32_array(ep, "lanes", lanes,
28 ARRAY_SIZE(lanes));
34 r = hdmi_phy_parse_lanes(phy, lanes);
/linux-master/arch/arm/crypto/
H A Dpoly1305-armv4.pl530 vdup.32 $R0,r2 @ r^1 in both lanes
/linux-master/arch/arm/mach-omap2/
H A Ddisplay.c73 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) argument
103 reg |= (lanes << enable_shift) & enable_mask;
104 reg |= (lanes << pipd_shift) & pipd_mask;
/linux-master/arch/x86/crypto/
H A Dsha256-avx-asm.S47 # This code schedules 1 block at a time, with 4 lanes per block
H A Dsha256-avx2-asm.S48 # This code schedules 2 blocks at a time, with 4 lanes per block
H A Dsha512-avx2-asm.S49 # This code schedules 1 blocks at a time, with 4 lanes per block
232 # Move to appropriate lanes for calculating w[16] and w[17]
234 # Move to appropriate lanes for calculating w[18] and w[19]
237 # Calculate w[16] and w[17] in both 128 bit lanes
239 # Calculate sigma1 for w[16] and w[17] on both 128 bit lanes
/linux-master/drivers/edac/
H A Dppc4xx_edac.c424 unsigned int lane, lanes; local
437 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) {
441 (lanes++ ? ", " : ""), lane);
452 n = snprintf(buffer, size, "%s; ", lanes ? "" : "None");
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu.h589 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
H A Dsi.c1540 static void si_set_pcie_lanes(struct amdgpu_device *adev, int lanes) argument
1547 switch (lanes) {
1567 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
/linux-master/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler_gfx10.asm562 // Write HWREGs with 16 VGPR lanes. TTMPs occupy space after this.
567 // Write SGPRs with 32 VGPR lanes. This works in wave32 and wave64 mode.
605 s_cmp_eq_u32 ttmp13, 0x20 //have 32 VGPR lanes filled?
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dprocesspptables.c701 ps->pcie.lanes = ((le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
705 ps->pcie.lanes = 0;
H A Dsmu7_hwmgr.c3626 power_state->pcie.lanes = 0;
/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpower_state.h91 unsigned int lanes; member in struct:PP_StatePcieBlock
/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Damdgpu_smu.h135 unsigned int lanes; member in struct:smu_state_pcie_block
/linux-master/drivers/gpu/drm/bridge/adv7511/
H A Dadv7533.c32 static const u8 clock_div_by_lanes[] = { 6, 4, 3 }; /* 2, 3, 4 lanes */
43 clock_div_by_lanes[dsi->lanes - 2] << 3);
73 /* set number of dsi lanes */
74 regmap_write(adv->regmap_cec, 0x1c, dsi->lanes << 4);
157 dsi->lanes = adv->num_dsi_lanes;
173 of_property_read_u32(np, "adi,dsi-lanes", &num_lanes);
/linux-master/drivers/gpu/drm/bridge/analogix/
H A Danx7625.c2080 dsi->lanes = ctx->pdata.mipi_lanes;
/linux-master/drivers/gpu/drm/bridge/cadence/
H A Dcdns-dsi-core.c526 unsigned int lanes = output->dev->lanes; local
541 if (dsi_htotal % lanes)
542 adj_dsi_htotal += lanes - (dsi_htotal % lanes);
549 if (do_div(dlane_bps, lanes * dpi_htotal))
570 unsigned int nlanes = output->dev->lanes;
714 DPHY_D_RSTB(output->dev->lanes) | DPHY_C_RSTB,
730 for (i = 1; i < output->dev->lanes; i++)
747 for (i = 0; i < output->dev->lanes;
[all...]
H A Dcdns-mhdp8546-core.c504 dev_err(mhdp->dev, "invalid number of lanes: %u\n", nlanes);
900 phy_cfg.dp.lanes = mhdp->link.num_lanes;
1037 dev_dbg(mhdp->dev, "%s, %u lanes, %u Mbps, vs %s, pe %s\n",
1072 phy_cfg.dp.lanes = mhdp->link.num_lanes;
1193 phy_cfg.dp.lanes = mhdp->link.num_lanes;
1282 "Reducing lanes number during CR phase\n");
1300 "Reducing lanes number during EQ phase\n");
1595 unsigned int lanes, unsigned int rate)
1608 max_bw = lanes * rate;
2200 dev_err(mhdp->dev, "%s: Not enough BW for %s (%u lanes a
1593 cdns_mhdp_bandwidth_ok(struct cdns_mhdp_device *mhdp, const struct drm_display_mode *mode, unsigned int lanes, unsigned int rate) argument
[all...]
/linux-master/drivers/gpu/drm/bridge/
H A Dchipone-icn6211.c414 DSI_CTRL_UNKNOWN | DSI_CTRL_DSI_LANES(icn->dsi->lanes - 1));
521 * If the 'data-lanes' property does not exist in DT or is invalid,
522 * default to previously hard-coded behavior, which was 4 data lanes.
525 icn->dsi->lanes = 4;
527 icn->dsi->lanes = dsi_lanes;
/linux-master/drivers/gpu/drm/bridge/imx/
H A Dimx8qm-ldb.c73 phy_cfg->lanes = 4;

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