1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author: Chris Zhong <zyw@rock-chips.com> 5 */ 6 7#ifndef _CDN_DP_REG_H 8#define _CDN_DP_REG_H 9 10#include <linux/bitops.h> 11 12#define ADDR_IMEM 0x10000 13#define ADDR_DMEM 0x20000 14 15/* APB CFG addr */ 16#define APB_CTRL 0 17#define XT_INT_CTRL 0x04 18#define MAILBOX_FULL_ADDR 0x08 19#define MAILBOX_EMPTY_ADDR 0x0c 20#define MAILBOX0_WR_DATA 0x10 21#define MAILBOX0_RD_DATA 0x14 22#define KEEP_ALIVE 0x18 23#define VER_L 0x1c 24#define VER_H 0x20 25#define VER_LIB_L_ADDR 0x24 26#define VER_LIB_H_ADDR 0x28 27#define SW_DEBUG_L 0x2c 28#define SW_DEBUG_H 0x30 29#define MAILBOX_INT_MASK 0x34 30#define MAILBOX_INT_STATUS 0x38 31#define SW_CLK_L 0x3c 32#define SW_CLK_H 0x40 33#define SW_EVENTS0 0x44 34#define SW_EVENTS1 0x48 35#define SW_EVENTS2 0x4c 36#define SW_EVENTS3 0x50 37#define XT_OCD_CTRL 0x60 38#define APB_INT_MASK 0x6c 39#define APB_STATUS_MASK 0x70 40 41/* audio decoder addr */ 42#define AUDIO_SRC_CNTL 0x30000 43#define AUDIO_SRC_CNFG 0x30004 44#define COM_CH_STTS_BITS 0x30008 45#define STTS_BIT_CH(x) (0x3000c + ((x) << 2)) 46#define SPDIF_CTRL_ADDR 0x3004c 47#define SPDIF_CH1_CS_3100_ADDR 0x30050 48#define SPDIF_CH1_CS_6332_ADDR 0x30054 49#define SPDIF_CH1_CS_9564_ADDR 0x30058 50#define SPDIF_CH1_CS_12796_ADDR 0x3005c 51#define SPDIF_CH1_CS_159128_ADDR 0x30060 52#define SPDIF_CH1_CS_191160_ADDR 0x30064 53#define SPDIF_CH2_CS_3100_ADDR 0x30068 54#define SPDIF_CH2_CS_6332_ADDR 0x3006c 55#define SPDIF_CH2_CS_9564_ADDR 0x30070 56#define SPDIF_CH2_CS_12796_ADDR 0x30074 57#define SPDIF_CH2_CS_159128_ADDR 0x30078 58#define SPDIF_CH2_CS_191160_ADDR 0x3007c 59#define SMPL2PKT_CNTL 0x30080 60#define SMPL2PKT_CNFG 0x30084 61#define FIFO_CNTL 0x30088 62#define FIFO_STTS 0x3008c 63 64/* source pif addr */ 65#define SOURCE_PIF_WR_ADDR 0x30800 66#define SOURCE_PIF_WR_REQ 0x30804 67#define SOURCE_PIF_RD_ADDR 0x30808 68#define SOURCE_PIF_RD_REQ 0x3080c 69#define SOURCE_PIF_DATA_WR 0x30810 70#define SOURCE_PIF_DATA_RD 0x30814 71#define SOURCE_PIF_FIFO1_FLUSH 0x30818 72#define SOURCE_PIF_FIFO2_FLUSH 0x3081c 73#define SOURCE_PIF_STATUS 0x30820 74#define SOURCE_PIF_INTERRUPT_SOURCE 0x30824 75#define SOURCE_PIF_INTERRUPT_MASK 0x30828 76#define SOURCE_PIF_PKT_ALLOC_REG 0x3082c 77#define SOURCE_PIF_PKT_ALLOC_WR_EN 0x30830 78#define SOURCE_PIF_SW_RESET 0x30834 79 80/* bellow registers need access by mailbox */ 81/* source car addr */ 82#define SOURCE_HDTX_CAR 0x0900 83#define SOURCE_DPTX_CAR 0x0904 84#define SOURCE_PHY_CAR 0x0908 85#define SOURCE_CEC_CAR 0x090c 86#define SOURCE_CBUS_CAR 0x0910 87#define SOURCE_PKT_CAR 0x0918 88#define SOURCE_AIF_CAR 0x091c 89#define SOURCE_CIPHER_CAR 0x0920 90#define SOURCE_CRYPTO_CAR 0x0924 91 92/* clock meters addr */ 93#define CM_CTRL 0x0a00 94#define CM_I2S_CTRL 0x0a04 95#define CM_SPDIF_CTRL 0x0a08 96#define CM_VID_CTRL 0x0a0c 97#define CM_LANE_CTRL 0x0a10 98#define I2S_NM_STABLE 0x0a14 99#define I2S_NCTS_STABLE 0x0a18 100#define SPDIF_NM_STABLE 0x0a1c 101#define SPDIF_NCTS_STABLE 0x0a20 102#define NMVID_MEAS_STABLE 0x0a24 103#define I2S_MEAS 0x0a40 104#define SPDIF_MEAS 0x0a80 105#define NMVID_MEAS 0x0ac0 106 107/* source vif addr */ 108#define BND_HSYNC2VSYNC 0x0b00 109#define HSYNC2VSYNC_F1_L1 0x0b04 110#define HSYNC2VSYNC_F2_L1 0x0b08 111#define HSYNC2VSYNC_STATUS 0x0b0c 112#define HSYNC2VSYNC_POL_CTRL 0x0b10 113 114/* dptx phy addr */ 115#define DP_TX_PHY_CONFIG_REG 0x2000 116#define DP_TX_PHY_SW_RESET 0x2004 117#define DP_TX_PHY_SCRAMBLER_SEED 0x2008 118#define DP_TX_PHY_TRAINING_01_04 0x200c 119#define DP_TX_PHY_TRAINING_05_08 0x2010 120#define DP_TX_PHY_TRAINING_09_10 0x2014 121#define TEST_COR 0x23fc 122 123/* dptx hpd addr */ 124#define HPD_IRQ_DET_MIN_TIMER 0x2100 125#define HPD_IRQ_DET_MAX_TIMER 0x2104 126#define HPD_UNPLGED_DET_MIN_TIMER 0x2108 127#define HPD_STABLE_TIMER 0x210c 128#define HPD_FILTER_TIMER 0x2110 129#define HPD_EVENT_MASK 0x211c 130#define HPD_EVENT_DET 0x2120 131 132/* dpyx framer addr */ 133#define DP_FRAMER_GLOBAL_CONFIG 0x2200 134#define DP_SW_RESET 0x2204 135#define DP_FRAMER_TU 0x2208 136#define DP_FRAMER_PXL_REPR 0x220c 137#define DP_FRAMER_SP 0x2210 138#define AUDIO_PACK_CONTROL 0x2214 139#define DP_VC_TABLE(x) (0x2218 + ((x) << 2)) 140#define DP_VB_ID 0x2258 141#define DP_MTPH_LVP_CONTROL 0x225c 142#define DP_MTPH_SYMBOL_VALUES 0x2260 143#define DP_MTPH_ECF_CONTROL 0x2264 144#define DP_MTPH_ACT_CONTROL 0x2268 145#define DP_MTPH_STATUS 0x226c 146#define DP_INTERRUPT_SOURCE 0x2270 147#define DP_INTERRUPT_MASK 0x2274 148#define DP_FRONT_BACK_PORCH 0x2278 149#define DP_BYTE_COUNT 0x227c 150 151/* dptx stream addr */ 152#define MSA_HORIZONTAL_0 0x2280 153#define MSA_HORIZONTAL_1 0x2284 154#define MSA_VERTICAL_0 0x2288 155#define MSA_VERTICAL_1 0x228c 156#define MSA_MISC 0x2290 157#define STREAM_CONFIG 0x2294 158#define AUDIO_PACK_STATUS 0x2298 159#define VIF_STATUS 0x229c 160#define PCK_STUFF_STATUS_0 0x22a0 161#define PCK_STUFF_STATUS_1 0x22a4 162#define INFO_PACK_STATUS 0x22a8 163#define RATE_GOVERNOR_STATUS 0x22ac 164#define DP_HORIZONTAL 0x22b0 165#define DP_VERTICAL_0 0x22b4 166#define DP_VERTICAL_1 0x22b8 167#define DP_BLOCK_SDP 0x22bc 168 169/* dptx glbl addr */ 170#define DPTX_LANE_EN 0x2300 171#define DPTX_ENHNCD 0x2304 172#define DPTX_INT_MASK 0x2308 173#define DPTX_INT_STATUS 0x230c 174 175/* dp aux addr */ 176#define DP_AUX_HOST_CONTROL 0x2800 177#define DP_AUX_INTERRUPT_SOURCE 0x2804 178#define DP_AUX_INTERRUPT_MASK 0x2808 179#define DP_AUX_SWAP_INVERSION_CONTROL 0x280c 180#define DP_AUX_SEND_NACK_TRANSACTION 0x2810 181#define DP_AUX_CLEAR_RX 0x2814 182#define DP_AUX_CLEAR_TX 0x2818 183#define DP_AUX_TIMER_STOP 0x281c 184#define DP_AUX_TIMER_CLEAR 0x2820 185#define DP_AUX_RESET_SW 0x2824 186#define DP_AUX_DIVIDE_2M 0x2828 187#define DP_AUX_TX_PREACHARGE_LENGTH 0x282c 188#define DP_AUX_FREQUENCY_1M_MAX 0x2830 189#define DP_AUX_FREQUENCY_1M_MIN 0x2834 190#define DP_AUX_RX_PRE_MIN 0x2838 191#define DP_AUX_RX_PRE_MAX 0x283c 192#define DP_AUX_TIMER_PRESET 0x2840 193#define DP_AUX_NACK_FORMAT 0x2844 194#define DP_AUX_TX_DATA 0x2848 195#define DP_AUX_RX_DATA 0x284c 196#define DP_AUX_TX_STATUS 0x2850 197#define DP_AUX_RX_STATUS 0x2854 198#define DP_AUX_RX_CYCLE_COUNTER 0x2858 199#define DP_AUX_MAIN_STATES 0x285c 200#define DP_AUX_MAIN_TIMER 0x2860 201#define DP_AUX_AFE_OUT 0x2864 202 203/* crypto addr */ 204#define CRYPTO_HDCP_REVISION 0x5800 205#define HDCP_CRYPTO_CONFIG 0x5804 206#define CRYPTO_INTERRUPT_SOURCE 0x5808 207#define CRYPTO_INTERRUPT_MASK 0x580c 208#define CRYPTO22_CONFIG 0x5818 209#define CRYPTO22_STATUS 0x581c 210#define SHA_256_DATA_IN 0x583c 211#define SHA_256_DATA_OUT_(x) (0x5850 + ((x) << 2)) 212#define AES_32_KEY_(x) (0x5870 + ((x) << 2)) 213#define AES_32_DATA_IN 0x5880 214#define AES_32_DATA_OUT_(x) (0x5884 + ((x) << 2)) 215#define CRYPTO14_CONFIG 0x58a0 216#define CRYPTO14_STATUS 0x58a4 217#define CRYPTO14_PRNM_OUT 0x58a8 218#define CRYPTO14_KM_0 0x58ac 219#define CRYPTO14_KM_1 0x58b0 220#define CRYPTO14_AN_0 0x58b4 221#define CRYPTO14_AN_1 0x58b8 222#define CRYPTO14_YOUR_KSV_0 0x58bc 223#define CRYPTO14_YOUR_KSV_1 0x58c0 224#define CRYPTO14_MI_0 0x58c4 225#define CRYPTO14_MI_1 0x58c8 226#define CRYPTO14_TI_0 0x58cc 227#define CRYPTO14_KI_0 0x58d0 228#define CRYPTO14_KI_1 0x58d4 229#define CRYPTO14_BLOCKS_NUM 0x58d8 230#define CRYPTO14_KEY_MEM_DATA_0 0x58dc 231#define CRYPTO14_KEY_MEM_DATA_1 0x58e0 232#define CRYPTO14_SHA1_MSG_DATA 0x58e4 233#define CRYPTO14_SHA1_V_VALUE_(x) (0x58e8 + ((x) << 2)) 234#define TRNG_CTRL 0x58fc 235#define TRNG_DATA_RDY 0x5900 236#define TRNG_DATA 0x5904 237 238/* cipher addr */ 239#define HDCP_REVISION 0x60000 240#define INTERRUPT_SOURCE 0x60004 241#define INTERRUPT_MASK 0x60008 242#define HDCP_CIPHER_CONFIG 0x6000c 243#define AES_128_KEY_0 0x60010 244#define AES_128_KEY_1 0x60014 245#define AES_128_KEY_2 0x60018 246#define AES_128_KEY_3 0x6001c 247#define AES_128_RANDOM_0 0x60020 248#define AES_128_RANDOM_1 0x60024 249#define CIPHER14_KM_0 0x60028 250#define CIPHER14_KM_1 0x6002c 251#define CIPHER14_STATUS 0x60030 252#define CIPHER14_RI_PJ_STATUS 0x60034 253#define CIPHER_MODE 0x60038 254#define CIPHER14_AN_0 0x6003c 255#define CIPHER14_AN_1 0x60040 256#define CIPHER22_AUTH 0x60044 257#define CIPHER14_R0_DP_STATUS 0x60048 258#define CIPHER14_BOOTSTRAP 0x6004c 259 260#define DPTX_FRMR_DATA_CLK_RSTN_EN BIT(11) 261#define DPTX_FRMR_DATA_CLK_EN BIT(10) 262#define DPTX_PHY_DATA_RSTN_EN BIT(9) 263#define DPTX_PHY_DATA_CLK_EN BIT(8) 264#define DPTX_PHY_CHAR_RSTN_EN BIT(7) 265#define DPTX_PHY_CHAR_CLK_EN BIT(6) 266#define SOURCE_AUX_SYS_CLK_RSTN_EN BIT(5) 267#define SOURCE_AUX_SYS_CLK_EN BIT(4) 268#define DPTX_SYS_CLK_RSTN_EN BIT(3) 269#define DPTX_SYS_CLK_EN BIT(2) 270#define CFG_DPTX_VIF_CLK_RSTN_EN BIT(1) 271#define CFG_DPTX_VIF_CLK_EN BIT(0) 272 273#define SOURCE_PHY_RSTN_EN BIT(1) 274#define SOURCE_PHY_CLK_EN BIT(0) 275 276#define SOURCE_PKT_SYS_RSTN_EN BIT(3) 277#define SOURCE_PKT_SYS_CLK_EN BIT(2) 278#define SOURCE_PKT_DATA_RSTN_EN BIT(1) 279#define SOURCE_PKT_DATA_CLK_EN BIT(0) 280 281#define SPDIF_CDR_CLK_RSTN_EN BIT(5) 282#define SPDIF_CDR_CLK_EN BIT(4) 283#define SOURCE_AIF_SYS_RSTN_EN BIT(3) 284#define SOURCE_AIF_SYS_CLK_EN BIT(2) 285#define SOURCE_AIF_CLK_RSTN_EN BIT(1) 286#define SOURCE_AIF_CLK_EN BIT(0) 287 288#define SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN BIT(3) 289#define SOURCE_CIPHER_SYS_CLK_EN BIT(2) 290#define SOURCE_CIPHER_CHAR_CLK_RSTN_EN BIT(1) 291#define SOURCE_CIPHER_CHAR_CLK_EN BIT(0) 292 293#define SOURCE_CRYPTO_SYS_CLK_RSTN_EN BIT(1) 294#define SOURCE_CRYPTO_SYS_CLK_EN BIT(0) 295 296#define APB_IRAM_PATH BIT(2) 297#define APB_DRAM_PATH BIT(1) 298#define APB_XT_RESET BIT(0) 299 300#define MAILBOX_INT_MASK_BIT BIT(1) 301#define PIF_INT_MASK_BIT BIT(0) 302#define ALL_INT_MASK 3 303 304/* mailbox */ 305#define MB_OPCODE_ID 0 306#define MB_MODULE_ID 1 307#define MB_SIZE_MSB_ID 2 308#define MB_SIZE_LSB_ID 3 309#define MB_DATA_ID 4 310 311#define MB_MODULE_ID_DP_TX 0x01 312#define MB_MODULE_ID_HDCP_TX 0x07 313#define MB_MODULE_ID_HDCP_RX 0x08 314#define MB_MODULE_ID_HDCP_GENERAL 0x09 315#define MB_MODULE_ID_GENERAL 0x0a 316 317/* general opcode */ 318#define GENERAL_MAIN_CONTROL 0x01 319#define GENERAL_TEST_ECHO 0x02 320#define GENERAL_BUS_SETTINGS 0x03 321#define GENERAL_TEST_ACCESS 0x04 322 323#define DPTX_SET_POWER_MNG 0x00 324#define DPTX_SET_HOST_CAPABILITIES 0x01 325#define DPTX_GET_EDID 0x02 326#define DPTX_READ_DPCD 0x03 327#define DPTX_WRITE_DPCD 0x04 328#define DPTX_ENABLE_EVENT 0x05 329#define DPTX_WRITE_REGISTER 0x06 330#define DPTX_READ_REGISTER 0x07 331#define DPTX_WRITE_FIELD 0x08 332#define DPTX_TRAINING_CONTROL 0x09 333#define DPTX_READ_EVENT 0x0a 334#define DPTX_READ_LINK_STAT 0x0b 335#define DPTX_SET_VIDEO 0x0c 336#define DPTX_SET_AUDIO 0x0d 337#define DPTX_GET_LAST_AUX_STAUS 0x0e 338#define DPTX_SET_LINK_BREAK_POINT 0x0f 339#define DPTX_FORCE_LANES 0x10 340#define DPTX_HPD_STATE 0x11 341 342#define FW_STANDBY 0 343#define FW_ACTIVE 1 344 345#define DPTX_EVENT_ENABLE_HPD BIT(0) 346#define DPTX_EVENT_ENABLE_TRAINING BIT(1) 347 348#define LINK_TRAINING_NOT_ACTIVE 0 349#define LINK_TRAINING_RUN 1 350#define LINK_TRAINING_RESTART 2 351 352#define CONTROL_VIDEO_IDLE 0 353#define CONTROL_VIDEO_VALID 1 354 355#define TU_CNT_RST_EN BIT(15) 356#define VIF_BYPASS_INTERLACE BIT(13) 357#define INTERLACE_FMT_DET BIT(12) 358#define INTERLACE_DTCT_WIN 0x20 359 360#define DP_FRAMER_SP_INTERLACE_EN BIT(2) 361#define DP_FRAMER_SP_HSP BIT(1) 362#define DP_FRAMER_SP_VSP BIT(0) 363 364/* capability */ 365#define AUX_HOST_INVERT 3 366#define FAST_LT_SUPPORT 1 367#define FAST_LT_NOT_SUPPORT 0 368#define LANE_MAPPING_NORMAL 0x1b 369#define LANE_MAPPING_FLIPPED 0xe4 370#define ENHANCED 1 371#define SCRAMBLER_EN BIT(4) 372 373#define FULL_LT_STARTED BIT(0) 374#define FASE_LT_STARTED BIT(1) 375#define CLK_RECOVERY_FINISHED BIT(2) 376#define EQ_PHASE_FINISHED BIT(3) 377#define FASE_LT_START_FINISHED BIT(4) 378#define CLK_RECOVERY_FAILED BIT(5) 379#define EQ_PHASE_FAILED BIT(6) 380#define FASE_LT_FAILED BIT(7) 381 382#define DPTX_HPD_EVENT BIT(0) 383#define DPTX_TRAINING_EVENT BIT(1) 384#define HDCP_TX_STATUS_EVENT BIT(4) 385#define HDCP2_TX_IS_KM_STORED_EVENT BIT(5) 386#define HDCP2_TX_STORE_KM_EVENT BIT(6) 387#define HDCP_TX_IS_RECEIVER_ID_VALID_EVENT BIT(7) 388 389#define TU_SIZE 30 390#define CDN_DP_MAX_LINK_RATE DP_LINK_BW_5_4 391 392/* audio */ 393#define AUDIO_PACK_EN BIT(8) 394#define SAMPLING_FREQ(x) (((x) & 0xf) << 16) 395#define ORIGINAL_SAMP_FREQ(x) (((x) & 0xf) << 24) 396#define SYNC_WR_TO_CH_ZERO BIT(1) 397#define I2S_DEC_START BIT(1) 398#define AUDIO_SW_RST BIT(0) 399#define SMPL2PKT_EN BIT(1) 400#define MAX_NUM_CH(x) (((x) & 0x1f) - 1) 401#define NUM_OF_I2S_PORTS(x) ((((x) / 2 - 1) & 0x3) << 5) 402#define AUDIO_TYPE_LPCM (2 << 7) 403#define CFG_SUB_PCKT_NUM(x) ((((x) - 1) & 0x7) << 11) 404#define AUDIO_CH_NUM(x) ((((x) - 1) & 0x1f) << 2) 405#define TRANS_SMPL_WIDTH_16 0 406#define TRANS_SMPL_WIDTH_24 BIT(11) 407#define TRANS_SMPL_WIDTH_32 (2 << 11) 408#define I2S_DEC_PORT_EN(x) (((x) & 0xf) << 17) 409#define SPDIF_ENABLE BIT(21) 410#define SPDIF_AVG_SEL BIT(20) 411#define SPDIF_JITTER_BYPASS BIT(19) 412#define SPDIF_FIFO_MID_RANGE(x) (((x) & 0xff) << 11) 413#define SPDIF_JITTER_THRSH(x) (((x) & 0xff) << 3) 414#define SPDIF_JITTER_AVG_WIN(x) ((x) & 0x7) 415 416/* Reference cycles when using lane clock as reference */ 417#define LANE_REF_CYC 0x8000 418 419enum voltage_swing_level { 420 VOLTAGE_LEVEL_0, 421 VOLTAGE_LEVEL_1, 422 VOLTAGE_LEVEL_2, 423 VOLTAGE_LEVEL_3, 424}; 425 426enum pre_emphasis_level { 427 PRE_EMPHASIS_LEVEL_0, 428 PRE_EMPHASIS_LEVEL_1, 429 PRE_EMPHASIS_LEVEL_2, 430 PRE_EMPHASIS_LEVEL_3, 431}; 432 433enum pattern_set { 434 PTS1 = BIT(0), 435 PTS2 = BIT(1), 436 PTS3 = BIT(2), 437 PTS4 = BIT(3), 438 DP_NONE = BIT(4) 439}; 440 441enum vic_color_depth { 442 BCS_6 = 0x1, 443 BCS_8 = 0x2, 444 BCS_10 = 0x4, 445 BCS_12 = 0x8, 446 BCS_16 = 0x10, 447}; 448 449enum vic_bt_type { 450 BT_601 = 0x0, 451 BT_709 = 0x1, 452}; 453 454void cdn_dp_clock_reset(struct cdn_dp_device *dp); 455 456void cdn_dp_set_fw_clk(struct cdn_dp_device *dp, unsigned long clk); 457int cdn_dp_load_firmware(struct cdn_dp_device *dp, const u32 *i_mem, 458 u32 i_size, const u32 *d_mem, u32 d_size); 459int cdn_dp_set_firmware_active(struct cdn_dp_device *dp, bool enable); 460int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip); 461int cdn_dp_event_config(struct cdn_dp_device *dp); 462u32 cdn_dp_get_event(struct cdn_dp_device *dp); 463int cdn_dp_get_hpd_status(struct cdn_dp_device *dp); 464int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value); 465int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len); 466int cdn_dp_get_edid_block(void *dp, u8 *edid, 467 unsigned int block, size_t length); 468int cdn_dp_train_link(struct cdn_dp_device *dp); 469int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active); 470int cdn_dp_config_video(struct cdn_dp_device *dp); 471int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio); 472int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable); 473int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio); 474#endif /* _CDN_DP_REG_H */ 475