/linux-master/arch/sh/kernel/cpu/sh3/ |
H A D | swsusp.S | 15 #define k2 r2 define 66 lds k2, pr
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H A D | entry.S | 69 #define k2 r2 define 83 * k2 scratch (Exception code) 193 lds k2, pr ! restore pr 210 ! k2 returns original pr 240 mov.l @r15+, k2 ! original PR 253 lds k2, pr ! restore pr 256 mov k3, k2 ! original SR value 260 and k1, k2 ! Mask original SR value 270 6: or k0, k2 ! Set the IMASK-bits 271 ldc k2, ss [all...] |
/linux-master/include/linux/ |
H A D | btree-128.h | 22 static inline void *btree_lookup128(struct btree_head128 *head, u64 k1, u64 k2) argument 24 u64 key[2] = {k1, k2}; 29 u64 *k1, u64 *k2) 31 u64 key[2] = {*k1, *k2}; 37 *k2 = key[1]; 41 static inline int btree_insert128(struct btree_head128 *head, u64 k1, u64 k2, argument 44 u64 key[2] = {k1, k2}; 49 static inline int btree_update128(struct btree_head128 *head, u64 k1, u64 k2, argument 52 u64 key[2] = {k1, k2}; 57 static inline void *btree_remove128(struct btree_head128 *head, u64 k1, u64 k2) argument 28 btree_get_prev128(struct btree_head128 *head, u64 *k1, u64 *k2) argument 63 btree_last128(struct btree_head128 *head, u64 *k1, u64 *k2) argument [all...] |
/linux-master/arch/arm/crypto/ |
H A D | nh-neon-core.S | 49 .macro _nh_stride k0, k1, k2, k3 60 vadd.u32 T2, T3, \k2
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H A D | sha1-ce-core.S | 18 k2 .req q2 69 vld1.32 {k2-k3}, [ip, :128] 100 add_update p, 1, k2, 9, 10, 11, 8 102 add_update m, 0, k2, 10, 11, 8, 9 103 add_update m, 1, k2, 11, 8, 9, 10 104 add_update m, 0, k2, 8, 9, 10, 11 105 add_update m, 1, k2, 9, 10, 11, 8
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/linux-master/arch/arm64/boot/dts/amlogic/ |
H A D | Makefile | 33 dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
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/linux-master/arch/arm64/crypto/ |
H A D | aes-ce.S | 86 .macro fin_round_Nx, de, k, k2, i0, i1, i2, i3, i4 98 eor \i0\().16b, \i0\().16b, \k2\().16b 100 eor \i1\().16b, \i1\().16b, \k2\().16b 102 eor \i2\().16b, \i2\().16b, \k2\().16b 103 eor \i3\().16b, \i3\().16b, \k2\().16b 105 eor \i4\().16b, \i4\().16b, \k2\().16b
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H A D | nh-neon-core.S | 35 .macro _nh_stride k0, k1, k2, k3 46 add T2.4s, T3.4s, \k2\().4s
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H A D | sha1-ce-core.S | 16 k2 .req v2 72 loadrc k2.4s, 0x8f1bbcdc, w6 105 add_update p, od, k2, 9, 10, 11, 8 107 add_update m, ev, k2, 10, 11, 8, 9 108 add_update m, od, k2, 11, 8, 9, 10 109 add_update m, ev, k2, 8, 9, 10, 11 110 add_update m, od, k2, 9, 10, 11, 8
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/linux-master/arch/riscv/crypto/ |
H A D | sha256-riscv64-zvknha_or_zvknhb-zvkb.S | 102 .macro sha256_16rounds last, k0, k1, k2, k3 105 sha256_4rounds \last, \k2, W2, W3, W0, W1
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/linux-master/arch/sparc/crypto/ |
H A D | des_glue.c | 186 u64 k2[DES_EXPKEY_WORDS / 2]; local 196 des_sparc64_key_expand((const u32 *)key, k2); 201 encrypt_to_decrypt(&dctx->encrypt_expkey[DES_EXPKEY_WORDS / 2], &k2[0]); 207 &k2[0], sizeof(k2));
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/linux-master/arch/x86/crypto/ |
H A D | nh-avx2-x86_64.S | 40 .macro _nh_2xstride k0, k1, k2, k3 45 vpaddd \k2, T3, T2
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H A D | nh-sse2-x86_64.S | 34 .macro _nh_stride k0, k1, k2, k3, offset 47 paddd \k2, T2
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H A D | poly1305-x86_64-cryptogams.pl | 2220 kmovw %eax,%k2 2264 vmovdqa64 $R0,0x00(%rsp){%k2} # save in case $len%128 != 0 2267 vmovdqu64 $R1,0x00(%rsp,%rax){%k2} 2270 vmovdqa64 $S1,0x40(%rsp){%k2} 2273 vmovdqu64 $R2,0x40(%rsp,%rax){%k2} 2275 vmovdqa64 $S2,0x80(%rsp){%k2} 2276 vmovdqu64 $R3,0x80(%rsp,%rax){%k2} 2277 vmovdqa64 $S3,0xc0(%rsp){%k2} 2278 vmovdqu64 $R4,0xc0(%rsp,%rax){%k2} 2279 vmovdqa64 $S4,0x100(%rsp){%k2} [all...] |
/linux-master/arch/x86/kvm/svm/ |
H A D | avic.c | 197 struct kvm_svm *k2; local 228 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) { 229 if (k2->avic_vm_id == vm_id)
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/linux-master/crypto/ |
H A D | tea.c | 60 u32 k0, k1, k2, k3; local 70 k2 = ctx->KEY[2]; 78 z += ((y << 4) + k2) ^ (y + sum) ^ ((y >> 5) + k3); 88 u32 k0, k1, k2, k3; local 98 k2 = ctx->KEY[2]; 106 z -= ((y << 4) + k2) ^ (y + sum) ^ ((y >> 5) + k3);
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H A D | vmac.c | 284 #define k2 (*(((u32 *)kh)+INDEX_LOW)) macro 293 p += MUL32(a0, k2); 299 p += MUL32(a1, k2); 307 q += MUL32(a2, k2); 317 q += MUL32(a3, k2); 330 #undef k2 macro 359 static u64 l3hash(u64 p1, u64 p2, u64 k1, u64 k2, u64 len) argument 379 /* compute (p1+k1)%p64 and (p2+k2)%p64 */ 382 p2 += k2; 383 p2 += (0 - (p2 < k2)) [all...] |
/linux-master/drivers/clk/sprd/ |
H A D | pll.c | 105 u16 k1, k2; local 134 k2 = pll->k2; 137 k2 + refin * nint * CLK_PLL_1M;
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H A D | pll.h | 57 u16 k2; member in struct:sprd_pll 74 .k2 = _k2, \
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/linux-master/drivers/crypto/ccp/ |
H A D | ccp-crypto-aes-cmac.c | 317 gk = (__be64 *)ctx->u.aes.k2; 324 sg_init_one(&ctx->u.aes.k2_sg, ctx->u.aes.k2, sizeof(ctx->u.aes.k2));
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H A D | ccp-crypto.h | 110 u8 k2[AES_BLOCK_SIZE]; member in struct:ccp_aes_ctx
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn314/ |
H A D | dcn314_dccg.c | 62 enum pixel_rate_div *k2) 68 *k2 = PIXEL_RATE_DIV_NA; 97 *k2 = (enum pixel_rate_div)val_k2; 104 enum pixel_rate_div k2) 111 if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) { 117 if (k1 == cur_k1 && k2 == cur_k2) 124 OTG0_PIXEL_RATE_DIVK2, k2); 129 OTG1_PIXEL_RATE_DIVK2, k2); 134 OTG2_PIXEL_RATE_DIVK2, k2); 139 OTG3_PIXEL_RATE_DIVK2, k2); 58 dccg314_get_pixel_rate_div( struct dccg *dccg, uint32_t otg_inst, enum pixel_rate_div *k1, enum pixel_rate_div *k2) argument 100 dccg314_set_pixel_rate_div( struct dccg *dccg, uint32_t otg_inst, enum pixel_rate_div k1, enum pixel_rate_div k2) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
H A D | dcn32_dccg.c | 62 enum pixel_rate_div *k2) 68 *k2 = PIXEL_RATE_DIV_NA; 97 *k2 = (enum pixel_rate_div)val_k2; 104 enum pixel_rate_div k2) 112 if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) { 118 if (k1 == cur_k1 && k2 == cur_k2) 125 OTG0_PIXEL_RATE_DIVK2, k2); 130 OTG1_PIXEL_RATE_DIVK2, k2); 135 OTG2_PIXEL_RATE_DIVK2, k2); 140 OTG3_PIXEL_RATE_DIVK2, k2); 58 dccg32_get_pixel_rate_div( struct dccg *dccg, uint32_t otg_inst, enum pixel_rate_div *k1, enum pixel_rate_div *k2) argument 100 dccg32_set_pixel_rate_div( struct dccg *dccg, uint32_t otg_inst, enum pixel_rate_div k1, enum pixel_rate_div k2) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
H A D | dcn35_dccg.c | 107 enum pixel_rate_div *k2) 113 *k2 = PIXEL_RATE_DIV_NA; 142 *k2 = (enum pixel_rate_div)val_k2; 149 enum pixel_rate_div k2) 156 if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) { 162 if (k1 == cur_k1 && k2 == cur_k2) 169 OTG0_PIXEL_RATE_DIVK2, k2); 174 OTG1_PIXEL_RATE_DIVK2, k2); 179 OTG2_PIXEL_RATE_DIVK2, k2); 184 OTG3_PIXEL_RATE_DIVK2, k2); 103 dccg35_get_pixel_rate_div( struct dccg *dccg, uint32_t otg_inst, enum pixel_rate_div *k1, enum pixel_rate_div *k2) argument 145 dccg35_set_pixel_rate_div( struct dccg *dccg, uint32_t otg_inst, enum pixel_rate_div k1, enum pixel_rate_div k2) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
H A D | dccg.h | 172 enum pixel_rate_div k2);
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