Searched refs:gvt (Results 1 - 25 of 32) sorted by last modified time

12

/linux-master/drivers/gpu/drm/i915/
H A Di915_drv.h209 struct intel_gvt *gvt; member in struct:drm_i915_private
H A DMakefile413 include $(src)/gvt/Makefile
H A Dintel_gvt.c45 * doc is available on https://github.com/intel/gvt-linux/wiki.
185 if (dev_priv->gvt)
278 if (dev_priv->gvt)
/linux-master/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c41 #include "gvt.h"
66 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
68 struct drm_i915_private *i915 = gvt->gt->i915;
84 static bool intel_gvt_match_device(struct intel_gvt *gvt,
87 return intel_gvt_get_device_type(gvt) & device;
102 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt,
107 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
114 static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size,
121 if (!intel_gvt_match_device(gvt, device))
131 p = intel_gvt_find_mmio_info(gvt,
65 intel_gvt_get_device_type(struct intel_gvt *gvt) argument
83 intel_gvt_match_device(struct intel_gvt *gvt, unsigned long device) argument
101 intel_gvt_find_mmio_info(struct intel_gvt *gvt, unsigned int offset) argument
113 setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size, u16 flags, u32 addr_mask, u32 ro_mask, u32 device, gvt_mmio_func read, gvt_mmio_func write) argument
155 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset) argument
258 struct intel_gvt *gvt = vgpu->gvt; local
1948 struct intel_gvt *gvt = vgpu->gvt; local
2181 init_generic_mmio_info(struct intel_gvt *gvt) argument
2444 init_bdw_mmio_info(struct intel_gvt *gvt) argument
2579 init_skl_mmio_info(struct intel_gvt *gvt) argument
2750 init_bxt_mmio_info(struct intel_gvt *gvt) argument
2798 find_mmio_block(struct intel_gvt *gvt, unsigned int offset) argument
2821 intel_gvt_clean_mmio_info(struct intel_gvt *gvt) argument
2841 struct intel_gvt *gvt = iter->data; local
2880 struct intel_gvt *gvt = iter->data; local
2913 init_mmio_info(struct intel_gvt *gvt) argument
2924 init_mmio_block_handlers(struct intel_gvt *gvt) argument
2951 intel_gvt_setup_mmio_info(struct intel_gvt *gvt) argument
3015 intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), void *data) argument
3112 intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, unsigned int offset) argument
3133 struct intel_gvt *gvt = vgpu->gvt; local
3203 intel_gvt_restore_fence(struct intel_gvt *gvt) argument
3216 mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data) argument
3227 intel_gvt_restore_mmio(struct intel_gvt *gvt) argument
[all...]
H A Dmmio.c39 #include "gvt.h"
59 #define reg_is_mmio(gvt, reg) \
60 (reg >= 0 && reg < gvt->device_info.mmio_size)
62 #define reg_is_gtt(gvt, reg) \
63 (reg >= gvt->device_info.gtt_start_offset \
64 && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
69 struct intel_gvt *gvt = NULL;
76 gvt = vgpu->gvt;
68 struct intel_gvt *gvt = NULL; local
110 struct intel_gvt *gvt = vgpu->gvt; local
185 struct intel_gvt *gvt = vgpu->gvt; local
247 struct intel_gvt *gvt = vgpu->gvt; local
[all...]
H A Ddisplay.c37 #include "gvt.h"
66 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
78 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
178 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
534 intel_gvt_request_service(vgpu->gvt,
543 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
626 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
658 for_each_pipe(vgpu->gvt->gt->i915, pipe)
673 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
762 struct drm_i915_private *dev_priv = vgpu->gvt
[all...]
H A Dfb_decoder.c38 #include "gvt.h"
153 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
209 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
339 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
H A Dcmd_parser.c48 #include "gvt.h"
520 (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
666 find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode, argument
671 hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
680 get_cmd_info(struct intel_gvt *gvt, u32 cmd, argument
689 return find_cmd_entry(gvt, opcode, engine);
896 struct intel_gvt *gvt = vgpu->gvt; local
900 if (offset + 4 > gvt->device_info.mmio_size) {
909 intel_gvt_mmio_set_cmd_accessible(gvt, offse
1095 struct intel_gvt *gvt = s->vgpu->gvt; local
2717 add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e) argument
3104 struct intel_gvt *gvt = vgpu->gvt; local
3208 init_cmd_table(struct intel_gvt *gvt) argument
3237 clean_cmd_table(struct intel_gvt *gvt) argument
3249 intel_gvt_clean_cmd_parser(struct intel_gvt *gvt) argument
3254 intel_gvt_init_cmd_parser(struct intel_gvt *gvt) argument
[all...]
H A Dkvmgt.c54 #include "gvt.h"
180 struct device *dev = vgpu->gvt->gt->i915->drm.dev;
203 struct device *dev = vgpu->gvt->gt->i915->drm.dev;
639 mutex_lock(&vgpu->gvt->lock);
640 for_each_active_vgpu(vgpu->gvt, itr, id) {
650 mutex_unlock(&vgpu->gvt->lock);
775 aperture_va = io_mapping_map_wc(&vgpu->gvt->gt->ggtt->iomap,
842 struct intel_gvt *gvt = vgpu->gvt; local
852 return (offset >= gvt
1515 struct intel_gvt *gvt = kdev_to_i915(mtype->parent->dev)->gvt; local
1719 init_device_info(struct intel_gvt *gvt) argument
1736 intel_gvt_test_and_emulate_vblank(struct intel_gvt *gvt) argument
1754 struct intel_gvt *gvt = (struct intel_gvt *)data; local
1782 clean_service_thread(struct intel_gvt *gvt) argument
1787 init_service_thread(struct intel_gvt *gvt) argument
1810 struct intel_gvt *gvt = fetch_and_zero(&i915->gvt); local
1845 struct intel_gvt *gvt; local
1952 struct intel_gvt *gvt = i915->gvt; local
[all...]
H A Dscheduler.h139 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt);
141 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt);
H A Dmmio.h71 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int reg);
72 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt);
74 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt);
75 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt);
76 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
77 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
80 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt,
99 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
108 void intel_gvt_restore_fence(struct intel_gvt *gvt);
109 void intel_gvt_restore_mmio(struct intel_gvt *gvt);
[all...]
H A Dinterrupt.c36 #include "gvt.h"
166 struct intel_gvt *gvt,
169 struct intel_gvt_irq *irq = &gvt->irq;
197 struct intel_gvt *gvt = vgpu->gvt; local
198 const struct intel_gvt_irq_ops *ops = gvt->irq.ops;
227 struct intel_gvt *gvt = vgpu->gvt; local
228 const struct intel_gvt_irq_ops *ops = gvt->irq.ops;
266 struct intel_gvt *gvt local
165 regbase_to_irq_info( struct intel_gvt *gvt, unsigned int reg) argument
552 struct intel_gvt *gvt = irq_to_gvt(irq); local
680 struct intel_gvt *gvt = vgpu->gvt; local
714 intel_gvt_init_irq(struct intel_gvt *gvt) argument
[all...]
H A Dinterrupt.h193 int intel_gvt_init_irq(struct intel_gvt *gvt);
H A Dgvt.h184 struct intel_gvt *gvt; member in struct:intel_vgpu
192 /* Both sched_data and sched_ctl can be seen a part of the global gvt
326 /* scheduler scope lock, protect gvt and vgpu schedule related data */
352 * use it with atomic bit ops so that no need to use gvt big lock.
382 static inline void intel_gvt_request_service(struct intel_gvt *gvt, argument
385 set_bit(service, (void *)&gvt->service_request);
386 wake_up(&gvt->service_thread_wq);
389 void intel_gvt_free_firmware(struct intel_gvt *gvt);
390 int intel_gvt_load_firmware(struct intel_gvt *gvt);
400 #define gvt_to_ggtt(gvt) ((gv
593 intel_gvt_mmio_set_accessed( struct intel_gvt *gvt, unsigned int offset) argument
607 intel_gvt_mmio_is_cmd_accessible( struct intel_gvt *gvt, unsigned int offset) argument
620 intel_gvt_mmio_set_cmd_accessible( struct intel_gvt *gvt, unsigned int offset) argument
632 intel_gvt_mmio_is_unalign( struct intel_gvt *gvt, unsigned int offset) argument
647 intel_gvt_mmio_has_mode_mask( struct intel_gvt *gvt, unsigned int offset) argument
663 intel_gvt_mmio_is_sr_in_ctx( struct intel_gvt *gvt, unsigned int offset) argument
677 intel_gvt_mmio_set_sr_in_ctx( struct intel_gvt *gvt, unsigned int offset) argument
692 intel_gvt_mmio_set_cmd_write_patch( struct intel_gvt *gvt, unsigned int offset) argument
707 intel_gvt_mmio_is_cmd_write_patch( struct intel_gvt *gvt, unsigned int offset) argument
[all...]
H A Dgtt.h223 int intel_gvt_init_gtt(struct intel_gvt *gvt);
224 void intel_gvt_clean_gtt(struct intel_gvt *gvt);
291 void intel_gvt_restore_ggtt(struct intel_gvt *gvt);
H A Dmmio_context.c43 #include "gvt.h"
176 struct intel_gvt *gvt = engine->i915->gvt; local
178 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt;
179 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list;
215 struct intel_gvt *gvt = vgpu->gvt; local
217 int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id];
231 for (mmio = gvt->engine_mmio_list.mmio;
366 u32 *regs = vgpu->gvt
592 intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt) argument
[all...]
H A Dmmio_context.h53 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt);
H A Dgtt.c37 #include "gvt.h"
77 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
95 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
97 if (drm_WARN(&i915->drm, !gvt_gmadr_is_valid(vgpu->gvt, h_addr),
101 if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
103 + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
106 + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
306 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
319 e->val64 = read_pte64(vgpu->gvt->gt->ggtt, index);
331 const struct intel_gvt_device_info *info = &vgpu->gvt
654 struct intel_gvt *gvt = spt->vgpu->gvt; local
683 struct intel_gvt *gvt = spt->vgpu->gvt; local
1404 struct intel_gvt *gvt = vgpu->gvt; local
1446 struct intel_gvt *gvt = vgpu->gvt; local
1465 struct intel_gvt *gvt = spt->vgpu->gvt; local
1502 struct intel_gvt *gvt = spt->vgpu->gvt; local
1756 struct intel_gvt *gvt = vgpu->gvt; local
1786 struct intel_gvt *gvt = vgpu->gvt; local
1863 struct intel_gvt *gvt = vgpu->gvt; local
2014 reclaim_one_ppgtt_mm(struct intel_gvt *gvt) argument
2071 struct intel_gvt *gvt = vgpu->gvt; local
2208 struct intel_gvt *gvt = vgpu->gvt; local
2537 clean_spt_oos(struct intel_gvt *gvt) argument
2554 setup_spt_oos(struct intel_gvt *gvt) argument
2687 intel_gvt_init_gtt(struct intel_gvt *gvt) argument
2738 intel_gvt_clean_gtt(struct intel_gvt *gvt) argument
2787 struct intel_gvt *gvt = vgpu->gvt; local
2828 intel_gvt_restore_ggtt(struct intel_gvt *gvt) argument
[all...]
H A Dscheduler.c48 #include "gvt.h"
87 struct drm_i915_private *dev_priv = workload->vgpu->gvt->gt->i915;
130 struct intel_gvt *gvt = vgpu->gvt; local
218 if (IS_BROADWELL(gvt->gt->i915) && workload->engine->id == RCS0)
290 struct intel_gvt *gvt = container_of(nb, struct intel_gvt, local
292 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
379 * requests from gvt always set the has_init_breadcrumb flag, here
524 struct intel_gvt *gvt = workload->vgpu->gvt; local
848 pick_next_workload(struct intel_gvt *gvt, struct intel_engine_cs *engine) argument
1066 complete_current_workload(struct intel_gvt *gvt, int ring_id) argument
1154 struct intel_gvt *gvt = engine->i915->gvt; local
1231 struct intel_gvt *gvt = vgpu->gvt; local
1242 intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt) argument
1258 intel_gvt_init_workload_scheduler(struct intel_gvt *gvt) argument
[all...]
H A Dedid.c37 #include "gvt.h"
141 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
282 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
379 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
409 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
481 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
H A Daperture_gm.c40 #include "gvt.h"
44 struct intel_gvt *gvt = vgpu->gvt; local
45 struct intel_gt *gt = gvt->gt;
54 start = ALIGN(gvt_hidden_gmadr_base(gvt), I915_GTT_PAGE_SIZE);
55 end = ALIGN(gvt_hidden_gmadr_end(gvt), I915_GTT_PAGE_SIZE);
60 start = ALIGN(gvt_aperture_gmadr_base(gvt), I915_GTT_PAGE_SIZE);
61 end = ALIGN(gvt_aperture_gmadr_end(gvt), I915_GTT_PAGE_SIZE);
82 struct intel_gvt *gvt = vgpu->gvt; local
110 struct intel_gvt *gvt = vgpu->gvt; local
132 struct intel_gvt *gvt = vgpu->gvt; local
168 struct intel_gvt *gvt = vgpu->gvt; local
193 struct intel_gvt *gvt = vgpu->gvt; local
235 struct intel_gvt *gvt = vgpu->gvt; local
245 struct intel_gvt *gvt = vgpu->gvt; local
323 struct intel_gvt *gvt = vgpu->gvt; local
[all...]
H A Dvgpu.c35 #include "gvt.h"
41 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
100 * @gvt : GVT device
105 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
107 unsigned int low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
108 unsigned int high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
112 gvt->types = kcalloc(num_types, sizeof(struct intel_vgpu_type),
114 if (!gvt->types)
117 gvt->mdev_types = kcalloc(num_types, sizeof(*gvt
104 intel_gvt_init_vgpu_types(struct intel_gvt *gvt) argument
154 intel_gvt_clean_vgpu_types(struct intel_gvt *gvt) argument
226 struct intel_gvt *gvt = vgpu->gvt; local
266 intel_gvt_create_idle_vgpu(struct intel_gvt *gvt) argument
314 struct intel_gvt *gvt = vgpu->gvt; local
437 struct intel_gvt *gvt = vgpu->gvt; local
[all...]
H A Ddebugfs.c26 #include "gvt.h"
58 static inline int mmio_diff_handler(struct intel_gvt *gvt, argument
65 preg = intel_uncore_read_notrace(gvt->gt->uncore, _MMIO(offset));
87 struct intel_gvt *gvt = vgpu->gvt; local
97 mutex_lock(&gvt->lock);
98 spin_lock_bh(&gvt->scheduler.mmio_context_lock);
100 mmio_hw_access_pre(gvt->gt);
102 intel_gvt_for_each_tracked_mmio(gvt, mmio_diff_handler, &param);
103 mmio_hw_access_post(gvt
195 struct intel_gvt *gvt = vgpu->gvt; local
208 intel_gvt_debugfs_init(struct intel_gvt *gvt) argument
222 intel_gvt_debugfs_clean(struct intel_gvt *gvt) argument
[all...]
H A Dfirmware.c36 #include "gvt.h"
70 static int expose_firmware_sysfs(struct intel_gvt *gvt)
72 struct intel_gvt_device_info *info = &gvt->device_info;
73 struct drm_i915_private *i915 = gvt->gt->i915;
97 memcpy(gvt->firmware.cfg_space, i915->vgpu.initial_cfg_space,
99 memcpy(p, gvt->firmware.cfg_space, info->cfg_space_size);
103 memcpy(gvt->firmware.mmio, i915->vgpu.initial_mmio,
106 memcpy(p, gvt->firmware.mmio, info->mmio_size);
122 static void clean_firmware_sysfs(struct intel_gvt *gvt)
124 struct pci_dev *pdev = to_pci_dev(gvt
69 expose_firmware_sysfs(struct intel_gvt *gvt) argument
121 clean_firmware_sysfs(struct intel_gvt *gvt) argument
134 intel_gvt_free_firmware(struct intel_gvt *gvt) argument
143 verify_firmware(struct intel_gvt *gvt, const struct firmware *fw) argument
198 intel_gvt_load_firmware(struct intel_gvt *gvt) argument
[all...]
H A Ddmabuf.c41 #include "gvt.h"
404 struct drm_device *dev = &vgpu->gvt->gt->i915->drm;
502 struct drm_device *dev = &vgpu->gvt->gt->i915->drm;
520 gvt_vgpu_err("create gvt gem obj failed\n");

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