| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| H A D | dcn35_hwseq.c | 487 void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on) argument
494 hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);
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| H A D | dcn35_hwseq.h | 38 void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 319 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz; local
324 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
342 clk_mgr->dccg, dpp_inst, dppclk_khz);
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 186 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz; local
191 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
209 clk_mgr->dccg, dpp_inst, dppclk_khz);
210 dppclk_active[dpp_inst] = true;
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| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| H A D | dcn314_hwseq.c | 381 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on) argument
388 hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);
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| H A D | dcn314_hwseq.h | 46 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
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| /linux-master/drivers/gpu/drm/amd/display/dmub/inc/ |
| H A D | dmub_cmd.h | 2352 uint8_t dpp_inst; member in struct:dmub_cmd_psr_copy_settings_data
3026 uint8_t dpp_inst; member in struct:dmub_cmd_replay_copy_settings_data
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| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 544 unsigned int dpp_inst,
555 switch (dpp_inst) {
542 dcn20_dpp_pg_control( struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) argument
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| H A D | dcn20_hwseq.h | 104 unsigned int dpp_inst,
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| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer_private.h | 121 unsigned int dpp_inst,
124 unsigned int dpp_inst,
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| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 666 * @dpp_inst: DPP instance reference.
673 unsigned int dpp_inst,
684 switch (dpp_inst) {
671 dcn10_dpp_pg_control( struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) argument
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| H A D | dcn10_hwseq.h | 92 unsigned int dpp_inst,
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| /linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dmub_replay.c | 175 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
177 copy_settings_data->dpp_inst = 0;
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| H A D | dmub_psr.c | 342 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
344 copy_settings_data->dpp_inst = 0;
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 114 int dpp_inst, dppclk_khz, prev_dppclk_khz; local
119 dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst;
122 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[dpp_inst];
126 clk_mgr->dccg, dpp_inst, dppclk_khz);
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| /linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | dccg.h | 96 int dpp_inst,
185 unsigned int dpp_inst,
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
| H A D | dcn35_dccg.c | 45 uint32_t dpp_inst, uint32_t enable)
49 switch (dpp_inst) {
68 static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, argument
73 if (dccg->dpp_clock_gated[dpp_inst]) {
93 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
97 dcn35_set_dppclk_enable(dccg, dpp_inst, true);
99 dcn35_set_dppclk_enable(dccg, dpp_inst, false);
100 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
484 unsigned int dpp_inst,
489 if (dccg->dpp_clock_gated[dpp_inst]
44 dcn35_set_dppclk_enable(struct dccg *dccg, uint32_t dpp_inst, uint32_t enable) argument
482 dccg35_dpp_root_clock_control( struct dccg *dccg, unsigned int dpp_inst, bool clock_on) argument
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dccg.h | 404 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
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| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn303/ |
| H A D | dcn303_hwseq.c | 46 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) argument
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| H A D | dcn303_hwseq.h | 32 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
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| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn302/ |
| H A D | dcn302_hwseq.c | 45 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) argument
55 switch (dpp_inst) {
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| H A D | dcn302_hwseq.h | 31 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_dccg.c | 330 unsigned int dpp_inst,
335 if (dccg->dpp_clock_gated[dpp_inst] != clock_on)
340 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0);
341 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
346 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 1);
347 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
352 dccg->dpp_clock_gated[dpp_inst] = !clock_on;
328 dccg314_dpp_root_clock_control( struct dccg *dccg, unsigned int dpp_inst, bool clock_on) argument
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 111 int dpp_inst, dppclk_khz, prev_dppclk_khz; local
116 dpp_inst = i;
123 clk_mgr->dccg, dpp_inst, dppclk_khz);
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_dccg.h | 199 int dpp_inst,
|