Searched refs:csr (Results 1 - 25 of 44) sorted by path

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/freebsd-11-stable/crypto/heimdal/lib/sqlite/
H A Dsqlite3.c119092 Fts3MultiSegReader csr; /* Must be right after "base" */ member in struct:Fts3auxCursor
124926 Fts3MultiSegReader csr; /* Cursor to iterate through level(s) */ local
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/freebsd-11-stable/sys/amd64/amd64/
H A Dfpu.c76 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
109 void ldmxcsr(u_int csr);
110 void stmxcsr(u_int *csr);
/freebsd-11-stable/sys/arm/at91/
H A Dat91_spi.c120 uint32_t csr; local
171 csr = SPI_CSR_CPOL | (4 << 16) | (0xff << 8);
172 WR4(sc, SPI_CSR0, csr);
173 WR4(sc, SPI_CSR1, csr);
174 WR4(sc, SPI_CSR2, csr);
175 WR4(sc, SPI_CSR3, csr);
H A Duart_dev_at91usart.c651 uint32_t csr; local
656 csr = RD4(&sc->sc_bas, USART_CSR);
658 if (csr & USART_CSR_OVRE) {
663 if (csr & USART_DCE_CHANGE_BITS)
666 if (csr & USART_CSR_ENDTX) {
671 if (csr & (USART_CSR_TXRDY | USART_CSR_ENDTX)) {
674 WR4(&sc->sc_bas, USART_IDR, csr & (USART_CSR_TXRDY |
685 if (csr & USART_CSR_RXBUFF) {
712 } else if (csr & USART_CSR_ENDRX) {
731 } else if (csr
805 uint32_t csr, new, old, sig; local
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/freebsd-11-stable/sys/arm/freescale/vybrid/
H A Dvf_edma.h167 uint16_t csr; member in struct:TCD
/freebsd-11-stable/sys/arm/ti/
H A Dti_sdma.c220 uint32_t csr; local
240 csr = ti_sdma_read_4(sc, DMA4_CSR(ch));
241 if (csr == 0) {
255 if (csr & DMA4_CSR_DROP)
259 if (csr & DMA4_CSR_SECURE_ERR)
262 if (csr & DMA4_CSR_MISALIGNED_ADRS_ERR)
265 if (csr & DMA4_CSR_TRANS_ERR) {
282 channel->callback(ch, csr, channel->callback_data);
586 uint32_t csr; local
601 csr
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/freebsd-11-stable/sys/contrib/octeon-sdk/
H A Dcvmx-helper.h83 * @param chcsr_init intial value of the csr (CVMX_HELPER_CSR_INIT_READ
84 * means to use the existing csr value as the
86 * @param chcsr_csr the name of the csr
87 * @param chcsr_type the type of the csr (see the -defs.h)
88 * @param chcsr_chip the chip for the csr/field
89 * @param chcsr_fld the field in the csr
95 chcsr_type csr; \
97 csr.u64 = cvmx_read_csr(chcsr_csr); \
99 csr.u64 = (chcsr_init); \
100 csr
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H A Dcvmx-npei-defs.h6611 uint64_t use_csr : 1; /**< When set '1' the csr value will be used for
7165 uint64_t csr : 39; /**< CSR State */ member in struct:cvmx_npei_state1::cvmx_npei_state1_s
7167 uint64_t csr : 39;
H A Dcvmx-pko-defs.h2462 uint64_t csr : 1; /**< BiST result of CSR memories (0=pass, !0=fail) */ member in struct:cvmx_pko_reg_bist_result::cvmx_pko_reg_bist_result_cn50xx
2490 uint64_t csr : 1;
2497 uint64_t csr : 1; /**< BiST result of CSR memories (0=pass, !0=fail) */ member in struct:cvmx_pko_reg_bist_result::cvmx_pko_reg_bist_result_cn52xx
2527 uint64_t csr : 1;
2544 uint64_t csr : 1; /**< BiST result of CSR memories (0=pass, !0=fail) */ member in struct:cvmx_pko_reg_bist_result::cvmx_pko_reg_bist_result_cn68xx
2580 uint64_t csr : 1;
2588 uint64_t csr : 1; /**< BiST result of CSR memories (0=pass, !0=fail) */ member in struct:cvmx_pko_reg_bist_result::cvmx_pko_reg_bist_result_cn68xxp1
2624 uint64_t csr : 1;
H A Dcvmx-sli-defs.h1722 uint64_t pipe_err : 1; /**< Illegal packet csr address. */
1723 uint64_t ill_pad : 1; /**< Illegal packet csr address. */
1836 uint64_t ill_pad : 1; /**< Illegal packet csr address. */
1948 uint64_t ill_pad : 1; /**< Illegal packet csr address. */
2042 uint64_t pipe_err : 1; /**< Illegal packet csr address. */
2043 uint64_t ill_pad : 1; /**< Illegal packet csr address. */
2155 uint64_t ill_pad : 1; /**< Illegal packet csr address. */
2276 uint64_t ill_pad : 1; /**< Illegal packet csr address. */
2396 uint64_t ill_pad : 1; /**< Illegal packet csr address. */
2501 uint64_t ill_pad : 1; /**< Illegal packet csr addres
5972 uint64_t csr : 39; /**< CSR State */ member in struct:cvmx_sli_state1::cvmx_sli_state1_s
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/freebsd-11-stable/sys/dev/de/
H A Dif_devar.h39 #define TULIP_CSR_READ(sc, csr) \
42 (sc)->tulip_csrs.csr)
43 #define TULIP_CSR_WRITE(sc, csr, val) \
46 (sc)->tulip_csrs.csr, val)
/freebsd-11-stable/sys/dev/firewire/
H A Dfirewire.c1515 uint32_t *csr; local
1522 csr = dfwdev->csrrom;
1526 err = fw_explore_read_quads(dfwdev, CSRROMOFF, &csr[0], 1);
1531 hdr = (struct csrhdr *)&csr[0];
1542 err = fw_explore_read_quads(dfwdev, CSRROMOFF + 0x04, &csr[1], 4);
1547 binfo = (struct bus_info *)&csr[1];
1633 if (bcmp(&csr[0], &fwdev->csrrom[0], sizeof(uint32_t) * 5) == 0) {
1644 bcopy(&csr[0], &fwdev->csrrom[0], sizeof(uint32_t) * 5);
/freebsd-11-stable/sys/dev/hifn/
H A Dhifn7751.c1805 u_int32_t cmdlen, csr; local
2073 csr = 0;
2075 csr |= HIFN_DMACSR_C_CTRL_ENA;
2079 csr |= HIFN_DMACSR_S_CTRL_ENA;
2083 csr |= HIFN_DMACSR_R_CTRL_ENA;
2087 csr |= HIFN_DMACSR_D_CTRL_ENA;
2090 if (csr)
2091 WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr);
/freebsd-11-stable/sys/dev/le/
H A Dif_le_ledma.c220 uint32_t aui_bit, csr; local
225 csr = L64854_GCSR(dma);
226 aui_bit = csr & E_TP_AUI;
239 csr = L64854_GCSR(dma);
240 csr |= (E_DSBL_WR_INVAL | aui_bit);
241 L64854_SCSR(dma, csr);
/freebsd-11-stable/sys/dev/lmc/
H A Dif_lmc.c150 u_int32_t csr = READ_CSR(TLP_SROM_MII); local
154 csr |= TLP_SROM_DIN; /* DIN setup */
156 csr &= ~TLP_SROM_DIN; /* DIN setup */
157 WRITE_CSR(TLP_SROM_MII, csr);
158 csr |= TLP_SROM_CLK; /* CLK rising edge */
159 WRITE_CSR(TLP_SROM_MII, csr);
160 csr &= ~TLP_SROM_CLK; /* CLK falling edge */
161 WRITE_CSR(TLP_SROM_MII, csr);
170 u_int32_t csr; local
174 csr
202 u_int32_t csr; local
372 u_int32_t csr = READ_CSR(TLP_SROM_MII); local
393 u_int32_t csr; local
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H A Dif_lmc.h1139 # define READ_CSR(csr) bus_space_read_4 (sc->csr_tag, sc->csr_handle, csr)
1140 # define WRITE_CSR(csr, val) bus_space_write_4(sc->csr_tag, sc->csr_handle, csr, val)
/freebsd-11-stable/sys/dev/mii/
H A Dlxtphy.c196 int bmcr, bmsr, csr; local
206 csr = PHY_READ(sc, MII_LXTPHY_CSR);
207 if (csr & CSR_LINK)
227 if (csr & CSR_SPEED)
231 if (csr & CSR_DUPLEX)
/freebsd-11-stable/sys/dev/mk48txx/
H A Dmk48txx.c163 uint8_t csr; local
170 csr = (*sc->sc_nvrd)(dev, clkoff + MK48TXX_ICSR);
171 csr |= MK48TXX_CSR_READ;
172 (*sc->sc_nvwr)(dev, clkoff + MK48TXX_ICSR, csr);
205 csr = (*sc->sc_nvrd)(dev, clkoff + MK48TXX_ICSR);
206 csr &= ~MK48TXX_CSR_READ;
207 (*sc->sc_nvwr)(dev, clkoff + MK48TXX_ICSR, csr);
223 uint8_t csr; local
237 csr = (*sc->sc_nvrd)(dev, clkoff + MK48TXX_ICSR);
238 csr |
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/freebsd-11-stable/sys/dev/oce/
H A Doce_hw.c57 post_status.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc));
62 OCE_WRITE_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc), post_status.dw0);
72 post_status.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc));
462 ctrl.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_CONTROL);
464 OCE_WRITE_CSR_MPU(sc, csr, MPU_EP_CONTROL, ctrl.dw0);
/freebsd-11-stable/sys/dev/pdq/
H A Dpdq_freebsd.h147 #define PDQ_CSR_WRITE(csr, name, data) PDQ_OS_IOWR_32((csr)->csr_bus, (csr)->csr_base, (csr)->name, data)
148 #define PDQ_CSR_READ(csr, name) PDQ_OS_IORD_32((csr)->csr_bus, (csr)->csr_base, (csr)->name)
H A Dpdqvar.h149 #define PDQ_CSR_WRITE(csr, name, data) PDQ_OS_MEMWR_32((csr)->csr_bus, (csr)->name, 0, data)
150 #define PDQ_CSR_READ(csr, name) PDQ_OS_MEMRD_32((csr)->csr_bus, (csr)->name, 0)
/freebsd-11-stable/sys/dev/ppc/
H A Dppc.c711 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ local
716 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
722 outb(csr, SMC665_iCODE);
723 outb(csr, SMC665_iCODE);
726 outb(csr, 0xd);
734 outb(csr, SMC666_iCODE);
735 outb(csr, SMC666_iCODE);
738 outb(csr, 0xd);
745 csr = SMC666_CSR;
753 outb(csr,
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/freebsd-11-stable/sys/dev/sound/sbus/
H A Dcs4231.c739 u_int32_t csr; local
745 csr = APC_READ(sc, APC_CSR);
746 if ((csr & APC_CSR_GI) == 0) {
750 APC_WRITE(sc, APC_CSR, csr);
752 if ((csr & APC_CSR_EIE) && (csr & APC_CSR_EI)) {
759 if ((csr & APC_CSR_PMIE) && (csr & APC_CSR_PMI)) {
774 if ((csr & APC_CSR_CIE) && (csr
801 u_int32_t csr; local
849 u_int32_t csr; local
1351 u_int32_t csr, togo; local
1424 u_int32_t csr, togo; local
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/freebsd-11-stable/sys/dev/usb/controller/
H A Dat91dci.c128 #define AT91_CSR_ACK(csr, what) do { \
129 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \
132 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \
305 uint32_t csr; local
310 csr = AT91_UDP_READ_4(sc, td->status_reg);
312 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
314 temp = csr;
321 if (!(csr & AT91_UDP_CSR_RXSETUP)) {
328 count = (csr
392 uint32_t csr; local
516 uint32_t csr; local
598 uint32_t csr; local
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H A Dmusb_otg.c384 uint8_t csr; local
402 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
404 DPRINTFN(4, "csr=0x%02x\n", csr);
410 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
418 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
422 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
426 if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
431 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
439 if (!(csr
510 uint8_t csr, csrh; local
620 uint8_t csr; local
763 uint8_t csr; local
881 uint8_t csr; local
1061 uint8_t csr, csrh; local
1235 uint8_t csr; local
1271 uint8_t csr, csrh; local
1358 uint8_t csr; local
1426 uint8_t csr; local
1576 uint8_t csr; local
1705 uint8_t csr, csrh; local
1929 uint8_t csr, csrh; local
2883 uint8_t csr; local
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