1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pko-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pko. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_PKO_DEFS_H__ 53232812Sjmallett#define __CVMX_PKO_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull)) 56215976Sjmallett#define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull)) 57215976Sjmallett#define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull)) 58215976Sjmallett#define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull)) 59215976Sjmallett#define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull)) 60215976Sjmallett#define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull)) 61215976Sjmallett#define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull)) 62215976Sjmallett#define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull)) 63215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 64215976Sjmallett#define CVMX_PKO_MEM_DEBUG14 CVMX_PKO_MEM_DEBUG14_FUNC() 65215976Sjmallettstatic inline uint64_t CVMX_PKO_MEM_DEBUG14_FUNC(void) 66215976Sjmallett{ 67232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 68215976Sjmallett cvmx_warn("CVMX_PKO_MEM_DEBUG14 not supported on this chip\n"); 69215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180050001170ull); 70215976Sjmallett} 71215976Sjmallett#else 72215976Sjmallett#define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull)) 73215976Sjmallett#endif 74215976Sjmallett#define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull)) 75215976Sjmallett#define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull)) 76215976Sjmallett#define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull)) 77215976Sjmallett#define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull)) 78215976Sjmallett#define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull)) 79215976Sjmallett#define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull)) 80215976Sjmallett#define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull)) 81215976Sjmallett#define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull)) 82215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 83232812Sjmallett#define CVMX_PKO_MEM_IPORT_PTRS CVMX_PKO_MEM_IPORT_PTRS_FUNC() 84232812Sjmallettstatic inline uint64_t CVMX_PKO_MEM_IPORT_PTRS_FUNC(void) 85232812Sjmallett{ 86232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 87232812Sjmallett cvmx_warn("CVMX_PKO_MEM_IPORT_PTRS not supported on this chip\n"); 88232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050001030ull); 89232812Sjmallett} 90232812Sjmallett#else 91232812Sjmallett#define CVMX_PKO_MEM_IPORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001030ull)) 92232812Sjmallett#endif 93232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 94232812Sjmallett#define CVMX_PKO_MEM_IPORT_QOS CVMX_PKO_MEM_IPORT_QOS_FUNC() 95232812Sjmallettstatic inline uint64_t CVMX_PKO_MEM_IPORT_QOS_FUNC(void) 96232812Sjmallett{ 97232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 98232812Sjmallett cvmx_warn("CVMX_PKO_MEM_IPORT_QOS not supported on this chip\n"); 99232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050001038ull); 100232812Sjmallett} 101232812Sjmallett#else 102232812Sjmallett#define CVMX_PKO_MEM_IPORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001038ull)) 103232812Sjmallett#endif 104232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 105232812Sjmallett#define CVMX_PKO_MEM_IQUEUE_PTRS CVMX_PKO_MEM_IQUEUE_PTRS_FUNC() 106232812Sjmallettstatic inline uint64_t CVMX_PKO_MEM_IQUEUE_PTRS_FUNC(void) 107232812Sjmallett{ 108232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 109232812Sjmallett cvmx_warn("CVMX_PKO_MEM_IQUEUE_PTRS not supported on this chip\n"); 110232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050001040ull); 111232812Sjmallett} 112232812Sjmallett#else 113232812Sjmallett#define CVMX_PKO_MEM_IQUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001040ull)) 114232812Sjmallett#endif 115232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116232812Sjmallett#define CVMX_PKO_MEM_IQUEUE_QOS CVMX_PKO_MEM_IQUEUE_QOS_FUNC() 117232812Sjmallettstatic inline uint64_t CVMX_PKO_MEM_IQUEUE_QOS_FUNC(void) 118232812Sjmallett{ 119232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 120232812Sjmallett cvmx_warn("CVMX_PKO_MEM_IQUEUE_QOS not supported on this chip\n"); 121232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050001048ull); 122232812Sjmallett} 123232812Sjmallett#else 124232812Sjmallett#define CVMX_PKO_MEM_IQUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001048ull)) 125232812Sjmallett#endif 126232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 127215976Sjmallett#define CVMX_PKO_MEM_PORT_PTRS CVMX_PKO_MEM_PORT_PTRS_FUNC() 128215976Sjmallettstatic inline uint64_t CVMX_PKO_MEM_PORT_PTRS_FUNC(void) 129215976Sjmallett{ 130232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 131215976Sjmallett cvmx_warn("CVMX_PKO_MEM_PORT_PTRS not supported on this chip\n"); 132215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180050001010ull); 133215976Sjmallett} 134215976Sjmallett#else 135215976Sjmallett#define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull)) 136215976Sjmallett#endif 137215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 138215976Sjmallett#define CVMX_PKO_MEM_PORT_QOS CVMX_PKO_MEM_PORT_QOS_FUNC() 139215976Sjmallettstatic inline uint64_t CVMX_PKO_MEM_PORT_QOS_FUNC(void) 140215976Sjmallett{ 141232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 142215976Sjmallett cvmx_warn("CVMX_PKO_MEM_PORT_QOS not supported on this chip\n"); 143215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180050001018ull); 144215976Sjmallett} 145215976Sjmallett#else 146215976Sjmallett#define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull)) 147215976Sjmallett#endif 148215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 149215976Sjmallett#define CVMX_PKO_MEM_PORT_RATE0 CVMX_PKO_MEM_PORT_RATE0_FUNC() 150215976Sjmallettstatic inline uint64_t CVMX_PKO_MEM_PORT_RATE0_FUNC(void) 151215976Sjmallett{ 152232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 153215976Sjmallett cvmx_warn("CVMX_PKO_MEM_PORT_RATE0 not supported on this chip\n"); 154215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180050001020ull); 155215976Sjmallett} 156215976Sjmallett#else 157215976Sjmallett#define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull)) 158215976Sjmallett#endif 159215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 160215976Sjmallett#define CVMX_PKO_MEM_PORT_RATE1 CVMX_PKO_MEM_PORT_RATE1_FUNC() 161215976Sjmallettstatic inline uint64_t CVMX_PKO_MEM_PORT_RATE1_FUNC(void) 162215976Sjmallett{ 163232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 164215976Sjmallett cvmx_warn("CVMX_PKO_MEM_PORT_RATE1 not supported on this chip\n"); 165215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180050001028ull); 166215976Sjmallett} 167215976Sjmallett#else 168215976Sjmallett#define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull)) 169215976Sjmallett#endif 170232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 171232812Sjmallett#define CVMX_PKO_MEM_QUEUE_PTRS CVMX_PKO_MEM_QUEUE_PTRS_FUNC() 172232812Sjmallettstatic inline uint64_t CVMX_PKO_MEM_QUEUE_PTRS_FUNC(void) 173232812Sjmallett{ 174232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 175232812Sjmallett cvmx_warn("CVMX_PKO_MEM_QUEUE_PTRS not supported on this chip\n"); 176232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050001000ull); 177232812Sjmallett} 178232812Sjmallett#else 179215976Sjmallett#define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull)) 180232812Sjmallett#endif 181232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 182232812Sjmallett#define CVMX_PKO_MEM_QUEUE_QOS CVMX_PKO_MEM_QUEUE_QOS_FUNC() 183232812Sjmallettstatic inline uint64_t CVMX_PKO_MEM_QUEUE_QOS_FUNC(void) 184232812Sjmallett{ 185232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 186232812Sjmallett cvmx_warn("CVMX_PKO_MEM_QUEUE_QOS not supported on this chip\n"); 187232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050001008ull); 188232812Sjmallett} 189232812Sjmallett#else 190215976Sjmallett#define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull)) 191232812Sjmallett#endif 192232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 193232812Sjmallett#define CVMX_PKO_MEM_THROTTLE_INT CVMX_PKO_MEM_THROTTLE_INT_FUNC() 194232812Sjmallettstatic inline uint64_t CVMX_PKO_MEM_THROTTLE_INT_FUNC(void) 195232812Sjmallett{ 196232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 197232812Sjmallett cvmx_warn("CVMX_PKO_MEM_THROTTLE_INT not supported on this chip\n"); 198232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050001058ull); 199232812Sjmallett} 200232812Sjmallett#else 201232812Sjmallett#define CVMX_PKO_MEM_THROTTLE_INT (CVMX_ADD_IO_SEG(0x0001180050001058ull)) 202232812Sjmallett#endif 203232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 204232812Sjmallett#define CVMX_PKO_MEM_THROTTLE_PIPE CVMX_PKO_MEM_THROTTLE_PIPE_FUNC() 205232812Sjmallettstatic inline uint64_t CVMX_PKO_MEM_THROTTLE_PIPE_FUNC(void) 206232812Sjmallett{ 207232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 208232812Sjmallett cvmx_warn("CVMX_PKO_MEM_THROTTLE_PIPE not supported on this chip\n"); 209232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050001050ull); 210232812Sjmallett} 211232812Sjmallett#else 212232812Sjmallett#define CVMX_PKO_MEM_THROTTLE_PIPE (CVMX_ADD_IO_SEG(0x0001180050001050ull)) 213232812Sjmallett#endif 214215976Sjmallett#define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull)) 215215976Sjmallett#define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull)) 216215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 217215976Sjmallettstatic inline uint64_t CVMX_PKO_REG_CRC_CTLX(unsigned long offset) 218215976Sjmallett{ 219215976Sjmallett if (!( 220215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 221215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 222215976Sjmallett cvmx_warn("CVMX_PKO_REG_CRC_CTLX(%lu) is invalid on this chip\n", offset); 223215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8; 224215976Sjmallett} 225215976Sjmallett#else 226215976Sjmallett#define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8) 227215976Sjmallett#endif 228215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 229215976Sjmallett#define CVMX_PKO_REG_CRC_ENABLE CVMX_PKO_REG_CRC_ENABLE_FUNC() 230215976Sjmallettstatic inline uint64_t CVMX_PKO_REG_CRC_ENABLE_FUNC(void) 231215976Sjmallett{ 232215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 233215976Sjmallett cvmx_warn("CVMX_PKO_REG_CRC_ENABLE not supported on this chip\n"); 234215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000020ull); 235215976Sjmallett} 236215976Sjmallett#else 237215976Sjmallett#define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull)) 238215976Sjmallett#endif 239215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 240215976Sjmallettstatic inline uint64_t CVMX_PKO_REG_CRC_IVX(unsigned long offset) 241215976Sjmallett{ 242215976Sjmallett if (!( 243215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 244215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 245215976Sjmallett cvmx_warn("CVMX_PKO_REG_CRC_IVX(%lu) is invalid on this chip\n", offset); 246215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8; 247215976Sjmallett} 248215976Sjmallett#else 249215976Sjmallett#define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8) 250215976Sjmallett#endif 251215976Sjmallett#define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull)) 252215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 253215976Sjmallett#define CVMX_PKO_REG_DEBUG1 CVMX_PKO_REG_DEBUG1_FUNC() 254215976Sjmallettstatic inline uint64_t CVMX_PKO_REG_DEBUG1_FUNC(void) 255215976Sjmallett{ 256232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 257215976Sjmallett cvmx_warn("CVMX_PKO_REG_DEBUG1 not supported on this chip\n"); 258215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800500000A0ull); 259215976Sjmallett} 260215976Sjmallett#else 261215976Sjmallett#define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull)) 262215976Sjmallett#endif 263215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 264215976Sjmallett#define CVMX_PKO_REG_DEBUG2 CVMX_PKO_REG_DEBUG2_FUNC() 265215976Sjmallettstatic inline uint64_t CVMX_PKO_REG_DEBUG2_FUNC(void) 266215976Sjmallett{ 267232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 268215976Sjmallett cvmx_warn("CVMX_PKO_REG_DEBUG2 not supported on this chip\n"); 269215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800500000A8ull); 270215976Sjmallett} 271215976Sjmallett#else 272215976Sjmallett#define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull)) 273215976Sjmallett#endif 274215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 275215976Sjmallett#define CVMX_PKO_REG_DEBUG3 CVMX_PKO_REG_DEBUG3_FUNC() 276215976Sjmallettstatic inline uint64_t CVMX_PKO_REG_DEBUG3_FUNC(void) 277215976Sjmallett{ 278232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 279215976Sjmallett cvmx_warn("CVMX_PKO_REG_DEBUG3 not supported on this chip\n"); 280215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800500000B0ull); 281215976Sjmallett} 282215976Sjmallett#else 283215976Sjmallett#define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull)) 284215976Sjmallett#endif 285215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 286232812Sjmallett#define CVMX_PKO_REG_DEBUG4 CVMX_PKO_REG_DEBUG4_FUNC() 287232812Sjmallettstatic inline uint64_t CVMX_PKO_REG_DEBUG4_FUNC(void) 288232812Sjmallett{ 289232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 290232812Sjmallett cvmx_warn("CVMX_PKO_REG_DEBUG4 not supported on this chip\n"); 291232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800500000B8ull); 292232812Sjmallett} 293232812Sjmallett#else 294232812Sjmallett#define CVMX_PKO_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x00011800500000B8ull)) 295232812Sjmallett#endif 296232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 297215976Sjmallett#define CVMX_PKO_REG_ENGINE_INFLIGHT CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC() 298215976Sjmallettstatic inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC(void) 299215976Sjmallett{ 300232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 301215976Sjmallett cvmx_warn("CVMX_PKO_REG_ENGINE_INFLIGHT not supported on this chip\n"); 302215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000050ull); 303215976Sjmallett} 304215976Sjmallett#else 305215976Sjmallett#define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull)) 306215976Sjmallett#endif 307215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 308232812Sjmallett#define CVMX_PKO_REG_ENGINE_INFLIGHT1 CVMX_PKO_REG_ENGINE_INFLIGHT1_FUNC() 309232812Sjmallettstatic inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT1_FUNC(void) 310232812Sjmallett{ 311232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 312232812Sjmallett cvmx_warn("CVMX_PKO_REG_ENGINE_INFLIGHT1 not supported on this chip\n"); 313232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000318ull); 314232812Sjmallett} 315232812Sjmallett#else 316232812Sjmallett#define CVMX_PKO_REG_ENGINE_INFLIGHT1 (CVMX_ADD_IO_SEG(0x0001180050000318ull)) 317232812Sjmallett#endif 318232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 319232812Sjmallettstatic inline uint64_t CVMX_PKO_REG_ENGINE_STORAGEX(unsigned long offset) 320232812Sjmallett{ 321232812Sjmallett if (!( 322232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 323232812Sjmallett cvmx_warn("CVMX_PKO_REG_ENGINE_STORAGEX(%lu) is invalid on this chip\n", offset); 324232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8; 325232812Sjmallett} 326232812Sjmallett#else 327232812Sjmallett#define CVMX_PKO_REG_ENGINE_STORAGEX(offset) (CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8) 328232812Sjmallett#endif 329232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 330215976Sjmallett#define CVMX_PKO_REG_ENGINE_THRESH CVMX_PKO_REG_ENGINE_THRESH_FUNC() 331215976Sjmallettstatic inline uint64_t CVMX_PKO_REG_ENGINE_THRESH_FUNC(void) 332215976Sjmallett{ 333232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 334215976Sjmallett cvmx_warn("CVMX_PKO_REG_ENGINE_THRESH not supported on this chip\n"); 335215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000058ull); 336215976Sjmallett} 337215976Sjmallett#else 338215976Sjmallett#define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull)) 339215976Sjmallett#endif 340215976Sjmallett#define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull)) 341215976Sjmallett#define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull)) 342232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 343232812Sjmallett#define CVMX_PKO_REG_GMX_PORT_MODE CVMX_PKO_REG_GMX_PORT_MODE_FUNC() 344232812Sjmallettstatic inline uint64_t CVMX_PKO_REG_GMX_PORT_MODE_FUNC(void) 345232812Sjmallett{ 346232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 347232812Sjmallett cvmx_warn("CVMX_PKO_REG_GMX_PORT_MODE not supported on this chip\n"); 348232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000018ull); 349232812Sjmallett} 350232812Sjmallett#else 351215976Sjmallett#define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull)) 352232812Sjmallett#endif 353215976Sjmallett#define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull)) 354232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 355232812Sjmallett#define CVMX_PKO_REG_LOOPBACK_BPID CVMX_PKO_REG_LOOPBACK_BPID_FUNC() 356232812Sjmallettstatic inline uint64_t CVMX_PKO_REG_LOOPBACK_BPID_FUNC(void) 357232812Sjmallett{ 358232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 359232812Sjmallett cvmx_warn("CVMX_PKO_REG_LOOPBACK_BPID not supported on this chip\n"); 360232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000118ull); 361232812Sjmallett} 362232812Sjmallett#else 363232812Sjmallett#define CVMX_PKO_REG_LOOPBACK_BPID (CVMX_ADD_IO_SEG(0x0001180050000118ull)) 364232812Sjmallett#endif 365232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 366232812Sjmallett#define CVMX_PKO_REG_LOOPBACK_PKIND CVMX_PKO_REG_LOOPBACK_PKIND_FUNC() 367232812Sjmallettstatic inline uint64_t CVMX_PKO_REG_LOOPBACK_PKIND_FUNC(void) 368232812Sjmallett{ 369232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 370232812Sjmallett cvmx_warn("CVMX_PKO_REG_LOOPBACK_PKIND not supported on this chip\n"); 371232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000068ull); 372232812Sjmallett} 373232812Sjmallett#else 374232812Sjmallett#define CVMX_PKO_REG_LOOPBACK_PKIND (CVMX_ADD_IO_SEG(0x0001180050000068ull)) 375232812Sjmallett#endif 376232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 377232812Sjmallett#define CVMX_PKO_REG_MIN_PKT CVMX_PKO_REG_MIN_PKT_FUNC() 378232812Sjmallettstatic inline uint64_t CVMX_PKO_REG_MIN_PKT_FUNC(void) 379232812Sjmallett{ 380232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 381232812Sjmallett cvmx_warn("CVMX_PKO_REG_MIN_PKT not supported on this chip\n"); 382232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000070ull); 383232812Sjmallett} 384232812Sjmallett#else 385232812Sjmallett#define CVMX_PKO_REG_MIN_PKT (CVMX_ADD_IO_SEG(0x0001180050000070ull)) 386232812Sjmallett#endif 387232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 388232812Sjmallett#define CVMX_PKO_REG_PREEMPT CVMX_PKO_REG_PREEMPT_FUNC() 389232812Sjmallettstatic inline uint64_t CVMX_PKO_REG_PREEMPT_FUNC(void) 390232812Sjmallett{ 391232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 392232812Sjmallett cvmx_warn("CVMX_PKO_REG_PREEMPT not supported on this chip\n"); 393232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000110ull); 394232812Sjmallett} 395232812Sjmallett#else 396232812Sjmallett#define CVMX_PKO_REG_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000110ull)) 397232812Sjmallett#endif 398215976Sjmallett#define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull)) 399215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 400232812Sjmallett#define CVMX_PKO_REG_QUEUE_PREEMPT CVMX_PKO_REG_QUEUE_PREEMPT_FUNC() 401232812Sjmallettstatic inline uint64_t CVMX_PKO_REG_QUEUE_PREEMPT_FUNC(void) 402232812Sjmallett{ 403232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 404232812Sjmallett cvmx_warn("CVMX_PKO_REG_QUEUE_PREEMPT not supported on this chip\n"); 405232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000108ull); 406232812Sjmallett} 407232812Sjmallett#else 408232812Sjmallett#define CVMX_PKO_REG_QUEUE_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000108ull)) 409232812Sjmallett#endif 410232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 411215976Sjmallett#define CVMX_PKO_REG_QUEUE_PTRS1 CVMX_PKO_REG_QUEUE_PTRS1_FUNC() 412215976Sjmallettstatic inline uint64_t CVMX_PKO_REG_QUEUE_PTRS1_FUNC(void) 413215976Sjmallett{ 414232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 415215976Sjmallett cvmx_warn("CVMX_PKO_REG_QUEUE_PTRS1 not supported on this chip\n"); 416215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000100ull); 417215976Sjmallett} 418215976Sjmallett#else 419215976Sjmallett#define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull)) 420215976Sjmallett#endif 421215976Sjmallett#define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull)) 422215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 423232812Sjmallett#define CVMX_PKO_REG_THROTTLE CVMX_PKO_REG_THROTTLE_FUNC() 424232812Sjmallettstatic inline uint64_t CVMX_PKO_REG_THROTTLE_FUNC(void) 425232812Sjmallett{ 426232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 427232812Sjmallett cvmx_warn("CVMX_PKO_REG_THROTTLE not supported on this chip\n"); 428232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000078ull); 429232812Sjmallett} 430232812Sjmallett#else 431232812Sjmallett#define CVMX_PKO_REG_THROTTLE (CVMX_ADD_IO_SEG(0x0001180050000078ull)) 432232812Sjmallett#endif 433232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 434215976Sjmallett#define CVMX_PKO_REG_TIMESTAMP CVMX_PKO_REG_TIMESTAMP_FUNC() 435215976Sjmallettstatic inline uint64_t CVMX_PKO_REG_TIMESTAMP_FUNC(void) 436215976Sjmallett{ 437232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 438215976Sjmallett cvmx_warn("CVMX_PKO_REG_TIMESTAMP not supported on this chip\n"); 439215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180050000060ull); 440215976Sjmallett} 441215976Sjmallett#else 442215976Sjmallett#define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull)) 443215976Sjmallett#endif 444215976Sjmallett 445215976Sjmallett/** 446215976Sjmallett * cvmx_pko_mem_count0 447215976Sjmallett * 448215976Sjmallett * Notes: 449215976Sjmallett * Total number of packets seen by PKO, per port 450215976Sjmallett * A write to this address will clear the entry whose index is specified as COUNT[5:0]. 451215976Sjmallett * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 452215976Sjmallett * CSR read operations to this address can be performed. A read of any entry that has not been 453215976Sjmallett * previously written is illegal and will result in unpredictable CSR read data. 454215976Sjmallett */ 455232812Sjmallettunion cvmx_pko_mem_count0 { 456215976Sjmallett uint64_t u64; 457232812Sjmallett struct cvmx_pko_mem_count0_s { 458232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 459215976Sjmallett uint64_t reserved_32_63 : 32; 460215976Sjmallett uint64_t count : 32; /**< Total number of packets seen by PKO */ 461215976Sjmallett#else 462215976Sjmallett uint64_t count : 32; 463215976Sjmallett uint64_t reserved_32_63 : 32; 464215976Sjmallett#endif 465215976Sjmallett } s; 466215976Sjmallett struct cvmx_pko_mem_count0_s cn30xx; 467215976Sjmallett struct cvmx_pko_mem_count0_s cn31xx; 468215976Sjmallett struct cvmx_pko_mem_count0_s cn38xx; 469215976Sjmallett struct cvmx_pko_mem_count0_s cn38xxp2; 470215976Sjmallett struct cvmx_pko_mem_count0_s cn50xx; 471215976Sjmallett struct cvmx_pko_mem_count0_s cn52xx; 472215976Sjmallett struct cvmx_pko_mem_count0_s cn52xxp1; 473215976Sjmallett struct cvmx_pko_mem_count0_s cn56xx; 474215976Sjmallett struct cvmx_pko_mem_count0_s cn56xxp1; 475215976Sjmallett struct cvmx_pko_mem_count0_s cn58xx; 476215976Sjmallett struct cvmx_pko_mem_count0_s cn58xxp1; 477232812Sjmallett struct cvmx_pko_mem_count0_s cn61xx; 478215976Sjmallett struct cvmx_pko_mem_count0_s cn63xx; 479215976Sjmallett struct cvmx_pko_mem_count0_s cn63xxp1; 480232812Sjmallett struct cvmx_pko_mem_count0_s cn66xx; 481232812Sjmallett struct cvmx_pko_mem_count0_s cn68xx; 482232812Sjmallett struct cvmx_pko_mem_count0_s cn68xxp1; 483232812Sjmallett struct cvmx_pko_mem_count0_s cnf71xx; 484215976Sjmallett}; 485215976Sjmalletttypedef union cvmx_pko_mem_count0 cvmx_pko_mem_count0_t; 486215976Sjmallett 487215976Sjmallett/** 488215976Sjmallett * cvmx_pko_mem_count1 489215976Sjmallett * 490215976Sjmallett * Notes: 491215976Sjmallett * Total number of bytes seen by PKO, per port 492215976Sjmallett * A write to this address will clear the entry whose index is specified as COUNT[5:0]. 493215976Sjmallett * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 494215976Sjmallett * CSR read operations to this address can be performed. A read of any entry that has not been 495215976Sjmallett * previously written is illegal and will result in unpredictable CSR read data. 496215976Sjmallett */ 497232812Sjmallettunion cvmx_pko_mem_count1 { 498215976Sjmallett uint64_t u64; 499232812Sjmallett struct cvmx_pko_mem_count1_s { 500232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 501215976Sjmallett uint64_t reserved_48_63 : 16; 502215976Sjmallett uint64_t count : 48; /**< Total number of bytes seen by PKO */ 503215976Sjmallett#else 504215976Sjmallett uint64_t count : 48; 505215976Sjmallett uint64_t reserved_48_63 : 16; 506215976Sjmallett#endif 507215976Sjmallett } s; 508215976Sjmallett struct cvmx_pko_mem_count1_s cn30xx; 509215976Sjmallett struct cvmx_pko_mem_count1_s cn31xx; 510215976Sjmallett struct cvmx_pko_mem_count1_s cn38xx; 511215976Sjmallett struct cvmx_pko_mem_count1_s cn38xxp2; 512215976Sjmallett struct cvmx_pko_mem_count1_s cn50xx; 513215976Sjmallett struct cvmx_pko_mem_count1_s cn52xx; 514215976Sjmallett struct cvmx_pko_mem_count1_s cn52xxp1; 515215976Sjmallett struct cvmx_pko_mem_count1_s cn56xx; 516215976Sjmallett struct cvmx_pko_mem_count1_s cn56xxp1; 517215976Sjmallett struct cvmx_pko_mem_count1_s cn58xx; 518215976Sjmallett struct cvmx_pko_mem_count1_s cn58xxp1; 519232812Sjmallett struct cvmx_pko_mem_count1_s cn61xx; 520215976Sjmallett struct cvmx_pko_mem_count1_s cn63xx; 521215976Sjmallett struct cvmx_pko_mem_count1_s cn63xxp1; 522232812Sjmallett struct cvmx_pko_mem_count1_s cn66xx; 523232812Sjmallett struct cvmx_pko_mem_count1_s cn68xx; 524232812Sjmallett struct cvmx_pko_mem_count1_s cn68xxp1; 525232812Sjmallett struct cvmx_pko_mem_count1_s cnf71xx; 526215976Sjmallett}; 527215976Sjmalletttypedef union cvmx_pko_mem_count1 cvmx_pko_mem_count1_t; 528215976Sjmallett 529215976Sjmallett/** 530215976Sjmallett * cvmx_pko_mem_debug0 531215976Sjmallett * 532215976Sjmallett * Notes: 533215976Sjmallett * Internal per-port state intended for debug use only - pko_prt_psb.cmnd[63:0] 534215976Sjmallett * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 535215976Sjmallett * CSR read operations to this address can be performed. 536215976Sjmallett */ 537232812Sjmallettunion cvmx_pko_mem_debug0 { 538215976Sjmallett uint64_t u64; 539232812Sjmallett struct cvmx_pko_mem_debug0_s { 540232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 541215976Sjmallett uint64_t fau : 28; /**< Fetch and add command words */ 542215976Sjmallett uint64_t cmd : 14; /**< Command word */ 543215976Sjmallett uint64_t segs : 6; /**< Number of segments/gather size */ 544215976Sjmallett uint64_t size : 16; /**< Packet length in bytes */ 545215976Sjmallett#else 546215976Sjmallett uint64_t size : 16; 547215976Sjmallett uint64_t segs : 6; 548215976Sjmallett uint64_t cmd : 14; 549215976Sjmallett uint64_t fau : 28; 550215976Sjmallett#endif 551215976Sjmallett } s; 552215976Sjmallett struct cvmx_pko_mem_debug0_s cn30xx; 553215976Sjmallett struct cvmx_pko_mem_debug0_s cn31xx; 554215976Sjmallett struct cvmx_pko_mem_debug0_s cn38xx; 555215976Sjmallett struct cvmx_pko_mem_debug0_s cn38xxp2; 556215976Sjmallett struct cvmx_pko_mem_debug0_s cn50xx; 557215976Sjmallett struct cvmx_pko_mem_debug0_s cn52xx; 558215976Sjmallett struct cvmx_pko_mem_debug0_s cn52xxp1; 559215976Sjmallett struct cvmx_pko_mem_debug0_s cn56xx; 560215976Sjmallett struct cvmx_pko_mem_debug0_s cn56xxp1; 561215976Sjmallett struct cvmx_pko_mem_debug0_s cn58xx; 562215976Sjmallett struct cvmx_pko_mem_debug0_s cn58xxp1; 563232812Sjmallett struct cvmx_pko_mem_debug0_s cn61xx; 564215976Sjmallett struct cvmx_pko_mem_debug0_s cn63xx; 565215976Sjmallett struct cvmx_pko_mem_debug0_s cn63xxp1; 566232812Sjmallett struct cvmx_pko_mem_debug0_s cn66xx; 567232812Sjmallett struct cvmx_pko_mem_debug0_s cn68xx; 568232812Sjmallett struct cvmx_pko_mem_debug0_s cn68xxp1; 569232812Sjmallett struct cvmx_pko_mem_debug0_s cnf71xx; 570215976Sjmallett}; 571215976Sjmalletttypedef union cvmx_pko_mem_debug0 cvmx_pko_mem_debug0_t; 572215976Sjmallett 573215976Sjmallett/** 574215976Sjmallett * cvmx_pko_mem_debug1 575215976Sjmallett * 576215976Sjmallett * Notes: 577215976Sjmallett * Internal per-port state intended for debug use only - pko_prt_psb.curr[63:0] 578215976Sjmallett * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 579215976Sjmallett * CSR read operations to this address can be performed. 580215976Sjmallett */ 581232812Sjmallettunion cvmx_pko_mem_debug1 { 582215976Sjmallett uint64_t u64; 583232812Sjmallett struct cvmx_pko_mem_debug1_s { 584232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 585215976Sjmallett uint64_t i : 1; /**< "I" value used for free operation */ 586215976Sjmallett uint64_t back : 4; /**< Back value used for free operation */ 587215976Sjmallett uint64_t pool : 3; /**< Pool value used for free operation */ 588215976Sjmallett uint64_t size : 16; /**< Size in bytes */ 589215976Sjmallett uint64_t ptr : 40; /**< Data pointer */ 590215976Sjmallett#else 591215976Sjmallett uint64_t ptr : 40; 592215976Sjmallett uint64_t size : 16; 593215976Sjmallett uint64_t pool : 3; 594215976Sjmallett uint64_t back : 4; 595215976Sjmallett uint64_t i : 1; 596215976Sjmallett#endif 597215976Sjmallett } s; 598215976Sjmallett struct cvmx_pko_mem_debug1_s cn30xx; 599215976Sjmallett struct cvmx_pko_mem_debug1_s cn31xx; 600215976Sjmallett struct cvmx_pko_mem_debug1_s cn38xx; 601215976Sjmallett struct cvmx_pko_mem_debug1_s cn38xxp2; 602215976Sjmallett struct cvmx_pko_mem_debug1_s cn50xx; 603215976Sjmallett struct cvmx_pko_mem_debug1_s cn52xx; 604215976Sjmallett struct cvmx_pko_mem_debug1_s cn52xxp1; 605215976Sjmallett struct cvmx_pko_mem_debug1_s cn56xx; 606215976Sjmallett struct cvmx_pko_mem_debug1_s cn56xxp1; 607215976Sjmallett struct cvmx_pko_mem_debug1_s cn58xx; 608215976Sjmallett struct cvmx_pko_mem_debug1_s cn58xxp1; 609232812Sjmallett struct cvmx_pko_mem_debug1_s cn61xx; 610215976Sjmallett struct cvmx_pko_mem_debug1_s cn63xx; 611215976Sjmallett struct cvmx_pko_mem_debug1_s cn63xxp1; 612232812Sjmallett struct cvmx_pko_mem_debug1_s cn66xx; 613232812Sjmallett struct cvmx_pko_mem_debug1_s cn68xx; 614232812Sjmallett struct cvmx_pko_mem_debug1_s cn68xxp1; 615232812Sjmallett struct cvmx_pko_mem_debug1_s cnf71xx; 616215976Sjmallett}; 617215976Sjmalletttypedef union cvmx_pko_mem_debug1 cvmx_pko_mem_debug1_t; 618215976Sjmallett 619215976Sjmallett/** 620215976Sjmallett * cvmx_pko_mem_debug10 621215976Sjmallett * 622215976Sjmallett * Notes: 623215976Sjmallett * Internal per-port state intended for debug use only - pko.dat.ptr.ptrs1, pko.dat.ptr.ptrs2 624215976Sjmallett * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 625215976Sjmallett * CSR read operations to this address can be performed. 626215976Sjmallett */ 627232812Sjmallettunion cvmx_pko_mem_debug10 { 628215976Sjmallett uint64_t u64; 629232812Sjmallett struct cvmx_pko_mem_debug10_s { 630232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 631215976Sjmallett uint64_t reserved_0_63 : 64; 632215976Sjmallett#else 633215976Sjmallett uint64_t reserved_0_63 : 64; 634215976Sjmallett#endif 635215976Sjmallett } s; 636232812Sjmallett struct cvmx_pko_mem_debug10_cn30xx { 637232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 638215976Sjmallett uint64_t fau : 28; /**< Fetch and add command words */ 639215976Sjmallett uint64_t cmd : 14; /**< Command word */ 640215976Sjmallett uint64_t segs : 6; /**< Number of segments/gather size */ 641215976Sjmallett uint64_t size : 16; /**< Packet length in bytes */ 642215976Sjmallett#else 643215976Sjmallett uint64_t size : 16; 644215976Sjmallett uint64_t segs : 6; 645215976Sjmallett uint64_t cmd : 14; 646215976Sjmallett uint64_t fau : 28; 647215976Sjmallett#endif 648215976Sjmallett } cn30xx; 649215976Sjmallett struct cvmx_pko_mem_debug10_cn30xx cn31xx; 650215976Sjmallett struct cvmx_pko_mem_debug10_cn30xx cn38xx; 651215976Sjmallett struct cvmx_pko_mem_debug10_cn30xx cn38xxp2; 652232812Sjmallett struct cvmx_pko_mem_debug10_cn50xx { 653232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 654215976Sjmallett uint64_t reserved_49_63 : 15; 655215976Sjmallett uint64_t ptrs1 : 17; /**< Internal state */ 656215976Sjmallett uint64_t reserved_17_31 : 15; 657215976Sjmallett uint64_t ptrs2 : 17; /**< Internal state */ 658215976Sjmallett#else 659215976Sjmallett uint64_t ptrs2 : 17; 660215976Sjmallett uint64_t reserved_17_31 : 15; 661215976Sjmallett uint64_t ptrs1 : 17; 662215976Sjmallett uint64_t reserved_49_63 : 15; 663215976Sjmallett#endif 664215976Sjmallett } cn50xx; 665215976Sjmallett struct cvmx_pko_mem_debug10_cn50xx cn52xx; 666215976Sjmallett struct cvmx_pko_mem_debug10_cn50xx cn52xxp1; 667215976Sjmallett struct cvmx_pko_mem_debug10_cn50xx cn56xx; 668215976Sjmallett struct cvmx_pko_mem_debug10_cn50xx cn56xxp1; 669215976Sjmallett struct cvmx_pko_mem_debug10_cn50xx cn58xx; 670215976Sjmallett struct cvmx_pko_mem_debug10_cn50xx cn58xxp1; 671232812Sjmallett struct cvmx_pko_mem_debug10_cn50xx cn61xx; 672215976Sjmallett struct cvmx_pko_mem_debug10_cn50xx cn63xx; 673215976Sjmallett struct cvmx_pko_mem_debug10_cn50xx cn63xxp1; 674232812Sjmallett struct cvmx_pko_mem_debug10_cn50xx cn66xx; 675232812Sjmallett struct cvmx_pko_mem_debug10_cn50xx cn68xx; 676232812Sjmallett struct cvmx_pko_mem_debug10_cn50xx cn68xxp1; 677232812Sjmallett struct cvmx_pko_mem_debug10_cn50xx cnf71xx; 678215976Sjmallett}; 679215976Sjmalletttypedef union cvmx_pko_mem_debug10 cvmx_pko_mem_debug10_t; 680215976Sjmallett 681215976Sjmallett/** 682215976Sjmallett * cvmx_pko_mem_debug11 683215976Sjmallett * 684215976Sjmallett * Notes: 685215976Sjmallett * Internal per-port state intended for debug use only - pko.out.sta.state[22:0] 686215976Sjmallett * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 687215976Sjmallett * CSR read operations to this address can be performed. 688215976Sjmallett */ 689232812Sjmallettunion cvmx_pko_mem_debug11 { 690215976Sjmallett uint64_t u64; 691232812Sjmallett struct cvmx_pko_mem_debug11_s { 692232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 693215976Sjmallett uint64_t i : 1; /**< "I" value used for free operation */ 694215976Sjmallett uint64_t back : 4; /**< Back value used for free operation */ 695215976Sjmallett uint64_t pool : 3; /**< Pool value used for free operation */ 696215976Sjmallett uint64_t size : 16; /**< Size in bytes */ 697215976Sjmallett uint64_t reserved_0_39 : 40; 698215976Sjmallett#else 699215976Sjmallett uint64_t reserved_0_39 : 40; 700215976Sjmallett uint64_t size : 16; 701215976Sjmallett uint64_t pool : 3; 702215976Sjmallett uint64_t back : 4; 703215976Sjmallett uint64_t i : 1; 704215976Sjmallett#endif 705215976Sjmallett } s; 706232812Sjmallett struct cvmx_pko_mem_debug11_cn30xx { 707232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 708215976Sjmallett uint64_t i : 1; /**< "I" value used for free operation */ 709215976Sjmallett uint64_t back : 4; /**< Back value used for free operation */ 710215976Sjmallett uint64_t pool : 3; /**< Pool value used for free operation */ 711215976Sjmallett uint64_t size : 16; /**< Size in bytes */ 712215976Sjmallett uint64_t ptr : 40; /**< Data pointer */ 713215976Sjmallett#else 714215976Sjmallett uint64_t ptr : 40; 715215976Sjmallett uint64_t size : 16; 716215976Sjmallett uint64_t pool : 3; 717215976Sjmallett uint64_t back : 4; 718215976Sjmallett uint64_t i : 1; 719215976Sjmallett#endif 720215976Sjmallett } cn30xx; 721215976Sjmallett struct cvmx_pko_mem_debug11_cn30xx cn31xx; 722215976Sjmallett struct cvmx_pko_mem_debug11_cn30xx cn38xx; 723215976Sjmallett struct cvmx_pko_mem_debug11_cn30xx cn38xxp2; 724232812Sjmallett struct cvmx_pko_mem_debug11_cn50xx { 725232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 726215976Sjmallett uint64_t reserved_23_63 : 41; 727215976Sjmallett uint64_t maj : 1; /**< Internal state */ 728215976Sjmallett uint64_t uid : 3; /**< Internal state */ 729215976Sjmallett uint64_t sop : 1; /**< Internal state */ 730215976Sjmallett uint64_t len : 1; /**< Internal state */ 731215976Sjmallett uint64_t chk : 1; /**< Internal state */ 732215976Sjmallett uint64_t cnt : 13; /**< Internal state */ 733215976Sjmallett uint64_t mod : 3; /**< Internal state */ 734215976Sjmallett#else 735215976Sjmallett uint64_t mod : 3; 736215976Sjmallett uint64_t cnt : 13; 737215976Sjmallett uint64_t chk : 1; 738215976Sjmallett uint64_t len : 1; 739215976Sjmallett uint64_t sop : 1; 740215976Sjmallett uint64_t uid : 3; 741215976Sjmallett uint64_t maj : 1; 742215976Sjmallett uint64_t reserved_23_63 : 41; 743215976Sjmallett#endif 744215976Sjmallett } cn50xx; 745215976Sjmallett struct cvmx_pko_mem_debug11_cn50xx cn52xx; 746215976Sjmallett struct cvmx_pko_mem_debug11_cn50xx cn52xxp1; 747215976Sjmallett struct cvmx_pko_mem_debug11_cn50xx cn56xx; 748215976Sjmallett struct cvmx_pko_mem_debug11_cn50xx cn56xxp1; 749215976Sjmallett struct cvmx_pko_mem_debug11_cn50xx cn58xx; 750215976Sjmallett struct cvmx_pko_mem_debug11_cn50xx cn58xxp1; 751232812Sjmallett struct cvmx_pko_mem_debug11_cn50xx cn61xx; 752215976Sjmallett struct cvmx_pko_mem_debug11_cn50xx cn63xx; 753215976Sjmallett struct cvmx_pko_mem_debug11_cn50xx cn63xxp1; 754232812Sjmallett struct cvmx_pko_mem_debug11_cn50xx cn66xx; 755232812Sjmallett struct cvmx_pko_mem_debug11_cn50xx cn68xx; 756232812Sjmallett struct cvmx_pko_mem_debug11_cn50xx cn68xxp1; 757232812Sjmallett struct cvmx_pko_mem_debug11_cn50xx cnf71xx; 758215976Sjmallett}; 759215976Sjmalletttypedef union cvmx_pko_mem_debug11 cvmx_pko_mem_debug11_t; 760215976Sjmallett 761215976Sjmallett/** 762215976Sjmallett * cvmx_pko_mem_debug12 763215976Sjmallett * 764215976Sjmallett * Notes: 765215976Sjmallett * Internal per-port state intended for debug use only - pko.out.ctl.cmnd[63:0] 766215976Sjmallett * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 767215976Sjmallett * CSR read operations to this address can be performed. 768215976Sjmallett */ 769232812Sjmallettunion cvmx_pko_mem_debug12 { 770215976Sjmallett uint64_t u64; 771232812Sjmallett struct cvmx_pko_mem_debug12_s { 772232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 773215976Sjmallett uint64_t reserved_0_63 : 64; 774215976Sjmallett#else 775215976Sjmallett uint64_t reserved_0_63 : 64; 776215976Sjmallett#endif 777215976Sjmallett } s; 778232812Sjmallett struct cvmx_pko_mem_debug12_cn30xx { 779232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 780215976Sjmallett uint64_t data : 64; /**< WorkQ data or Store0 pointer */ 781215976Sjmallett#else 782215976Sjmallett uint64_t data : 64; 783215976Sjmallett#endif 784215976Sjmallett } cn30xx; 785215976Sjmallett struct cvmx_pko_mem_debug12_cn30xx cn31xx; 786215976Sjmallett struct cvmx_pko_mem_debug12_cn30xx cn38xx; 787215976Sjmallett struct cvmx_pko_mem_debug12_cn30xx cn38xxp2; 788232812Sjmallett struct cvmx_pko_mem_debug12_cn50xx { 789232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 790215976Sjmallett uint64_t fau : 28; /**< Fetch and add command words */ 791215976Sjmallett uint64_t cmd : 14; /**< Command word */ 792215976Sjmallett uint64_t segs : 6; /**< Number of segments/gather size */ 793215976Sjmallett uint64_t size : 16; /**< Packet length in bytes */ 794215976Sjmallett#else 795215976Sjmallett uint64_t size : 16; 796215976Sjmallett uint64_t segs : 6; 797215976Sjmallett uint64_t cmd : 14; 798215976Sjmallett uint64_t fau : 28; 799215976Sjmallett#endif 800215976Sjmallett } cn50xx; 801215976Sjmallett struct cvmx_pko_mem_debug12_cn50xx cn52xx; 802215976Sjmallett struct cvmx_pko_mem_debug12_cn50xx cn52xxp1; 803215976Sjmallett struct cvmx_pko_mem_debug12_cn50xx cn56xx; 804215976Sjmallett struct cvmx_pko_mem_debug12_cn50xx cn56xxp1; 805215976Sjmallett struct cvmx_pko_mem_debug12_cn50xx cn58xx; 806215976Sjmallett struct cvmx_pko_mem_debug12_cn50xx cn58xxp1; 807232812Sjmallett struct cvmx_pko_mem_debug12_cn50xx cn61xx; 808215976Sjmallett struct cvmx_pko_mem_debug12_cn50xx cn63xx; 809215976Sjmallett struct cvmx_pko_mem_debug12_cn50xx cn63xxp1; 810232812Sjmallett struct cvmx_pko_mem_debug12_cn50xx cn66xx; 811232812Sjmallett struct cvmx_pko_mem_debug12_cn68xx { 812232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 813232812Sjmallett uint64_t state : 64; /**< Internal state */ 814232812Sjmallett#else 815232812Sjmallett uint64_t state : 64; 816232812Sjmallett#endif 817232812Sjmallett } cn68xx; 818232812Sjmallett struct cvmx_pko_mem_debug12_cn68xx cn68xxp1; 819232812Sjmallett struct cvmx_pko_mem_debug12_cn50xx cnf71xx; 820215976Sjmallett}; 821215976Sjmalletttypedef union cvmx_pko_mem_debug12 cvmx_pko_mem_debug12_t; 822215976Sjmallett 823215976Sjmallett/** 824215976Sjmallett * cvmx_pko_mem_debug13 825215976Sjmallett * 826215976Sjmallett * Notes: 827215976Sjmallett * Internal per-port state intended for debug use only - pko.out.ctl.head[63:0] 828215976Sjmallett * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 829215976Sjmallett * CSR read operations to this address can be performed. 830215976Sjmallett */ 831232812Sjmallettunion cvmx_pko_mem_debug13 { 832215976Sjmallett uint64_t u64; 833232812Sjmallett struct cvmx_pko_mem_debug13_s { 834232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 835232812Sjmallett uint64_t reserved_0_63 : 64; 836215976Sjmallett#else 837232812Sjmallett uint64_t reserved_0_63 : 64; 838215976Sjmallett#endif 839215976Sjmallett } s; 840232812Sjmallett struct cvmx_pko_mem_debug13_cn30xx { 841232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 842215976Sjmallett uint64_t reserved_51_63 : 13; 843215976Sjmallett uint64_t widx : 17; /**< PDB widx */ 844215976Sjmallett uint64_t ridx2 : 17; /**< PDB ridx2 */ 845215976Sjmallett uint64_t widx2 : 17; /**< PDB widx2 */ 846215976Sjmallett#else 847215976Sjmallett uint64_t widx2 : 17; 848215976Sjmallett uint64_t ridx2 : 17; 849215976Sjmallett uint64_t widx : 17; 850215976Sjmallett uint64_t reserved_51_63 : 13; 851215976Sjmallett#endif 852215976Sjmallett } cn30xx; 853215976Sjmallett struct cvmx_pko_mem_debug13_cn30xx cn31xx; 854215976Sjmallett struct cvmx_pko_mem_debug13_cn30xx cn38xx; 855215976Sjmallett struct cvmx_pko_mem_debug13_cn30xx cn38xxp2; 856232812Sjmallett struct cvmx_pko_mem_debug13_cn50xx { 857232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 858215976Sjmallett uint64_t i : 1; /**< "I" value used for free operation */ 859215976Sjmallett uint64_t back : 4; /**< Back value used for free operation */ 860215976Sjmallett uint64_t pool : 3; /**< Pool value used for free operation */ 861215976Sjmallett uint64_t size : 16; /**< Size in bytes */ 862215976Sjmallett uint64_t ptr : 40; /**< Data pointer */ 863215976Sjmallett#else 864215976Sjmallett uint64_t ptr : 40; 865215976Sjmallett uint64_t size : 16; 866215976Sjmallett uint64_t pool : 3; 867215976Sjmallett uint64_t back : 4; 868215976Sjmallett uint64_t i : 1; 869215976Sjmallett#endif 870215976Sjmallett } cn50xx; 871215976Sjmallett struct cvmx_pko_mem_debug13_cn50xx cn52xx; 872215976Sjmallett struct cvmx_pko_mem_debug13_cn50xx cn52xxp1; 873215976Sjmallett struct cvmx_pko_mem_debug13_cn50xx cn56xx; 874215976Sjmallett struct cvmx_pko_mem_debug13_cn50xx cn56xxp1; 875215976Sjmallett struct cvmx_pko_mem_debug13_cn50xx cn58xx; 876215976Sjmallett struct cvmx_pko_mem_debug13_cn50xx cn58xxp1; 877232812Sjmallett struct cvmx_pko_mem_debug13_cn50xx cn61xx; 878215976Sjmallett struct cvmx_pko_mem_debug13_cn50xx cn63xx; 879215976Sjmallett struct cvmx_pko_mem_debug13_cn50xx cn63xxp1; 880232812Sjmallett struct cvmx_pko_mem_debug13_cn50xx cn66xx; 881232812Sjmallett struct cvmx_pko_mem_debug13_cn68xx { 882232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 883232812Sjmallett uint64_t state : 64; /**< Internal state */ 884232812Sjmallett#else 885232812Sjmallett uint64_t state : 64; 886232812Sjmallett#endif 887232812Sjmallett } cn68xx; 888232812Sjmallett struct cvmx_pko_mem_debug13_cn68xx cn68xxp1; 889232812Sjmallett struct cvmx_pko_mem_debug13_cn50xx cnf71xx; 890215976Sjmallett}; 891215976Sjmalletttypedef union cvmx_pko_mem_debug13 cvmx_pko_mem_debug13_t; 892215976Sjmallett 893215976Sjmallett/** 894215976Sjmallett * cvmx_pko_mem_debug14 895215976Sjmallett * 896215976Sjmallett * Notes: 897215976Sjmallett * Internal per-port state intended for debug use only - pko.prt.psb.save[63:0] 898215976Sjmallett * This CSR is a memory of 132 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 899215976Sjmallett * CSR read operations to this address can be performed. 900215976Sjmallett */ 901232812Sjmallettunion cvmx_pko_mem_debug14 { 902215976Sjmallett uint64_t u64; 903232812Sjmallett struct cvmx_pko_mem_debug14_s { 904232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 905215976Sjmallett uint64_t reserved_0_63 : 64; 906215976Sjmallett#else 907215976Sjmallett uint64_t reserved_0_63 : 64; 908215976Sjmallett#endif 909215976Sjmallett } s; 910232812Sjmallett struct cvmx_pko_mem_debug14_cn30xx { 911232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 912215976Sjmallett uint64_t reserved_17_63 : 47; 913215976Sjmallett uint64_t ridx : 17; /**< PDB ridx */ 914215976Sjmallett#else 915215976Sjmallett uint64_t ridx : 17; 916215976Sjmallett uint64_t reserved_17_63 : 47; 917215976Sjmallett#endif 918215976Sjmallett } cn30xx; 919215976Sjmallett struct cvmx_pko_mem_debug14_cn30xx cn31xx; 920215976Sjmallett struct cvmx_pko_mem_debug14_cn30xx cn38xx; 921215976Sjmallett struct cvmx_pko_mem_debug14_cn30xx cn38xxp2; 922232812Sjmallett struct cvmx_pko_mem_debug14_cn52xx { 923232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 924215976Sjmallett uint64_t data : 64; /**< Command words */ 925215976Sjmallett#else 926215976Sjmallett uint64_t data : 64; 927215976Sjmallett#endif 928215976Sjmallett } cn52xx; 929215976Sjmallett struct cvmx_pko_mem_debug14_cn52xx cn52xxp1; 930215976Sjmallett struct cvmx_pko_mem_debug14_cn52xx cn56xx; 931215976Sjmallett struct cvmx_pko_mem_debug14_cn52xx cn56xxp1; 932232812Sjmallett struct cvmx_pko_mem_debug14_cn52xx cn61xx; 933215976Sjmallett struct cvmx_pko_mem_debug14_cn52xx cn63xx; 934215976Sjmallett struct cvmx_pko_mem_debug14_cn52xx cn63xxp1; 935232812Sjmallett struct cvmx_pko_mem_debug14_cn52xx cn66xx; 936232812Sjmallett struct cvmx_pko_mem_debug14_cn52xx cnf71xx; 937215976Sjmallett}; 938215976Sjmalletttypedef union cvmx_pko_mem_debug14 cvmx_pko_mem_debug14_t; 939215976Sjmallett 940215976Sjmallett/** 941215976Sjmallett * cvmx_pko_mem_debug2 942215976Sjmallett * 943215976Sjmallett * Notes: 944215976Sjmallett * Internal per-port state intended for debug use only - pko_prt_psb.head[63:0] 945215976Sjmallett * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 946215976Sjmallett * CSR read operations to this address can be performed. 947215976Sjmallett */ 948232812Sjmallettunion cvmx_pko_mem_debug2 { 949215976Sjmallett uint64_t u64; 950232812Sjmallett struct cvmx_pko_mem_debug2_s { 951232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 952215976Sjmallett uint64_t i : 1; /**< "I" value used for free operation */ 953215976Sjmallett uint64_t back : 4; /**< Back value used for free operation */ 954215976Sjmallett uint64_t pool : 3; /**< Pool value used for free operation */ 955215976Sjmallett uint64_t size : 16; /**< Size in bytes */ 956215976Sjmallett uint64_t ptr : 40; /**< Data pointer */ 957215976Sjmallett#else 958215976Sjmallett uint64_t ptr : 40; 959215976Sjmallett uint64_t size : 16; 960215976Sjmallett uint64_t pool : 3; 961215976Sjmallett uint64_t back : 4; 962215976Sjmallett uint64_t i : 1; 963215976Sjmallett#endif 964215976Sjmallett } s; 965215976Sjmallett struct cvmx_pko_mem_debug2_s cn30xx; 966215976Sjmallett struct cvmx_pko_mem_debug2_s cn31xx; 967215976Sjmallett struct cvmx_pko_mem_debug2_s cn38xx; 968215976Sjmallett struct cvmx_pko_mem_debug2_s cn38xxp2; 969215976Sjmallett struct cvmx_pko_mem_debug2_s cn50xx; 970215976Sjmallett struct cvmx_pko_mem_debug2_s cn52xx; 971215976Sjmallett struct cvmx_pko_mem_debug2_s cn52xxp1; 972215976Sjmallett struct cvmx_pko_mem_debug2_s cn56xx; 973215976Sjmallett struct cvmx_pko_mem_debug2_s cn56xxp1; 974215976Sjmallett struct cvmx_pko_mem_debug2_s cn58xx; 975215976Sjmallett struct cvmx_pko_mem_debug2_s cn58xxp1; 976232812Sjmallett struct cvmx_pko_mem_debug2_s cn61xx; 977215976Sjmallett struct cvmx_pko_mem_debug2_s cn63xx; 978215976Sjmallett struct cvmx_pko_mem_debug2_s cn63xxp1; 979232812Sjmallett struct cvmx_pko_mem_debug2_s cn66xx; 980232812Sjmallett struct cvmx_pko_mem_debug2_s cn68xx; 981232812Sjmallett struct cvmx_pko_mem_debug2_s cn68xxp1; 982232812Sjmallett struct cvmx_pko_mem_debug2_s cnf71xx; 983215976Sjmallett}; 984215976Sjmalletttypedef union cvmx_pko_mem_debug2 cvmx_pko_mem_debug2_t; 985215976Sjmallett 986215976Sjmallett/** 987215976Sjmallett * cvmx_pko_mem_debug3 988215976Sjmallett * 989215976Sjmallett * Notes: 990215976Sjmallett * Internal per-port state intended for debug use only - pko_prt_psb.resp[63:0] 991215976Sjmallett * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 992215976Sjmallett * CSR read operations to this address can be performed. 993215976Sjmallett */ 994232812Sjmallettunion cvmx_pko_mem_debug3 { 995215976Sjmallett uint64_t u64; 996232812Sjmallett struct cvmx_pko_mem_debug3_s { 997232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 998215976Sjmallett uint64_t reserved_0_63 : 64; 999215976Sjmallett#else 1000215976Sjmallett uint64_t reserved_0_63 : 64; 1001215976Sjmallett#endif 1002215976Sjmallett } s; 1003232812Sjmallett struct cvmx_pko_mem_debug3_cn30xx { 1004232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1005215976Sjmallett uint64_t i : 1; /**< "I" value used for free operation */ 1006215976Sjmallett uint64_t back : 4; /**< Back value used for free operation */ 1007215976Sjmallett uint64_t pool : 3; /**< Pool value used for free operation */ 1008215976Sjmallett uint64_t size : 16; /**< Size in bytes */ 1009215976Sjmallett uint64_t ptr : 40; /**< Data pointer */ 1010215976Sjmallett#else 1011215976Sjmallett uint64_t ptr : 40; 1012215976Sjmallett uint64_t size : 16; 1013215976Sjmallett uint64_t pool : 3; 1014215976Sjmallett uint64_t back : 4; 1015215976Sjmallett uint64_t i : 1; 1016215976Sjmallett#endif 1017215976Sjmallett } cn30xx; 1018215976Sjmallett struct cvmx_pko_mem_debug3_cn30xx cn31xx; 1019215976Sjmallett struct cvmx_pko_mem_debug3_cn30xx cn38xx; 1020215976Sjmallett struct cvmx_pko_mem_debug3_cn30xx cn38xxp2; 1021232812Sjmallett struct cvmx_pko_mem_debug3_cn50xx { 1022232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1023215976Sjmallett uint64_t data : 64; /**< WorkQ data or Store0 pointer */ 1024215976Sjmallett#else 1025215976Sjmallett uint64_t data : 64; 1026215976Sjmallett#endif 1027215976Sjmallett } cn50xx; 1028215976Sjmallett struct cvmx_pko_mem_debug3_cn50xx cn52xx; 1029215976Sjmallett struct cvmx_pko_mem_debug3_cn50xx cn52xxp1; 1030215976Sjmallett struct cvmx_pko_mem_debug3_cn50xx cn56xx; 1031215976Sjmallett struct cvmx_pko_mem_debug3_cn50xx cn56xxp1; 1032215976Sjmallett struct cvmx_pko_mem_debug3_cn50xx cn58xx; 1033215976Sjmallett struct cvmx_pko_mem_debug3_cn50xx cn58xxp1; 1034232812Sjmallett struct cvmx_pko_mem_debug3_cn50xx cn61xx; 1035215976Sjmallett struct cvmx_pko_mem_debug3_cn50xx cn63xx; 1036215976Sjmallett struct cvmx_pko_mem_debug3_cn50xx cn63xxp1; 1037232812Sjmallett struct cvmx_pko_mem_debug3_cn50xx cn66xx; 1038232812Sjmallett struct cvmx_pko_mem_debug3_cn50xx cn68xx; 1039232812Sjmallett struct cvmx_pko_mem_debug3_cn50xx cn68xxp1; 1040232812Sjmallett struct cvmx_pko_mem_debug3_cn50xx cnf71xx; 1041215976Sjmallett}; 1042215976Sjmalletttypedef union cvmx_pko_mem_debug3 cvmx_pko_mem_debug3_t; 1043215976Sjmallett 1044215976Sjmallett/** 1045215976Sjmallett * cvmx_pko_mem_debug4 1046215976Sjmallett * 1047215976Sjmallett * Notes: 1048215976Sjmallett * Internal per-port state intended for debug use only - pko_prt_psb.state[63:0] 1049215976Sjmallett * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1050215976Sjmallett * CSR read operations to this address can be performed. 1051215976Sjmallett */ 1052232812Sjmallettunion cvmx_pko_mem_debug4 { 1053215976Sjmallett uint64_t u64; 1054232812Sjmallett struct cvmx_pko_mem_debug4_s { 1055232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1056215976Sjmallett uint64_t reserved_0_63 : 64; 1057215976Sjmallett#else 1058215976Sjmallett uint64_t reserved_0_63 : 64; 1059215976Sjmallett#endif 1060215976Sjmallett } s; 1061232812Sjmallett struct cvmx_pko_mem_debug4_cn30xx { 1062232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1063215976Sjmallett uint64_t data : 64; /**< WorkQ data or Store0 pointer */ 1064215976Sjmallett#else 1065215976Sjmallett uint64_t data : 64; 1066215976Sjmallett#endif 1067215976Sjmallett } cn30xx; 1068215976Sjmallett struct cvmx_pko_mem_debug4_cn30xx cn31xx; 1069215976Sjmallett struct cvmx_pko_mem_debug4_cn30xx cn38xx; 1070215976Sjmallett struct cvmx_pko_mem_debug4_cn30xx cn38xxp2; 1071232812Sjmallett struct cvmx_pko_mem_debug4_cn50xx { 1072232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1073215976Sjmallett uint64_t cmnd_segs : 3; /**< Internal state */ 1074215976Sjmallett uint64_t cmnd_siz : 16; /**< Internal state */ 1075215976Sjmallett uint64_t cmnd_off : 6; /**< Internal state */ 1076215976Sjmallett uint64_t uid : 3; /**< Internal state */ 1077215976Sjmallett uint64_t dread_sop : 1; /**< Internal state */ 1078215976Sjmallett uint64_t init_dwrite : 1; /**< Internal state */ 1079215976Sjmallett uint64_t chk_once : 1; /**< Internal state */ 1080215976Sjmallett uint64_t chk_mode : 1; /**< Internal state */ 1081215976Sjmallett uint64_t active : 1; /**< Internal state */ 1082215976Sjmallett uint64_t static_p : 1; /**< Internal state */ 1083215976Sjmallett uint64_t qos : 3; /**< Internal state */ 1084215976Sjmallett uint64_t qcb_ridx : 5; /**< Internal state */ 1085215976Sjmallett uint64_t qid_off_max : 4; /**< Internal state */ 1086215976Sjmallett uint64_t qid_off : 4; /**< Internal state */ 1087215976Sjmallett uint64_t qid_base : 8; /**< Internal state */ 1088215976Sjmallett uint64_t wait : 1; /**< Internal state */ 1089215976Sjmallett uint64_t minor : 2; /**< Internal state */ 1090215976Sjmallett uint64_t major : 3; /**< Internal state */ 1091215976Sjmallett#else 1092215976Sjmallett uint64_t major : 3; 1093215976Sjmallett uint64_t minor : 2; 1094215976Sjmallett uint64_t wait : 1; 1095215976Sjmallett uint64_t qid_base : 8; 1096215976Sjmallett uint64_t qid_off : 4; 1097215976Sjmallett uint64_t qid_off_max : 4; 1098215976Sjmallett uint64_t qcb_ridx : 5; 1099215976Sjmallett uint64_t qos : 3; 1100215976Sjmallett uint64_t static_p : 1; 1101215976Sjmallett uint64_t active : 1; 1102215976Sjmallett uint64_t chk_mode : 1; 1103215976Sjmallett uint64_t chk_once : 1; 1104215976Sjmallett uint64_t init_dwrite : 1; 1105215976Sjmallett uint64_t dread_sop : 1; 1106215976Sjmallett uint64_t uid : 3; 1107215976Sjmallett uint64_t cmnd_off : 6; 1108215976Sjmallett uint64_t cmnd_siz : 16; 1109215976Sjmallett uint64_t cmnd_segs : 3; 1110215976Sjmallett#endif 1111215976Sjmallett } cn50xx; 1112232812Sjmallett struct cvmx_pko_mem_debug4_cn52xx { 1113232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1114215976Sjmallett uint64_t curr_siz : 8; /**< Internal state */ 1115215976Sjmallett uint64_t curr_off : 16; /**< Internal state */ 1116215976Sjmallett uint64_t cmnd_segs : 6; /**< Internal state */ 1117215976Sjmallett uint64_t cmnd_siz : 16; /**< Internal state */ 1118215976Sjmallett uint64_t cmnd_off : 6; /**< Internal state */ 1119215976Sjmallett uint64_t uid : 2; /**< Internal state */ 1120215976Sjmallett uint64_t dread_sop : 1; /**< Internal state */ 1121215976Sjmallett uint64_t init_dwrite : 1; /**< Internal state */ 1122215976Sjmallett uint64_t chk_once : 1; /**< Internal state */ 1123215976Sjmallett uint64_t chk_mode : 1; /**< Internal state */ 1124215976Sjmallett uint64_t wait : 1; /**< Internal state */ 1125215976Sjmallett uint64_t minor : 2; /**< Internal state */ 1126215976Sjmallett uint64_t major : 3; /**< Internal state */ 1127215976Sjmallett#else 1128215976Sjmallett uint64_t major : 3; 1129215976Sjmallett uint64_t minor : 2; 1130215976Sjmallett uint64_t wait : 1; 1131215976Sjmallett uint64_t chk_mode : 1; 1132215976Sjmallett uint64_t chk_once : 1; 1133215976Sjmallett uint64_t init_dwrite : 1; 1134215976Sjmallett uint64_t dread_sop : 1; 1135215976Sjmallett uint64_t uid : 2; 1136215976Sjmallett uint64_t cmnd_off : 6; 1137215976Sjmallett uint64_t cmnd_siz : 16; 1138215976Sjmallett uint64_t cmnd_segs : 6; 1139215976Sjmallett uint64_t curr_off : 16; 1140215976Sjmallett uint64_t curr_siz : 8; 1141215976Sjmallett#endif 1142215976Sjmallett } cn52xx; 1143215976Sjmallett struct cvmx_pko_mem_debug4_cn52xx cn52xxp1; 1144215976Sjmallett struct cvmx_pko_mem_debug4_cn52xx cn56xx; 1145215976Sjmallett struct cvmx_pko_mem_debug4_cn52xx cn56xxp1; 1146215976Sjmallett struct cvmx_pko_mem_debug4_cn50xx cn58xx; 1147215976Sjmallett struct cvmx_pko_mem_debug4_cn50xx cn58xxp1; 1148232812Sjmallett struct cvmx_pko_mem_debug4_cn52xx cn61xx; 1149215976Sjmallett struct cvmx_pko_mem_debug4_cn52xx cn63xx; 1150215976Sjmallett struct cvmx_pko_mem_debug4_cn52xx cn63xxp1; 1151232812Sjmallett struct cvmx_pko_mem_debug4_cn52xx cn66xx; 1152232812Sjmallett struct cvmx_pko_mem_debug4_cn52xx cn68xx; 1153232812Sjmallett struct cvmx_pko_mem_debug4_cn52xx cn68xxp1; 1154232812Sjmallett struct cvmx_pko_mem_debug4_cn52xx cnf71xx; 1155215976Sjmallett}; 1156215976Sjmalletttypedef union cvmx_pko_mem_debug4 cvmx_pko_mem_debug4_t; 1157215976Sjmallett 1158215976Sjmallett/** 1159215976Sjmallett * cvmx_pko_mem_debug5 1160215976Sjmallett * 1161215976Sjmallett * Notes: 1162215976Sjmallett * Internal per-port state intended for debug use only - pko_prt_psb.state[127:64] 1163215976Sjmallett * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1164215976Sjmallett * CSR read operations to this address can be performed. 1165215976Sjmallett */ 1166232812Sjmallettunion cvmx_pko_mem_debug5 { 1167215976Sjmallett uint64_t u64; 1168232812Sjmallett struct cvmx_pko_mem_debug5_s { 1169232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1170215976Sjmallett uint64_t reserved_0_63 : 64; 1171215976Sjmallett#else 1172215976Sjmallett uint64_t reserved_0_63 : 64; 1173215976Sjmallett#endif 1174215976Sjmallett } s; 1175232812Sjmallett struct cvmx_pko_mem_debug5_cn30xx { 1176232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1177215976Sjmallett uint64_t dwri_mod : 1; /**< Dwrite mod */ 1178215976Sjmallett uint64_t dwri_sop : 1; /**< Dwrite sop needed */ 1179215976Sjmallett uint64_t dwri_len : 1; /**< Dwrite len */ 1180215976Sjmallett uint64_t dwri_cnt : 13; /**< Dwrite count */ 1181215976Sjmallett uint64_t cmnd_siz : 16; /**< Copy of cmnd.size */ 1182215976Sjmallett uint64_t uid : 1; /**< UID */ 1183215976Sjmallett uint64_t xfer_wor : 1; /**< Transfer work needed */ 1184215976Sjmallett uint64_t xfer_dwr : 1; /**< Transfer dwrite needed */ 1185215976Sjmallett uint64_t cbuf_fre : 1; /**< Cbuf needs free */ 1186215976Sjmallett uint64_t reserved_27_27 : 1; 1187215976Sjmallett uint64_t chk_mode : 1; /**< Checksum mode */ 1188215976Sjmallett uint64_t active : 1; /**< Port is active */ 1189215976Sjmallett uint64_t qos : 3; /**< Current QOS round */ 1190215976Sjmallett uint64_t qcb_ridx : 5; /**< Buffer read index for QCB */ 1191215976Sjmallett uint64_t qid_off : 3; /**< Offset to be added to QID_BASE for current queue */ 1192215976Sjmallett uint64_t qid_base : 7; /**< Absolute QID of the queue array base = &QUEUES[0] */ 1193215976Sjmallett uint64_t wait : 1; /**< State wait when set */ 1194215976Sjmallett uint64_t minor : 2; /**< State minor code */ 1195215976Sjmallett uint64_t major : 4; /**< State major code */ 1196215976Sjmallett#else 1197215976Sjmallett uint64_t major : 4; 1198215976Sjmallett uint64_t minor : 2; 1199215976Sjmallett uint64_t wait : 1; 1200215976Sjmallett uint64_t qid_base : 7; 1201215976Sjmallett uint64_t qid_off : 3; 1202215976Sjmallett uint64_t qcb_ridx : 5; 1203215976Sjmallett uint64_t qos : 3; 1204215976Sjmallett uint64_t active : 1; 1205215976Sjmallett uint64_t chk_mode : 1; 1206215976Sjmallett uint64_t reserved_27_27 : 1; 1207215976Sjmallett uint64_t cbuf_fre : 1; 1208215976Sjmallett uint64_t xfer_dwr : 1; 1209215976Sjmallett uint64_t xfer_wor : 1; 1210215976Sjmallett uint64_t uid : 1; 1211215976Sjmallett uint64_t cmnd_siz : 16; 1212215976Sjmallett uint64_t dwri_cnt : 13; 1213215976Sjmallett uint64_t dwri_len : 1; 1214215976Sjmallett uint64_t dwri_sop : 1; 1215215976Sjmallett uint64_t dwri_mod : 1; 1216215976Sjmallett#endif 1217215976Sjmallett } cn30xx; 1218215976Sjmallett struct cvmx_pko_mem_debug5_cn30xx cn31xx; 1219215976Sjmallett struct cvmx_pko_mem_debug5_cn30xx cn38xx; 1220215976Sjmallett struct cvmx_pko_mem_debug5_cn30xx cn38xxp2; 1221232812Sjmallett struct cvmx_pko_mem_debug5_cn50xx { 1222232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1223215976Sjmallett uint64_t curr_ptr : 29; /**< Internal state */ 1224215976Sjmallett uint64_t curr_siz : 16; /**< Internal state */ 1225215976Sjmallett uint64_t curr_off : 16; /**< Internal state */ 1226215976Sjmallett uint64_t cmnd_segs : 3; /**< Internal state */ 1227215976Sjmallett#else 1228215976Sjmallett uint64_t cmnd_segs : 3; 1229215976Sjmallett uint64_t curr_off : 16; 1230215976Sjmallett uint64_t curr_siz : 16; 1231215976Sjmallett uint64_t curr_ptr : 29; 1232215976Sjmallett#endif 1233215976Sjmallett } cn50xx; 1234232812Sjmallett struct cvmx_pko_mem_debug5_cn52xx { 1235232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1236215976Sjmallett uint64_t reserved_54_63 : 10; 1237215976Sjmallett uint64_t nxt_inflt : 6; /**< Internal state */ 1238215976Sjmallett uint64_t curr_ptr : 40; /**< Internal state */ 1239215976Sjmallett uint64_t curr_siz : 8; /**< Internal state */ 1240215976Sjmallett#else 1241215976Sjmallett uint64_t curr_siz : 8; 1242215976Sjmallett uint64_t curr_ptr : 40; 1243215976Sjmallett uint64_t nxt_inflt : 6; 1244215976Sjmallett uint64_t reserved_54_63 : 10; 1245215976Sjmallett#endif 1246215976Sjmallett } cn52xx; 1247215976Sjmallett struct cvmx_pko_mem_debug5_cn52xx cn52xxp1; 1248215976Sjmallett struct cvmx_pko_mem_debug5_cn52xx cn56xx; 1249215976Sjmallett struct cvmx_pko_mem_debug5_cn52xx cn56xxp1; 1250215976Sjmallett struct cvmx_pko_mem_debug5_cn50xx cn58xx; 1251215976Sjmallett struct cvmx_pko_mem_debug5_cn50xx cn58xxp1; 1252232812Sjmallett struct cvmx_pko_mem_debug5_cn61xx { 1253232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1254215976Sjmallett uint64_t reserved_56_63 : 8; 1255215976Sjmallett uint64_t ptp : 1; /**< Internal state */ 1256215976Sjmallett uint64_t major_3 : 1; /**< Internal state */ 1257215976Sjmallett uint64_t nxt_inflt : 6; /**< Internal state */ 1258215976Sjmallett uint64_t curr_ptr : 40; /**< Internal state */ 1259215976Sjmallett uint64_t curr_siz : 8; /**< Internal state */ 1260215976Sjmallett#else 1261215976Sjmallett uint64_t curr_siz : 8; 1262215976Sjmallett uint64_t curr_ptr : 40; 1263215976Sjmallett uint64_t nxt_inflt : 6; 1264215976Sjmallett uint64_t major_3 : 1; 1265215976Sjmallett uint64_t ptp : 1; 1266215976Sjmallett uint64_t reserved_56_63 : 8; 1267215976Sjmallett#endif 1268232812Sjmallett } cn61xx; 1269232812Sjmallett struct cvmx_pko_mem_debug5_cn61xx cn63xx; 1270232812Sjmallett struct cvmx_pko_mem_debug5_cn61xx cn63xxp1; 1271232812Sjmallett struct cvmx_pko_mem_debug5_cn61xx cn66xx; 1272232812Sjmallett struct cvmx_pko_mem_debug5_cn68xx { 1273232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1274232812Sjmallett uint64_t reserved_57_63 : 7; 1275232812Sjmallett uint64_t uid_2 : 1; /**< Internal state */ 1276232812Sjmallett uint64_t ptp : 1; /**< Internal state */ 1277232812Sjmallett uint64_t major_3 : 1; /**< Internal state */ 1278232812Sjmallett uint64_t nxt_inflt : 6; /**< Internal state */ 1279232812Sjmallett uint64_t curr_ptr : 40; /**< Internal state */ 1280232812Sjmallett uint64_t curr_siz : 8; /**< Internal state */ 1281232812Sjmallett#else 1282232812Sjmallett uint64_t curr_siz : 8; 1283232812Sjmallett uint64_t curr_ptr : 40; 1284232812Sjmallett uint64_t nxt_inflt : 6; 1285232812Sjmallett uint64_t major_3 : 1; 1286232812Sjmallett uint64_t ptp : 1; 1287232812Sjmallett uint64_t uid_2 : 1; 1288232812Sjmallett uint64_t reserved_57_63 : 7; 1289232812Sjmallett#endif 1290232812Sjmallett } cn68xx; 1291232812Sjmallett struct cvmx_pko_mem_debug5_cn68xx cn68xxp1; 1292232812Sjmallett struct cvmx_pko_mem_debug5_cn61xx cnf71xx; 1293215976Sjmallett}; 1294215976Sjmalletttypedef union cvmx_pko_mem_debug5 cvmx_pko_mem_debug5_t; 1295215976Sjmallett 1296215976Sjmallett/** 1297215976Sjmallett * cvmx_pko_mem_debug6 1298215976Sjmallett * 1299215976Sjmallett * Notes: 1300215976Sjmallett * Internal per-port state intended for debug use only - pko_prt_psb.port[63:0] 1301215976Sjmallett * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1302215976Sjmallett * CSR read operations to this address can be performed. 1303215976Sjmallett */ 1304232812Sjmallettunion cvmx_pko_mem_debug6 { 1305215976Sjmallett uint64_t u64; 1306232812Sjmallett struct cvmx_pko_mem_debug6_s { 1307232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1308215976Sjmallett uint64_t reserved_37_63 : 27; 1309215976Sjmallett uint64_t qid_offres : 4; /**< Internal state */ 1310215976Sjmallett uint64_t qid_offths : 4; /**< Internal state */ 1311215976Sjmallett uint64_t preempter : 1; /**< Internal state */ 1312215976Sjmallett uint64_t preemptee : 1; /**< Internal state */ 1313215976Sjmallett uint64_t preempted : 1; /**< Internal state */ 1314215976Sjmallett uint64_t active : 1; /**< Internal state */ 1315215976Sjmallett uint64_t statc : 1; /**< Internal state */ 1316215976Sjmallett uint64_t qos : 3; /**< Internal state */ 1317215976Sjmallett uint64_t qcb_ridx : 5; /**< Internal state */ 1318215976Sjmallett uint64_t qid_offmax : 4; /**< Internal state */ 1319215976Sjmallett uint64_t reserved_0_11 : 12; 1320215976Sjmallett#else 1321215976Sjmallett uint64_t reserved_0_11 : 12; 1322215976Sjmallett uint64_t qid_offmax : 4; 1323215976Sjmallett uint64_t qcb_ridx : 5; 1324215976Sjmallett uint64_t qos : 3; 1325215976Sjmallett uint64_t statc : 1; 1326215976Sjmallett uint64_t active : 1; 1327215976Sjmallett uint64_t preempted : 1; 1328215976Sjmallett uint64_t preemptee : 1; 1329215976Sjmallett uint64_t preempter : 1; 1330215976Sjmallett uint64_t qid_offths : 4; 1331215976Sjmallett uint64_t qid_offres : 4; 1332215976Sjmallett uint64_t reserved_37_63 : 27; 1333215976Sjmallett#endif 1334215976Sjmallett } s; 1335232812Sjmallett struct cvmx_pko_mem_debug6_cn30xx { 1336232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1337215976Sjmallett uint64_t reserved_11_63 : 53; 1338215976Sjmallett uint64_t qid_offm : 3; /**< Qid offset max */ 1339215976Sjmallett uint64_t static_p : 1; /**< Static port when set */ 1340215976Sjmallett uint64_t work_min : 3; /**< Work minor */ 1341215976Sjmallett uint64_t dwri_chk : 1; /**< Dwrite checksum mode */ 1342215976Sjmallett uint64_t dwri_uid : 1; /**< Dwrite UID */ 1343215976Sjmallett uint64_t dwri_mod : 2; /**< Dwrite mod */ 1344215976Sjmallett#else 1345215976Sjmallett uint64_t dwri_mod : 2; 1346215976Sjmallett uint64_t dwri_uid : 1; 1347215976Sjmallett uint64_t dwri_chk : 1; 1348215976Sjmallett uint64_t work_min : 3; 1349215976Sjmallett uint64_t static_p : 1; 1350215976Sjmallett uint64_t qid_offm : 3; 1351215976Sjmallett uint64_t reserved_11_63 : 53; 1352215976Sjmallett#endif 1353215976Sjmallett } cn30xx; 1354215976Sjmallett struct cvmx_pko_mem_debug6_cn30xx cn31xx; 1355215976Sjmallett struct cvmx_pko_mem_debug6_cn30xx cn38xx; 1356215976Sjmallett struct cvmx_pko_mem_debug6_cn30xx cn38xxp2; 1357232812Sjmallett struct cvmx_pko_mem_debug6_cn50xx { 1358232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1359215976Sjmallett uint64_t reserved_11_63 : 53; 1360215976Sjmallett uint64_t curr_ptr : 11; /**< Internal state */ 1361215976Sjmallett#else 1362215976Sjmallett uint64_t curr_ptr : 11; 1363215976Sjmallett uint64_t reserved_11_63 : 53; 1364215976Sjmallett#endif 1365215976Sjmallett } cn50xx; 1366232812Sjmallett struct cvmx_pko_mem_debug6_cn52xx { 1367232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1368215976Sjmallett uint64_t reserved_37_63 : 27; 1369215976Sjmallett uint64_t qid_offres : 4; /**< Internal state */ 1370215976Sjmallett uint64_t qid_offths : 4; /**< Internal state */ 1371215976Sjmallett uint64_t preempter : 1; /**< Internal state */ 1372215976Sjmallett uint64_t preemptee : 1; /**< Internal state */ 1373215976Sjmallett uint64_t preempted : 1; /**< Internal state */ 1374215976Sjmallett uint64_t active : 1; /**< Internal state */ 1375215976Sjmallett uint64_t statc : 1; /**< Internal state */ 1376215976Sjmallett uint64_t qos : 3; /**< Internal state */ 1377215976Sjmallett uint64_t qcb_ridx : 5; /**< Internal state */ 1378215976Sjmallett uint64_t qid_offmax : 4; /**< Internal state */ 1379215976Sjmallett uint64_t qid_off : 4; /**< Internal state */ 1380215976Sjmallett uint64_t qid_base : 8; /**< Internal state */ 1381215976Sjmallett#else 1382215976Sjmallett uint64_t qid_base : 8; 1383215976Sjmallett uint64_t qid_off : 4; 1384215976Sjmallett uint64_t qid_offmax : 4; 1385215976Sjmallett uint64_t qcb_ridx : 5; 1386215976Sjmallett uint64_t qos : 3; 1387215976Sjmallett uint64_t statc : 1; 1388215976Sjmallett uint64_t active : 1; 1389215976Sjmallett uint64_t preempted : 1; 1390215976Sjmallett uint64_t preemptee : 1; 1391215976Sjmallett uint64_t preempter : 1; 1392215976Sjmallett uint64_t qid_offths : 4; 1393215976Sjmallett uint64_t qid_offres : 4; 1394215976Sjmallett uint64_t reserved_37_63 : 27; 1395215976Sjmallett#endif 1396215976Sjmallett } cn52xx; 1397215976Sjmallett struct cvmx_pko_mem_debug6_cn52xx cn52xxp1; 1398215976Sjmallett struct cvmx_pko_mem_debug6_cn52xx cn56xx; 1399215976Sjmallett struct cvmx_pko_mem_debug6_cn52xx cn56xxp1; 1400215976Sjmallett struct cvmx_pko_mem_debug6_cn50xx cn58xx; 1401215976Sjmallett struct cvmx_pko_mem_debug6_cn50xx cn58xxp1; 1402232812Sjmallett struct cvmx_pko_mem_debug6_cn52xx cn61xx; 1403215976Sjmallett struct cvmx_pko_mem_debug6_cn52xx cn63xx; 1404215976Sjmallett struct cvmx_pko_mem_debug6_cn52xx cn63xxp1; 1405232812Sjmallett struct cvmx_pko_mem_debug6_cn52xx cn66xx; 1406232812Sjmallett struct cvmx_pko_mem_debug6_cn52xx cn68xx; 1407232812Sjmallett struct cvmx_pko_mem_debug6_cn52xx cn68xxp1; 1408232812Sjmallett struct cvmx_pko_mem_debug6_cn52xx cnf71xx; 1409215976Sjmallett}; 1410215976Sjmalletttypedef union cvmx_pko_mem_debug6 cvmx_pko_mem_debug6_t; 1411215976Sjmallett 1412215976Sjmallett/** 1413215976Sjmallett * cvmx_pko_mem_debug7 1414215976Sjmallett * 1415215976Sjmallett * Notes: 1416215976Sjmallett * Internal per-queue state intended for debug use only - pko_prt_qsb.state[63:0] 1417215976Sjmallett * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1418215976Sjmallett * CSR read operations to this address can be performed. 1419215976Sjmallett */ 1420232812Sjmallettunion cvmx_pko_mem_debug7 { 1421215976Sjmallett uint64_t u64; 1422232812Sjmallett struct cvmx_pko_mem_debug7_s { 1423232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1424232812Sjmallett uint64_t reserved_0_63 : 64; 1425215976Sjmallett#else 1426232812Sjmallett uint64_t reserved_0_63 : 64; 1427215976Sjmallett#endif 1428215976Sjmallett } s; 1429232812Sjmallett struct cvmx_pko_mem_debug7_cn30xx { 1430232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1431215976Sjmallett uint64_t reserved_58_63 : 6; 1432215976Sjmallett uint64_t dwb : 9; /**< Calculated DWB count used for free operation */ 1433215976Sjmallett uint64_t start : 33; /**< Calculated start address used for free operation */ 1434215976Sjmallett uint64_t size : 16; /**< Packet length in bytes */ 1435215976Sjmallett#else 1436215976Sjmallett uint64_t size : 16; 1437215976Sjmallett uint64_t start : 33; 1438215976Sjmallett uint64_t dwb : 9; 1439215976Sjmallett uint64_t reserved_58_63 : 6; 1440215976Sjmallett#endif 1441215976Sjmallett } cn30xx; 1442215976Sjmallett struct cvmx_pko_mem_debug7_cn30xx cn31xx; 1443215976Sjmallett struct cvmx_pko_mem_debug7_cn30xx cn38xx; 1444215976Sjmallett struct cvmx_pko_mem_debug7_cn30xx cn38xxp2; 1445232812Sjmallett struct cvmx_pko_mem_debug7_cn50xx { 1446232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1447215976Sjmallett uint64_t qos : 5; /**< QOS mask to enable the queue when set */ 1448215976Sjmallett uint64_t tail : 1; /**< This queue is the last (tail) in the queue array */ 1449215976Sjmallett uint64_t buf_siz : 13; /**< Command buffer remaining size in words */ 1450215976Sjmallett uint64_t buf_ptr : 33; /**< Command word pointer */ 1451215976Sjmallett uint64_t qcb_widx : 6; /**< Buffer write index for QCB */ 1452215976Sjmallett uint64_t qcb_ridx : 6; /**< Buffer read index for QCB */ 1453215976Sjmallett#else 1454215976Sjmallett uint64_t qcb_ridx : 6; 1455215976Sjmallett uint64_t qcb_widx : 6; 1456215976Sjmallett uint64_t buf_ptr : 33; 1457215976Sjmallett uint64_t buf_siz : 13; 1458215976Sjmallett uint64_t tail : 1; 1459215976Sjmallett uint64_t qos : 5; 1460215976Sjmallett#endif 1461215976Sjmallett } cn50xx; 1462215976Sjmallett struct cvmx_pko_mem_debug7_cn50xx cn52xx; 1463215976Sjmallett struct cvmx_pko_mem_debug7_cn50xx cn52xxp1; 1464215976Sjmallett struct cvmx_pko_mem_debug7_cn50xx cn56xx; 1465215976Sjmallett struct cvmx_pko_mem_debug7_cn50xx cn56xxp1; 1466215976Sjmallett struct cvmx_pko_mem_debug7_cn50xx cn58xx; 1467215976Sjmallett struct cvmx_pko_mem_debug7_cn50xx cn58xxp1; 1468232812Sjmallett struct cvmx_pko_mem_debug7_cn50xx cn61xx; 1469215976Sjmallett struct cvmx_pko_mem_debug7_cn50xx cn63xx; 1470215976Sjmallett struct cvmx_pko_mem_debug7_cn50xx cn63xxp1; 1471232812Sjmallett struct cvmx_pko_mem_debug7_cn50xx cn66xx; 1472232812Sjmallett struct cvmx_pko_mem_debug7_cn68xx { 1473232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1474232812Sjmallett uint64_t qos : 3; /**< QOS mask to enable the queue when set */ 1475232812Sjmallett uint64_t tail : 1; /**< This queue is the last (tail) in the queue array */ 1476232812Sjmallett uint64_t buf_siz : 13; /**< Command buffer remaining size in words */ 1477232812Sjmallett uint64_t buf_ptr : 33; /**< Command word pointer */ 1478232812Sjmallett uint64_t qcb_widx : 7; /**< Buffer write index for QCB */ 1479232812Sjmallett uint64_t qcb_ridx : 7; /**< Buffer read index for QCB */ 1480232812Sjmallett#else 1481232812Sjmallett uint64_t qcb_ridx : 7; 1482232812Sjmallett uint64_t qcb_widx : 7; 1483232812Sjmallett uint64_t buf_ptr : 33; 1484232812Sjmallett uint64_t buf_siz : 13; 1485232812Sjmallett uint64_t tail : 1; 1486232812Sjmallett uint64_t qos : 3; 1487232812Sjmallett#endif 1488232812Sjmallett } cn68xx; 1489232812Sjmallett struct cvmx_pko_mem_debug7_cn68xx cn68xxp1; 1490232812Sjmallett struct cvmx_pko_mem_debug7_cn50xx cnf71xx; 1491215976Sjmallett}; 1492215976Sjmalletttypedef union cvmx_pko_mem_debug7 cvmx_pko_mem_debug7_t; 1493215976Sjmallett 1494215976Sjmallett/** 1495215976Sjmallett * cvmx_pko_mem_debug8 1496215976Sjmallett * 1497215976Sjmallett * Notes: 1498215976Sjmallett * Internal per-queue state intended for debug use only - pko_prt_qsb.state[91:64] 1499215976Sjmallett * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1500215976Sjmallett * CSR read operations to this address can be performed. 1501215976Sjmallett */ 1502232812Sjmallettunion cvmx_pko_mem_debug8 { 1503215976Sjmallett uint64_t u64; 1504232812Sjmallett struct cvmx_pko_mem_debug8_s { 1505232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1506215976Sjmallett uint64_t reserved_59_63 : 5; 1507215976Sjmallett uint64_t tail : 1; /**< This queue is the last (tail) in the queue array */ 1508215976Sjmallett uint64_t buf_siz : 13; /**< Command buffer remaining size in words */ 1509215976Sjmallett uint64_t reserved_0_44 : 45; 1510215976Sjmallett#else 1511215976Sjmallett uint64_t reserved_0_44 : 45; 1512215976Sjmallett uint64_t buf_siz : 13; 1513215976Sjmallett uint64_t tail : 1; 1514215976Sjmallett uint64_t reserved_59_63 : 5; 1515215976Sjmallett#endif 1516215976Sjmallett } s; 1517232812Sjmallett struct cvmx_pko_mem_debug8_cn30xx { 1518232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1519215976Sjmallett uint64_t qos : 5; /**< QOS mask to enable the queue when set */ 1520215976Sjmallett uint64_t tail : 1; /**< This queue is the last (tail) in the queue array */ 1521215976Sjmallett uint64_t buf_siz : 13; /**< Command buffer remaining size in words */ 1522215976Sjmallett uint64_t buf_ptr : 33; /**< Command word pointer */ 1523215976Sjmallett uint64_t qcb_widx : 6; /**< Buffer write index for QCB */ 1524215976Sjmallett uint64_t qcb_ridx : 6; /**< Buffer read index for QCB */ 1525215976Sjmallett#else 1526215976Sjmallett uint64_t qcb_ridx : 6; 1527215976Sjmallett uint64_t qcb_widx : 6; 1528215976Sjmallett uint64_t buf_ptr : 33; 1529215976Sjmallett uint64_t buf_siz : 13; 1530215976Sjmallett uint64_t tail : 1; 1531215976Sjmallett uint64_t qos : 5; 1532215976Sjmallett#endif 1533215976Sjmallett } cn30xx; 1534215976Sjmallett struct cvmx_pko_mem_debug8_cn30xx cn31xx; 1535215976Sjmallett struct cvmx_pko_mem_debug8_cn30xx cn38xx; 1536215976Sjmallett struct cvmx_pko_mem_debug8_cn30xx cn38xxp2; 1537232812Sjmallett struct cvmx_pko_mem_debug8_cn50xx { 1538232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1539215976Sjmallett uint64_t reserved_28_63 : 36; 1540215976Sjmallett uint64_t doorbell : 20; /**< Doorbell count */ 1541215976Sjmallett uint64_t reserved_6_7 : 2; 1542215976Sjmallett uint64_t static_p : 1; /**< Static priority */ 1543215976Sjmallett uint64_t s_tail : 1; /**< Static tail */ 1544215976Sjmallett uint64_t static_q : 1; /**< Static priority */ 1545215976Sjmallett uint64_t qos : 3; /**< QOS mask to enable the queue when set */ 1546215976Sjmallett#else 1547215976Sjmallett uint64_t qos : 3; 1548215976Sjmallett uint64_t static_q : 1; 1549215976Sjmallett uint64_t s_tail : 1; 1550215976Sjmallett uint64_t static_p : 1; 1551215976Sjmallett uint64_t reserved_6_7 : 2; 1552215976Sjmallett uint64_t doorbell : 20; 1553215976Sjmallett uint64_t reserved_28_63 : 36; 1554215976Sjmallett#endif 1555215976Sjmallett } cn50xx; 1556232812Sjmallett struct cvmx_pko_mem_debug8_cn52xx { 1557232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1558215976Sjmallett uint64_t reserved_29_63 : 35; 1559215976Sjmallett uint64_t preempter : 1; /**< Preempter */ 1560215976Sjmallett uint64_t doorbell : 20; /**< Doorbell count */ 1561215976Sjmallett uint64_t reserved_7_7 : 1; 1562215976Sjmallett uint64_t preemptee : 1; /**< Preemptee */ 1563215976Sjmallett uint64_t static_p : 1; /**< Static priority */ 1564215976Sjmallett uint64_t s_tail : 1; /**< Static tail */ 1565215976Sjmallett uint64_t static_q : 1; /**< Static priority */ 1566215976Sjmallett uint64_t qos : 3; /**< QOS mask to enable the queue when set */ 1567215976Sjmallett#else 1568215976Sjmallett uint64_t qos : 3; 1569215976Sjmallett uint64_t static_q : 1; 1570215976Sjmallett uint64_t s_tail : 1; 1571215976Sjmallett uint64_t static_p : 1; 1572215976Sjmallett uint64_t preemptee : 1; 1573215976Sjmallett uint64_t reserved_7_7 : 1; 1574215976Sjmallett uint64_t doorbell : 20; 1575215976Sjmallett uint64_t preempter : 1; 1576215976Sjmallett uint64_t reserved_29_63 : 35; 1577215976Sjmallett#endif 1578215976Sjmallett } cn52xx; 1579215976Sjmallett struct cvmx_pko_mem_debug8_cn52xx cn52xxp1; 1580215976Sjmallett struct cvmx_pko_mem_debug8_cn52xx cn56xx; 1581215976Sjmallett struct cvmx_pko_mem_debug8_cn52xx cn56xxp1; 1582215976Sjmallett struct cvmx_pko_mem_debug8_cn50xx cn58xx; 1583215976Sjmallett struct cvmx_pko_mem_debug8_cn50xx cn58xxp1; 1584232812Sjmallett struct cvmx_pko_mem_debug8_cn61xx { 1585232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1586232812Sjmallett uint64_t reserved_42_63 : 22; 1587232812Sjmallett uint64_t qid_qqos : 8; /**< QOS_MASK */ 1588232812Sjmallett uint64_t reserved_33_33 : 1; 1589232812Sjmallett uint64_t qid_idx : 4; /**< IDX */ 1590232812Sjmallett uint64_t preempter : 1; /**< Preempter */ 1591232812Sjmallett uint64_t doorbell : 20; /**< Doorbell count */ 1592232812Sjmallett uint64_t reserved_7_7 : 1; 1593232812Sjmallett uint64_t preemptee : 1; /**< Preemptee */ 1594232812Sjmallett uint64_t static_p : 1; /**< Static priority */ 1595232812Sjmallett uint64_t s_tail : 1; /**< Static tail */ 1596232812Sjmallett uint64_t static_q : 1; /**< Static priority */ 1597232812Sjmallett uint64_t qos : 3; /**< QOS mask to enable the queue when set */ 1598232812Sjmallett#else 1599232812Sjmallett uint64_t qos : 3; 1600232812Sjmallett uint64_t static_q : 1; 1601232812Sjmallett uint64_t s_tail : 1; 1602232812Sjmallett uint64_t static_p : 1; 1603232812Sjmallett uint64_t preemptee : 1; 1604232812Sjmallett uint64_t reserved_7_7 : 1; 1605232812Sjmallett uint64_t doorbell : 20; 1606232812Sjmallett uint64_t preempter : 1; 1607232812Sjmallett uint64_t qid_idx : 4; 1608232812Sjmallett uint64_t reserved_33_33 : 1; 1609232812Sjmallett uint64_t qid_qqos : 8; 1610232812Sjmallett uint64_t reserved_42_63 : 22; 1611232812Sjmallett#endif 1612232812Sjmallett } cn61xx; 1613215976Sjmallett struct cvmx_pko_mem_debug8_cn52xx cn63xx; 1614215976Sjmallett struct cvmx_pko_mem_debug8_cn52xx cn63xxp1; 1615232812Sjmallett struct cvmx_pko_mem_debug8_cn61xx cn66xx; 1616232812Sjmallett struct cvmx_pko_mem_debug8_cn68xx { 1617232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1618232812Sjmallett uint64_t reserved_37_63 : 27; 1619232812Sjmallett uint64_t preempter : 1; /**< Preempter */ 1620232812Sjmallett uint64_t doorbell : 20; /**< Doorbell count */ 1621232812Sjmallett uint64_t reserved_9_15 : 7; 1622232812Sjmallett uint64_t preemptee : 1; /**< Preemptee */ 1623232812Sjmallett uint64_t static_p : 1; /**< Static priority */ 1624232812Sjmallett uint64_t s_tail : 1; /**< Static tail */ 1625232812Sjmallett uint64_t static_q : 1; /**< Static priority */ 1626232812Sjmallett uint64_t qos : 5; /**< QOS mask to enable the queue when set */ 1627232812Sjmallett#else 1628232812Sjmallett uint64_t qos : 5; 1629232812Sjmallett uint64_t static_q : 1; 1630232812Sjmallett uint64_t s_tail : 1; 1631232812Sjmallett uint64_t static_p : 1; 1632232812Sjmallett uint64_t preemptee : 1; 1633232812Sjmallett uint64_t reserved_9_15 : 7; 1634232812Sjmallett uint64_t doorbell : 20; 1635232812Sjmallett uint64_t preempter : 1; 1636232812Sjmallett uint64_t reserved_37_63 : 27; 1637232812Sjmallett#endif 1638232812Sjmallett } cn68xx; 1639232812Sjmallett struct cvmx_pko_mem_debug8_cn68xx cn68xxp1; 1640232812Sjmallett struct cvmx_pko_mem_debug8_cn61xx cnf71xx; 1641215976Sjmallett}; 1642215976Sjmalletttypedef union cvmx_pko_mem_debug8 cvmx_pko_mem_debug8_t; 1643215976Sjmallett 1644215976Sjmallett/** 1645215976Sjmallett * cvmx_pko_mem_debug9 1646215976Sjmallett * 1647215976Sjmallett * Notes: 1648215976Sjmallett * Internal per-port state intended for debug use only - pko.dat.ptr.ptrs0, pko.dat.ptr.ptrs3 1649215976Sjmallett * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1650215976Sjmallett * CSR read operations to this address can be performed. 1651215976Sjmallett */ 1652232812Sjmallettunion cvmx_pko_mem_debug9 { 1653215976Sjmallett uint64_t u64; 1654232812Sjmallett struct cvmx_pko_mem_debug9_s { 1655232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1656215976Sjmallett uint64_t reserved_49_63 : 15; 1657215976Sjmallett uint64_t ptrs0 : 17; /**< Internal state */ 1658215976Sjmallett uint64_t reserved_0_31 : 32; 1659215976Sjmallett#else 1660215976Sjmallett uint64_t reserved_0_31 : 32; 1661215976Sjmallett uint64_t ptrs0 : 17; 1662215976Sjmallett uint64_t reserved_49_63 : 15; 1663215976Sjmallett#endif 1664215976Sjmallett } s; 1665232812Sjmallett struct cvmx_pko_mem_debug9_cn30xx { 1666232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1667215976Sjmallett uint64_t reserved_28_63 : 36; 1668215976Sjmallett uint64_t doorbell : 20; /**< Doorbell count */ 1669215976Sjmallett uint64_t reserved_5_7 : 3; 1670215976Sjmallett uint64_t s_tail : 1; /**< reads as zero (S_TAIL cannot be read) */ 1671215976Sjmallett uint64_t static_q : 1; /**< reads as zero (STATIC_Q cannot be read) */ 1672215976Sjmallett uint64_t qos : 3; /**< QOS mask to enable the queue when set */ 1673215976Sjmallett#else 1674215976Sjmallett uint64_t qos : 3; 1675215976Sjmallett uint64_t static_q : 1; 1676215976Sjmallett uint64_t s_tail : 1; 1677215976Sjmallett uint64_t reserved_5_7 : 3; 1678215976Sjmallett uint64_t doorbell : 20; 1679215976Sjmallett uint64_t reserved_28_63 : 36; 1680215976Sjmallett#endif 1681215976Sjmallett } cn30xx; 1682215976Sjmallett struct cvmx_pko_mem_debug9_cn30xx cn31xx; 1683232812Sjmallett struct cvmx_pko_mem_debug9_cn38xx { 1684232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1685215976Sjmallett uint64_t reserved_28_63 : 36; 1686215976Sjmallett uint64_t doorbell : 20; /**< Doorbell count */ 1687215976Sjmallett uint64_t reserved_6_7 : 2; 1688215976Sjmallett uint64_t static_p : 1; /**< Static priority (port) */ 1689215976Sjmallett uint64_t s_tail : 1; /**< Static tail */ 1690215976Sjmallett uint64_t static_q : 1; /**< Static priority */ 1691215976Sjmallett uint64_t qos : 3; /**< QOS mask to enable the queue when set */ 1692215976Sjmallett#else 1693215976Sjmallett uint64_t qos : 3; 1694215976Sjmallett uint64_t static_q : 1; 1695215976Sjmallett uint64_t s_tail : 1; 1696215976Sjmallett uint64_t static_p : 1; 1697215976Sjmallett uint64_t reserved_6_7 : 2; 1698215976Sjmallett uint64_t doorbell : 20; 1699215976Sjmallett uint64_t reserved_28_63 : 36; 1700215976Sjmallett#endif 1701215976Sjmallett } cn38xx; 1702215976Sjmallett struct cvmx_pko_mem_debug9_cn38xx cn38xxp2; 1703232812Sjmallett struct cvmx_pko_mem_debug9_cn50xx { 1704232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1705215976Sjmallett uint64_t reserved_49_63 : 15; 1706215976Sjmallett uint64_t ptrs0 : 17; /**< Internal state */ 1707215976Sjmallett uint64_t reserved_17_31 : 15; 1708215976Sjmallett uint64_t ptrs3 : 17; /**< Internal state */ 1709215976Sjmallett#else 1710215976Sjmallett uint64_t ptrs3 : 17; 1711215976Sjmallett uint64_t reserved_17_31 : 15; 1712215976Sjmallett uint64_t ptrs0 : 17; 1713215976Sjmallett uint64_t reserved_49_63 : 15; 1714215976Sjmallett#endif 1715215976Sjmallett } cn50xx; 1716215976Sjmallett struct cvmx_pko_mem_debug9_cn50xx cn52xx; 1717215976Sjmallett struct cvmx_pko_mem_debug9_cn50xx cn52xxp1; 1718215976Sjmallett struct cvmx_pko_mem_debug9_cn50xx cn56xx; 1719215976Sjmallett struct cvmx_pko_mem_debug9_cn50xx cn56xxp1; 1720215976Sjmallett struct cvmx_pko_mem_debug9_cn50xx cn58xx; 1721215976Sjmallett struct cvmx_pko_mem_debug9_cn50xx cn58xxp1; 1722232812Sjmallett struct cvmx_pko_mem_debug9_cn50xx cn61xx; 1723215976Sjmallett struct cvmx_pko_mem_debug9_cn50xx cn63xx; 1724215976Sjmallett struct cvmx_pko_mem_debug9_cn50xx cn63xxp1; 1725232812Sjmallett struct cvmx_pko_mem_debug9_cn50xx cn66xx; 1726232812Sjmallett struct cvmx_pko_mem_debug9_cn50xx cn68xx; 1727232812Sjmallett struct cvmx_pko_mem_debug9_cn50xx cn68xxp1; 1728232812Sjmallett struct cvmx_pko_mem_debug9_cn50xx cnf71xx; 1729215976Sjmallett}; 1730215976Sjmalletttypedef union cvmx_pko_mem_debug9 cvmx_pko_mem_debug9_t; 1731215976Sjmallett 1732215976Sjmallett/** 1733232812Sjmallett * cvmx_pko_mem_iport_ptrs 1734232812Sjmallett * 1735232812Sjmallett * Notes: 1736232812Sjmallett * This CSR is a memory of 128 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1737232812Sjmallett * CSR read operations to this address can be performed. The index to this CSR is an IPORT. A read of any 1738232812Sjmallett * entry that has not been previously written is illegal and will result in unpredictable CSR read data. 1739232812Sjmallett */ 1740232812Sjmallettunion cvmx_pko_mem_iport_ptrs { 1741232812Sjmallett uint64_t u64; 1742232812Sjmallett struct cvmx_pko_mem_iport_ptrs_s { 1743232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1744232812Sjmallett uint64_t reserved_63_63 : 1; 1745232812Sjmallett uint64_t crc : 1; /**< Set if this IPID uses CRC */ 1746232812Sjmallett uint64_t static_p : 1; /**< Set if this IPID has static priority */ 1747232812Sjmallett uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 1748232812Sjmallett uint64_t min_pkt : 3; /**< Min packet size specified by PKO_REG_MIN_PKT[MIN_PKT] */ 1749232812Sjmallett uint64_t reserved_31_49 : 19; 1750232812Sjmallett uint64_t pipe : 7; /**< The PKO pipe or loopback port 1751232812Sjmallett When INT != PIP/IPD: 1752232812Sjmallett PIPE is the PKO pipe to which this port is mapped 1753232812Sjmallett All used PKO-internal ports that map to the same 1754232812Sjmallett PIPE must also map to the same INT and EID in 1755232812Sjmallett this case. 1756232812Sjmallett When INT == PIP/IPD: 1757232812Sjmallett PIPE must be in the range 1758232812Sjmallett 0..PKO_REG_LOOPBACK[NUM_PORTS]-1 1759232812Sjmallett in this case and selects one of the loopback 1760232812Sjmallett ports. */ 1761232812Sjmallett uint64_t reserved_21_23 : 3; 1762232812Sjmallett uint64_t intr : 5; /**< The interface to which this port is mapped 1763232812Sjmallett All used PKO-internal ports that map to the same EID 1764232812Sjmallett must also map to the same INT. All used PKO-internal 1765232812Sjmallett ports that map to the same INT must also map to the 1766232812Sjmallett same EID. 1767232812Sjmallett Encoding: 1768232812Sjmallett 0 = GMX0 XAUI/DXAUI/RXAUI0 or SGMII0 1769232812Sjmallett 1 = GMX0 SGMII1 1770232812Sjmallett 2 = GMX0 SGMII2 1771232812Sjmallett 3 = GMX0 SGMII3 1772232812Sjmallett 4 = GMX1 RXAUI 1773232812Sjmallett 8 = GMX2 XAUI/DXAUI or SGMII0 1774232812Sjmallett 9 = GMX2 SGMII1 1775232812Sjmallett 10 = GMX2 SGMII2 1776232812Sjmallett 11 = GMX2 SGMII3 1777232812Sjmallett 12 = GMX3 XAUI/DXAUI or SGMII0 1778232812Sjmallett 13 = GMX3 SGMII1 1779232812Sjmallett 14 = GMX3 SGMII2 1780232812Sjmallett 15 = GMX3 SGMII3 1781232812Sjmallett 16 = GMX4 XAUI/DXAUI or SGMII0 1782232812Sjmallett 17 = GMX4 SGMII1 1783232812Sjmallett 18 = GMX4 SGMII2 1784232812Sjmallett 19 = GMX4 SGMII3 1785232812Sjmallett 28 = ILK interface 0 1786232812Sjmallett 29 = ILK interface 1 1787232812Sjmallett 30 = DPI 1788232812Sjmallett 31 = PIP/IPD 1789232812Sjmallett others = reserved */ 1790232812Sjmallett uint64_t reserved_13_15 : 3; 1791232812Sjmallett uint64_t eid : 5; /**< Engine ID to which this port is mapped 1792232812Sjmallett EID==31 can be used with unused PKO-internal ports. 1793232812Sjmallett Otherwise, 0-19 are legal EID values. */ 1794232812Sjmallett uint64_t reserved_7_7 : 1; 1795232812Sjmallett uint64_t ipid : 7; /**< PKO-internal Port ID to be accessed */ 1796232812Sjmallett#else 1797232812Sjmallett uint64_t ipid : 7; 1798232812Sjmallett uint64_t reserved_7_7 : 1; 1799232812Sjmallett uint64_t eid : 5; 1800232812Sjmallett uint64_t reserved_13_15 : 3; 1801232812Sjmallett uint64_t intr : 5; 1802232812Sjmallett uint64_t reserved_21_23 : 3; 1803232812Sjmallett uint64_t pipe : 7; 1804232812Sjmallett uint64_t reserved_31_49 : 19; 1805232812Sjmallett uint64_t min_pkt : 3; 1806232812Sjmallett uint64_t qos_mask : 8; 1807232812Sjmallett uint64_t static_p : 1; 1808232812Sjmallett uint64_t crc : 1; 1809232812Sjmallett uint64_t reserved_63_63 : 1; 1810232812Sjmallett#endif 1811232812Sjmallett } s; 1812232812Sjmallett struct cvmx_pko_mem_iport_ptrs_s cn68xx; 1813232812Sjmallett struct cvmx_pko_mem_iport_ptrs_s cn68xxp1; 1814232812Sjmallett}; 1815232812Sjmalletttypedef union cvmx_pko_mem_iport_ptrs cvmx_pko_mem_iport_ptrs_t; 1816232812Sjmallett 1817232812Sjmallett/** 1818232812Sjmallett * cvmx_pko_mem_iport_qos 1819232812Sjmallett * 1820232812Sjmallett * Notes: 1821232812Sjmallett * Sets the QOS mask, per port. These QOS_MASK bits are logically and physically the same QOS_MASK 1822232812Sjmallett * bits in PKO_MEM_IPORT_PTRS. This CSR address allows the QOS_MASK bits to be written during PKO 1823232812Sjmallett * operation without affecting any other port state. The engine to which port PID is mapped is engine 1824232812Sjmallett * EID. Note that the port to engine mapping must be the same as was previously programmed via the 1825232812Sjmallett * PKO_MEM_IPORT_PTRS CSR. 1826232812Sjmallett * This CSR is a memory of 128 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1827232812Sjmallett * CSR read operations to this address can be performed. The index to this CSR is an IPORT. A read of 1828232812Sjmallett * any entry that has not been previously written is illegal and will result in unpredictable CSR read data. 1829232812Sjmallett */ 1830232812Sjmallettunion cvmx_pko_mem_iport_qos { 1831232812Sjmallett uint64_t u64; 1832232812Sjmallett struct cvmx_pko_mem_iport_qos_s { 1833232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1834232812Sjmallett uint64_t reserved_61_63 : 3; 1835232812Sjmallett uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 1836232812Sjmallett uint64_t reserved_13_52 : 40; 1837232812Sjmallett uint64_t eid : 5; /**< Engine ID to which this port is mapped */ 1838232812Sjmallett uint64_t reserved_7_7 : 1; 1839232812Sjmallett uint64_t ipid : 7; /**< PKO-internal Port ID */ 1840232812Sjmallett#else 1841232812Sjmallett uint64_t ipid : 7; 1842232812Sjmallett uint64_t reserved_7_7 : 1; 1843232812Sjmallett uint64_t eid : 5; 1844232812Sjmallett uint64_t reserved_13_52 : 40; 1845232812Sjmallett uint64_t qos_mask : 8; 1846232812Sjmallett uint64_t reserved_61_63 : 3; 1847232812Sjmallett#endif 1848232812Sjmallett } s; 1849232812Sjmallett struct cvmx_pko_mem_iport_qos_s cn68xx; 1850232812Sjmallett struct cvmx_pko_mem_iport_qos_s cn68xxp1; 1851232812Sjmallett}; 1852232812Sjmalletttypedef union cvmx_pko_mem_iport_qos cvmx_pko_mem_iport_qos_t; 1853232812Sjmallett 1854232812Sjmallett/** 1855232812Sjmallett * cvmx_pko_mem_iqueue_ptrs 1856232812Sjmallett * 1857232812Sjmallett * Notes: 1858232812Sjmallett * Sets the queue to port mapping and the initial command buffer pointer, per queue. Unused queues must 1859232812Sjmallett * set BUF_PTR=0. Each queue may map to at most one port. No more than 32 queues may map to a port. 1860232812Sjmallett * The set of queues that is mapped to a port must be a contiguous array of queues. The port to which 1861232812Sjmallett * queue QID is mapped is port IPID. The index of queue QID in port IPID's queue list is IDX. The last 1862232812Sjmallett * queue in port IPID's queue array must have its TAIL bit set. 1863232812Sjmallett * STATIC_Q marks queue QID as having static priority. STATIC_P marks the port IPID to which QID is 1864232812Sjmallett * mapped as having at least one queue with static priority. If any QID that maps to IPID has static 1865232812Sjmallett * priority, then all QID that map to IPID must have STATIC_P set. Queues marked as static priority 1866232812Sjmallett * must be contiguous and begin at IDX 0. The last queue that is marked as having static priority 1867232812Sjmallett * must have its S_TAIL bit set. 1868232812Sjmallett * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1869232812Sjmallett * CSR read operations to this address can be performed. The index to this CSR is an IQUEUE. A read of any 1870232812Sjmallett * entry that has not been previously written is illegal and will result in unpredictable CSR read data. 1871232812Sjmallett */ 1872232812Sjmallettunion cvmx_pko_mem_iqueue_ptrs { 1873232812Sjmallett uint64_t u64; 1874232812Sjmallett struct cvmx_pko_mem_iqueue_ptrs_s { 1875232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1876232812Sjmallett uint64_t s_tail : 1; /**< Set if this QID is the tail of the static queues */ 1877232812Sjmallett uint64_t static_p : 1; /**< Set if any QID in this IPID has static priority */ 1878232812Sjmallett uint64_t static_q : 1; /**< Set if this QID has static priority */ 1879232812Sjmallett uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 1880232812Sjmallett uint64_t buf_ptr : 31; /**< Command buffer pointer[37:7] */ 1881232812Sjmallett uint64_t tail : 1; /**< Set if this QID is the tail of the queue array */ 1882232812Sjmallett uint64_t index : 5; /**< Index (distance from head) in the queue array */ 1883232812Sjmallett uint64_t reserved_15_15 : 1; 1884232812Sjmallett uint64_t ipid : 7; /**< PKO-Internal Port ID to which this queue is mapped */ 1885232812Sjmallett uint64_t qid : 8; /**< Queue ID */ 1886232812Sjmallett#else 1887232812Sjmallett uint64_t qid : 8; 1888232812Sjmallett uint64_t ipid : 7; 1889232812Sjmallett uint64_t reserved_15_15 : 1; 1890232812Sjmallett uint64_t index : 5; 1891232812Sjmallett uint64_t tail : 1; 1892232812Sjmallett uint64_t buf_ptr : 31; 1893232812Sjmallett uint64_t qos_mask : 8; 1894232812Sjmallett uint64_t static_q : 1; 1895232812Sjmallett uint64_t static_p : 1; 1896232812Sjmallett uint64_t s_tail : 1; 1897232812Sjmallett#endif 1898232812Sjmallett } s; 1899232812Sjmallett struct cvmx_pko_mem_iqueue_ptrs_s cn68xx; 1900232812Sjmallett struct cvmx_pko_mem_iqueue_ptrs_s cn68xxp1; 1901232812Sjmallett}; 1902232812Sjmalletttypedef union cvmx_pko_mem_iqueue_ptrs cvmx_pko_mem_iqueue_ptrs_t; 1903232812Sjmallett 1904232812Sjmallett/** 1905232812Sjmallett * cvmx_pko_mem_iqueue_qos 1906232812Sjmallett * 1907232812Sjmallett * Notes: 1908232812Sjmallett * Sets the QOS mask, per queue. These QOS_MASK bits are logically and physically the same QOS_MASK 1909232812Sjmallett * bits in PKO_MEM_IQUEUE_PTRS. This CSR address allows the QOS_MASK bits to be written during PKO 1910232812Sjmallett * operation without affecting any other queue state. The port to which queue QID is mapped is port 1911232812Sjmallett * IPID. Note that the queue to port mapping must be the same as was previously programmed via the 1912232812Sjmallett * PKO_MEM_IQUEUE_PTRS CSR. 1913232812Sjmallett * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1914232812Sjmallett * CSR read operations to this address can be performed. The index to this CSR is an IQUEUE. A read of any 1915232812Sjmallett * entry that has not been previously written is illegal and will result in unpredictable CSR read data. 1916232812Sjmallett */ 1917232812Sjmallettunion cvmx_pko_mem_iqueue_qos { 1918232812Sjmallett uint64_t u64; 1919232812Sjmallett struct cvmx_pko_mem_iqueue_qos_s { 1920232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1921232812Sjmallett uint64_t reserved_61_63 : 3; 1922232812Sjmallett uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 1923232812Sjmallett uint64_t reserved_15_52 : 38; 1924232812Sjmallett uint64_t ipid : 7; /**< PKO-Internal Port ID to which this queue is mapped */ 1925232812Sjmallett uint64_t qid : 8; /**< Queue ID */ 1926232812Sjmallett#else 1927232812Sjmallett uint64_t qid : 8; 1928232812Sjmallett uint64_t ipid : 7; 1929232812Sjmallett uint64_t reserved_15_52 : 38; 1930232812Sjmallett uint64_t qos_mask : 8; 1931232812Sjmallett uint64_t reserved_61_63 : 3; 1932232812Sjmallett#endif 1933232812Sjmallett } s; 1934232812Sjmallett struct cvmx_pko_mem_iqueue_qos_s cn68xx; 1935232812Sjmallett struct cvmx_pko_mem_iqueue_qos_s cn68xxp1; 1936232812Sjmallett}; 1937232812Sjmalletttypedef union cvmx_pko_mem_iqueue_qos cvmx_pko_mem_iqueue_qos_t; 1938232812Sjmallett 1939232812Sjmallett/** 1940215976Sjmallett * cvmx_pko_mem_port_ptrs 1941215976Sjmallett * 1942215976Sjmallett * Notes: 1943215976Sjmallett * Sets the port to engine mapping, per port. Ports marked as static priority need not be contiguous, 1944215976Sjmallett * but they must be the lowest numbered PIDs mapped to this EID and must have QOS_MASK=0xff. If EID==8 1945215976Sjmallett * or EID==9, then PID[1:0] is used to direct the packet to the correct port on that interface. 1946215976Sjmallett * EID==15 can be used for unused PKO-internal ports. 1947215976Sjmallett * BP_PORT==63 means that the PKO-internal port is not backpressured. 1948215976Sjmallett * BP_PORTs are assumed to belong to an interface as follows: 1949232812Sjmallett * 46 <= BP_PORT < 48 -> srio interface 3 1950232812Sjmallett * 44 <= BP_PORT < 46 -> srio interface 2 1951215976Sjmallett * 42 <= BP_PORT < 44 -> srio interface 1 1952215976Sjmallett * 40 <= BP_PORT < 42 -> srio interface 0 1953215976Sjmallett * 36 <= BP_PORT < 40 -> loopback interface 1954215976Sjmallett * 32 <= BP_PORT < 36 -> PCIe interface 1955215976Sjmallett * 0 <= BP_PORT < 16 -> SGMII/Xaui interface 0 1956215976Sjmallett * 1957215976Sjmallett * Note that the SRIO interfaces do not actually provide backpressure. Thus, ports that use 1958232812Sjmallett * 40 <= BP_PORT < 48 for backpressure will never be backpressured. 1959215976Sjmallett * 1960215976Sjmallett * The reset configuration is the following: 1961215976Sjmallett * PID EID(ext port) BP_PORT QOS_MASK STATIC_P 1962215976Sjmallett * ------------------------------------------- 1963215976Sjmallett * 0 0( 0) 0 0xff 0 1964215976Sjmallett * 1 1( 1) 1 0xff 0 1965215976Sjmallett * 2 2( 2) 2 0xff 0 1966215976Sjmallett * 3 3( 3) 3 0xff 0 1967215976Sjmallett * 4 0( 0) 4 0xff 0 1968215976Sjmallett * 5 1( 1) 5 0xff 0 1969215976Sjmallett * 6 2( 2) 6 0xff 0 1970215976Sjmallett * 7 3( 3) 7 0xff 0 1971215976Sjmallett * 8 0( 0) 8 0xff 0 1972215976Sjmallett * 9 1( 1) 9 0xff 0 1973215976Sjmallett * 10 2( 2) 10 0xff 0 1974215976Sjmallett * 11 3( 3) 11 0xff 0 1975215976Sjmallett * 12 0( 0) 12 0xff 0 1976215976Sjmallett * 13 1( 1) 13 0xff 0 1977215976Sjmallett * 14 2( 2) 14 0xff 0 1978215976Sjmallett * 15 3( 3) 15 0xff 0 1979215976Sjmallett * ------------------------------------------- 1980232812Sjmallett * 16 4(16) 16 0xff 0 1981232812Sjmallett * 17 5(17) 17 0xff 0 1982232812Sjmallett * 18 6(18) 18 0xff 0 1983232812Sjmallett * 19 7(19) 19 0xff 0 1984232812Sjmallett * 20 4(16) 20 0xff 0 1985232812Sjmallett * 21 5(17) 21 0xff 0 1986232812Sjmallett * 22 6(18) 22 0xff 0 1987232812Sjmallett * 23 7(19) 23 0xff 0 1988232812Sjmallett * 24 4(16) 24 0xff 0 1989232812Sjmallett * 25 5(17) 25 0xff 0 1990232812Sjmallett * 26 6(18) 26 0xff 0 1991232812Sjmallett * 27 7(19) 27 0xff 0 1992232812Sjmallett * 28 4(16) 28 0xff 0 1993232812Sjmallett * 29 5(17) 29 0xff 0 1994232812Sjmallett * 30 6(18) 30 0xff 0 1995232812Sjmallett * 31 7(19) 31 0xff 0 1996215976Sjmallett * ------------------------------------------- 1997215976Sjmallett * 32 8(32) 32 0xff 0 1998215976Sjmallett * 33 8(33) 33 0xff 0 1999215976Sjmallett * 34 8(34) 34 0xff 0 2000215976Sjmallett * 35 8(35) 35 0xff 0 2001215976Sjmallett * ------------------------------------------- 2002215976Sjmallett * 36 9(36) 36 0xff 0 2003215976Sjmallett * 37 9(37) 37 0xff 0 2004215976Sjmallett * 38 9(38) 38 0xff 0 2005215976Sjmallett * 39 9(39) 39 0xff 0 2006215976Sjmallett * 2007232812Sjmallett * This CSR is a memory of 48 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2008215976Sjmallett * CSR read operations to this address can be performed. A read of any entry that has not been 2009215976Sjmallett * previously written is illegal and will result in unpredictable CSR read data. 2010215976Sjmallett */ 2011232812Sjmallettunion cvmx_pko_mem_port_ptrs { 2012215976Sjmallett uint64_t u64; 2013232812Sjmallett struct cvmx_pko_mem_port_ptrs_s { 2014232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2015215976Sjmallett uint64_t reserved_62_63 : 2; 2016215976Sjmallett uint64_t static_p : 1; /**< Set if this PID has static priority */ 2017215976Sjmallett uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 2018215976Sjmallett uint64_t reserved_16_52 : 37; 2019215976Sjmallett uint64_t bp_port : 6; /**< PID listens to BP_PORT for per-packet backpressure 2020232812Sjmallett Legal BP_PORTs: 0-15, 32-47, 63 (63 means no BP) */ 2021215976Sjmallett uint64_t eid : 4; /**< Engine ID to which this port is mapped 2022232812Sjmallett Legal EIDs: 0-3, 8-13, 15 (15 only if port not used) */ 2023215976Sjmallett uint64_t pid : 6; /**< Port ID[5:0] */ 2024215976Sjmallett#else 2025215976Sjmallett uint64_t pid : 6; 2026215976Sjmallett uint64_t eid : 4; 2027215976Sjmallett uint64_t bp_port : 6; 2028215976Sjmallett uint64_t reserved_16_52 : 37; 2029215976Sjmallett uint64_t qos_mask : 8; 2030215976Sjmallett uint64_t static_p : 1; 2031215976Sjmallett uint64_t reserved_62_63 : 2; 2032215976Sjmallett#endif 2033215976Sjmallett } s; 2034215976Sjmallett struct cvmx_pko_mem_port_ptrs_s cn52xx; 2035215976Sjmallett struct cvmx_pko_mem_port_ptrs_s cn52xxp1; 2036215976Sjmallett struct cvmx_pko_mem_port_ptrs_s cn56xx; 2037215976Sjmallett struct cvmx_pko_mem_port_ptrs_s cn56xxp1; 2038232812Sjmallett struct cvmx_pko_mem_port_ptrs_s cn61xx; 2039215976Sjmallett struct cvmx_pko_mem_port_ptrs_s cn63xx; 2040215976Sjmallett struct cvmx_pko_mem_port_ptrs_s cn63xxp1; 2041232812Sjmallett struct cvmx_pko_mem_port_ptrs_s cn66xx; 2042232812Sjmallett struct cvmx_pko_mem_port_ptrs_s cnf71xx; 2043215976Sjmallett}; 2044215976Sjmalletttypedef union cvmx_pko_mem_port_ptrs cvmx_pko_mem_port_ptrs_t; 2045215976Sjmallett 2046215976Sjmallett/** 2047215976Sjmallett * cvmx_pko_mem_port_qos 2048215976Sjmallett * 2049215976Sjmallett * Notes: 2050215976Sjmallett * Sets the QOS mask, per port. These QOS_MASK bits are logically and physically the same QOS_MASK 2051215976Sjmallett * bits in PKO_MEM_PORT_PTRS. This CSR address allows the QOS_MASK bits to be written during PKO 2052215976Sjmallett * operation without affecting any other port state. The engine to which port PID is mapped is engine 2053215976Sjmallett * EID. Note that the port to engine mapping must be the same as was previously programmed via the 2054215976Sjmallett * PKO_MEM_PORT_PTRS CSR. 2055215976Sjmallett * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2056215976Sjmallett * CSR read operations to this address can be performed. A read of any entry that has not been 2057215976Sjmallett * previously written is illegal and will result in unpredictable CSR read data. 2058215976Sjmallett */ 2059232812Sjmallettunion cvmx_pko_mem_port_qos { 2060215976Sjmallett uint64_t u64; 2061232812Sjmallett struct cvmx_pko_mem_port_qos_s { 2062232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2063215976Sjmallett uint64_t reserved_61_63 : 3; 2064215976Sjmallett uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 2065215976Sjmallett uint64_t reserved_10_52 : 43; 2066215976Sjmallett uint64_t eid : 4; /**< Engine ID to which this port is mapped 2067215976Sjmallett Legal EIDs: 0-3, 8-11 */ 2068215976Sjmallett uint64_t pid : 6; /**< Port ID[5:0] */ 2069215976Sjmallett#else 2070215976Sjmallett uint64_t pid : 6; 2071215976Sjmallett uint64_t eid : 4; 2072215976Sjmallett uint64_t reserved_10_52 : 43; 2073215976Sjmallett uint64_t qos_mask : 8; 2074215976Sjmallett uint64_t reserved_61_63 : 3; 2075215976Sjmallett#endif 2076215976Sjmallett } s; 2077215976Sjmallett struct cvmx_pko_mem_port_qos_s cn52xx; 2078215976Sjmallett struct cvmx_pko_mem_port_qos_s cn52xxp1; 2079215976Sjmallett struct cvmx_pko_mem_port_qos_s cn56xx; 2080215976Sjmallett struct cvmx_pko_mem_port_qos_s cn56xxp1; 2081232812Sjmallett struct cvmx_pko_mem_port_qos_s cn61xx; 2082215976Sjmallett struct cvmx_pko_mem_port_qos_s cn63xx; 2083215976Sjmallett struct cvmx_pko_mem_port_qos_s cn63xxp1; 2084232812Sjmallett struct cvmx_pko_mem_port_qos_s cn66xx; 2085232812Sjmallett struct cvmx_pko_mem_port_qos_s cnf71xx; 2086215976Sjmallett}; 2087215976Sjmalletttypedef union cvmx_pko_mem_port_qos cvmx_pko_mem_port_qos_t; 2088215976Sjmallett 2089215976Sjmallett/** 2090215976Sjmallett * cvmx_pko_mem_port_rate0 2091215976Sjmallett * 2092215976Sjmallett * Notes: 2093215976Sjmallett * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2094215976Sjmallett * CSR read operations to this address can be performed. A read of any entry that has not been 2095215976Sjmallett * previously written is illegal and will result in unpredictable CSR read data. 2096215976Sjmallett */ 2097232812Sjmallettunion cvmx_pko_mem_port_rate0 { 2098215976Sjmallett uint64_t u64; 2099232812Sjmallett struct cvmx_pko_mem_port_rate0_s { 2100232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2101215976Sjmallett uint64_t reserved_51_63 : 13; 2102215976Sjmallett uint64_t rate_word : 19; /**< Rate limiting adder per 8 byte */ 2103215976Sjmallett uint64_t rate_pkt : 24; /**< Rate limiting adder per packet */ 2104232812Sjmallett uint64_t reserved_7_7 : 1; 2105232812Sjmallett uint64_t pid : 7; /**< Port ID[5:0] */ 2106232812Sjmallett#else 2107232812Sjmallett uint64_t pid : 7; 2108232812Sjmallett uint64_t reserved_7_7 : 1; 2109232812Sjmallett uint64_t rate_pkt : 24; 2110232812Sjmallett uint64_t rate_word : 19; 2111232812Sjmallett uint64_t reserved_51_63 : 13; 2112232812Sjmallett#endif 2113232812Sjmallett } s; 2114232812Sjmallett struct cvmx_pko_mem_port_rate0_cn52xx { 2115232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2116232812Sjmallett uint64_t reserved_51_63 : 13; 2117232812Sjmallett uint64_t rate_word : 19; /**< Rate limiting adder per 8 byte */ 2118232812Sjmallett uint64_t rate_pkt : 24; /**< Rate limiting adder per packet */ 2119215976Sjmallett uint64_t reserved_6_7 : 2; 2120215976Sjmallett uint64_t pid : 6; /**< Port ID[5:0] */ 2121215976Sjmallett#else 2122215976Sjmallett uint64_t pid : 6; 2123215976Sjmallett uint64_t reserved_6_7 : 2; 2124215976Sjmallett uint64_t rate_pkt : 24; 2125215976Sjmallett uint64_t rate_word : 19; 2126215976Sjmallett uint64_t reserved_51_63 : 13; 2127215976Sjmallett#endif 2128232812Sjmallett } cn52xx; 2129232812Sjmallett struct cvmx_pko_mem_port_rate0_cn52xx cn52xxp1; 2130232812Sjmallett struct cvmx_pko_mem_port_rate0_cn52xx cn56xx; 2131232812Sjmallett struct cvmx_pko_mem_port_rate0_cn52xx cn56xxp1; 2132232812Sjmallett struct cvmx_pko_mem_port_rate0_cn52xx cn61xx; 2133232812Sjmallett struct cvmx_pko_mem_port_rate0_cn52xx cn63xx; 2134232812Sjmallett struct cvmx_pko_mem_port_rate0_cn52xx cn63xxp1; 2135232812Sjmallett struct cvmx_pko_mem_port_rate0_cn52xx cn66xx; 2136232812Sjmallett struct cvmx_pko_mem_port_rate0_s cn68xx; 2137232812Sjmallett struct cvmx_pko_mem_port_rate0_s cn68xxp1; 2138232812Sjmallett struct cvmx_pko_mem_port_rate0_cn52xx cnf71xx; 2139215976Sjmallett}; 2140215976Sjmalletttypedef union cvmx_pko_mem_port_rate0 cvmx_pko_mem_port_rate0_t; 2141215976Sjmallett 2142215976Sjmallett/** 2143215976Sjmallett * cvmx_pko_mem_port_rate1 2144215976Sjmallett * 2145215976Sjmallett * Notes: 2146215976Sjmallett * Writing PKO_MEM_PORT_RATE1[PID,RATE_LIM] has the side effect of setting the corresponding 2147215976Sjmallett * accumulator to zero. 2148215976Sjmallett * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2149215976Sjmallett * CSR read operations to this address can be performed. A read of any entry that has not been 2150215976Sjmallett * previously written is illegal and will result in unpredictable CSR read data. 2151215976Sjmallett */ 2152232812Sjmallettunion cvmx_pko_mem_port_rate1 { 2153215976Sjmallett uint64_t u64; 2154232812Sjmallett struct cvmx_pko_mem_port_rate1_s { 2155232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2156215976Sjmallett uint64_t reserved_32_63 : 32; 2157215976Sjmallett uint64_t rate_lim : 24; /**< Rate limiting accumulator limit */ 2158232812Sjmallett uint64_t reserved_7_7 : 1; 2159232812Sjmallett uint64_t pid : 7; /**< Port ID[5:0] */ 2160232812Sjmallett#else 2161232812Sjmallett uint64_t pid : 7; 2162232812Sjmallett uint64_t reserved_7_7 : 1; 2163232812Sjmallett uint64_t rate_lim : 24; 2164232812Sjmallett uint64_t reserved_32_63 : 32; 2165232812Sjmallett#endif 2166232812Sjmallett } s; 2167232812Sjmallett struct cvmx_pko_mem_port_rate1_cn52xx { 2168232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2169232812Sjmallett uint64_t reserved_32_63 : 32; 2170232812Sjmallett uint64_t rate_lim : 24; /**< Rate limiting accumulator limit */ 2171215976Sjmallett uint64_t reserved_6_7 : 2; 2172215976Sjmallett uint64_t pid : 6; /**< Port ID[5:0] */ 2173215976Sjmallett#else 2174215976Sjmallett uint64_t pid : 6; 2175215976Sjmallett uint64_t reserved_6_7 : 2; 2176215976Sjmallett uint64_t rate_lim : 24; 2177215976Sjmallett uint64_t reserved_32_63 : 32; 2178215976Sjmallett#endif 2179232812Sjmallett } cn52xx; 2180232812Sjmallett struct cvmx_pko_mem_port_rate1_cn52xx cn52xxp1; 2181232812Sjmallett struct cvmx_pko_mem_port_rate1_cn52xx cn56xx; 2182232812Sjmallett struct cvmx_pko_mem_port_rate1_cn52xx cn56xxp1; 2183232812Sjmallett struct cvmx_pko_mem_port_rate1_cn52xx cn61xx; 2184232812Sjmallett struct cvmx_pko_mem_port_rate1_cn52xx cn63xx; 2185232812Sjmallett struct cvmx_pko_mem_port_rate1_cn52xx cn63xxp1; 2186232812Sjmallett struct cvmx_pko_mem_port_rate1_cn52xx cn66xx; 2187232812Sjmallett struct cvmx_pko_mem_port_rate1_s cn68xx; 2188232812Sjmallett struct cvmx_pko_mem_port_rate1_s cn68xxp1; 2189232812Sjmallett struct cvmx_pko_mem_port_rate1_cn52xx cnf71xx; 2190215976Sjmallett}; 2191215976Sjmalletttypedef union cvmx_pko_mem_port_rate1 cvmx_pko_mem_port_rate1_t; 2192215976Sjmallett 2193215976Sjmallett/** 2194215976Sjmallett * cvmx_pko_mem_queue_ptrs 2195215976Sjmallett * 2196215976Sjmallett * Notes: 2197215976Sjmallett * Sets the queue to port mapping and the initial command buffer pointer, per queue 2198215976Sjmallett * Each queue may map to at most one port. No more than 16 queues may map to a port. The set of 2199215976Sjmallett * queues that is mapped to a port must be a contiguous array of queues. The port to which queue QID 2200215976Sjmallett * is mapped is port PID. The index of queue QID in port PID's queue list is IDX. The last queue in 2201215976Sjmallett * port PID's queue array must have its TAIL bit set. Unused queues must be mapped to port 63. 2202215976Sjmallett * STATIC_Q marks queue QID as having static priority. STATIC_P marks the port PID to which QID is 2203215976Sjmallett * mapped as having at least one queue with static priority. If any QID that maps to PID has static 2204215976Sjmallett * priority, then all QID that map to PID must have STATIC_P set. Queues marked as static priority 2205215976Sjmallett * must be contiguous and begin at IDX 0. The last queue that is marked as having static priority 2206215976Sjmallett * must have its S_TAIL bit set. 2207215976Sjmallett * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2208215976Sjmallett * CSR read operations to this address can be performed. A read of any entry that has not been 2209215976Sjmallett * previously written is illegal and will result in unpredictable CSR read data. 2210215976Sjmallett */ 2211232812Sjmallettunion cvmx_pko_mem_queue_ptrs { 2212215976Sjmallett uint64_t u64; 2213232812Sjmallett struct cvmx_pko_mem_queue_ptrs_s { 2214232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2215215976Sjmallett uint64_t s_tail : 1; /**< Set if this QID is the tail of the static queues */ 2216215976Sjmallett uint64_t static_p : 1; /**< Set if any QID in this PID has static priority */ 2217215976Sjmallett uint64_t static_q : 1; /**< Set if this QID has static priority */ 2218215976Sjmallett uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 2219215976Sjmallett uint64_t buf_ptr : 36; /**< Command buffer pointer, <23:17> MBZ */ 2220215976Sjmallett uint64_t tail : 1; /**< Set if this QID is the tail of the queue array */ 2221215976Sjmallett uint64_t index : 3; /**< Index[2:0] (distance from head) in the queue array */ 2222215976Sjmallett uint64_t port : 6; /**< Port ID to which this queue is mapped */ 2223215976Sjmallett uint64_t queue : 7; /**< Queue ID[6:0] */ 2224215976Sjmallett#else 2225215976Sjmallett uint64_t queue : 7; 2226215976Sjmallett uint64_t port : 6; 2227215976Sjmallett uint64_t index : 3; 2228215976Sjmallett uint64_t tail : 1; 2229215976Sjmallett uint64_t buf_ptr : 36; 2230215976Sjmallett uint64_t qos_mask : 8; 2231215976Sjmallett uint64_t static_q : 1; 2232215976Sjmallett uint64_t static_p : 1; 2233215976Sjmallett uint64_t s_tail : 1; 2234215976Sjmallett#endif 2235215976Sjmallett } s; 2236215976Sjmallett struct cvmx_pko_mem_queue_ptrs_s cn30xx; 2237215976Sjmallett struct cvmx_pko_mem_queue_ptrs_s cn31xx; 2238215976Sjmallett struct cvmx_pko_mem_queue_ptrs_s cn38xx; 2239215976Sjmallett struct cvmx_pko_mem_queue_ptrs_s cn38xxp2; 2240215976Sjmallett struct cvmx_pko_mem_queue_ptrs_s cn50xx; 2241215976Sjmallett struct cvmx_pko_mem_queue_ptrs_s cn52xx; 2242215976Sjmallett struct cvmx_pko_mem_queue_ptrs_s cn52xxp1; 2243215976Sjmallett struct cvmx_pko_mem_queue_ptrs_s cn56xx; 2244215976Sjmallett struct cvmx_pko_mem_queue_ptrs_s cn56xxp1; 2245215976Sjmallett struct cvmx_pko_mem_queue_ptrs_s cn58xx; 2246215976Sjmallett struct cvmx_pko_mem_queue_ptrs_s cn58xxp1; 2247232812Sjmallett struct cvmx_pko_mem_queue_ptrs_s cn61xx; 2248215976Sjmallett struct cvmx_pko_mem_queue_ptrs_s cn63xx; 2249215976Sjmallett struct cvmx_pko_mem_queue_ptrs_s cn63xxp1; 2250232812Sjmallett struct cvmx_pko_mem_queue_ptrs_s cn66xx; 2251232812Sjmallett struct cvmx_pko_mem_queue_ptrs_s cnf71xx; 2252215976Sjmallett}; 2253215976Sjmalletttypedef union cvmx_pko_mem_queue_ptrs cvmx_pko_mem_queue_ptrs_t; 2254215976Sjmallett 2255215976Sjmallett/** 2256215976Sjmallett * cvmx_pko_mem_queue_qos 2257215976Sjmallett * 2258215976Sjmallett * Notes: 2259215976Sjmallett * Sets the QOS mask, per queue. These QOS_MASK bits are logically and physically the same QOS_MASK 2260215976Sjmallett * bits in PKO_MEM_QUEUE_PTRS. This CSR address allows the QOS_MASK bits to be written during PKO 2261215976Sjmallett * operation without affecting any other queue state. The port to which queue QID is mapped is port 2262215976Sjmallett * PID. Note that the queue to port mapping must be the same as was previously programmed via the 2263215976Sjmallett * PKO_MEM_QUEUE_PTRS CSR. 2264215976Sjmallett * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2265215976Sjmallett * CSR read operations to this address can be performed. A read of any entry that has not been 2266215976Sjmallett * previously written is illegal and will result in unpredictable CSR read data. 2267215976Sjmallett */ 2268232812Sjmallettunion cvmx_pko_mem_queue_qos { 2269215976Sjmallett uint64_t u64; 2270232812Sjmallett struct cvmx_pko_mem_queue_qos_s { 2271232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2272215976Sjmallett uint64_t reserved_61_63 : 3; 2273215976Sjmallett uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 2274215976Sjmallett uint64_t reserved_13_52 : 40; 2275215976Sjmallett uint64_t pid : 6; /**< Port ID to which this queue is mapped */ 2276215976Sjmallett uint64_t qid : 7; /**< Queue ID */ 2277215976Sjmallett#else 2278215976Sjmallett uint64_t qid : 7; 2279215976Sjmallett uint64_t pid : 6; 2280215976Sjmallett uint64_t reserved_13_52 : 40; 2281215976Sjmallett uint64_t qos_mask : 8; 2282215976Sjmallett uint64_t reserved_61_63 : 3; 2283215976Sjmallett#endif 2284215976Sjmallett } s; 2285215976Sjmallett struct cvmx_pko_mem_queue_qos_s cn30xx; 2286215976Sjmallett struct cvmx_pko_mem_queue_qos_s cn31xx; 2287215976Sjmallett struct cvmx_pko_mem_queue_qos_s cn38xx; 2288215976Sjmallett struct cvmx_pko_mem_queue_qos_s cn38xxp2; 2289215976Sjmallett struct cvmx_pko_mem_queue_qos_s cn50xx; 2290215976Sjmallett struct cvmx_pko_mem_queue_qos_s cn52xx; 2291215976Sjmallett struct cvmx_pko_mem_queue_qos_s cn52xxp1; 2292215976Sjmallett struct cvmx_pko_mem_queue_qos_s cn56xx; 2293215976Sjmallett struct cvmx_pko_mem_queue_qos_s cn56xxp1; 2294215976Sjmallett struct cvmx_pko_mem_queue_qos_s cn58xx; 2295215976Sjmallett struct cvmx_pko_mem_queue_qos_s cn58xxp1; 2296232812Sjmallett struct cvmx_pko_mem_queue_qos_s cn61xx; 2297215976Sjmallett struct cvmx_pko_mem_queue_qos_s cn63xx; 2298215976Sjmallett struct cvmx_pko_mem_queue_qos_s cn63xxp1; 2299232812Sjmallett struct cvmx_pko_mem_queue_qos_s cn66xx; 2300232812Sjmallett struct cvmx_pko_mem_queue_qos_s cnf71xx; 2301215976Sjmallett}; 2302215976Sjmalletttypedef union cvmx_pko_mem_queue_qos cvmx_pko_mem_queue_qos_t; 2303215976Sjmallett 2304215976Sjmallett/** 2305232812Sjmallett * cvmx_pko_mem_throttle_int 2306232812Sjmallett * 2307232812Sjmallett * Notes: 2308232812Sjmallett * Writing PACKET and WORD with 0 resets both counts for INT to 0 rather than add 0. 2309232812Sjmallett * Otherwise, writes to this CSR add to the existing WORD/PACKET counts for the interface INT. 2310232812Sjmallett * 2311232812Sjmallett * PKO tracks the number of (8-byte) WORD's and PACKET's in-flight (sum total in both PKO 2312232812Sjmallett * and the interface MAC) on the interface. (When PKO first selects a packet from a PKO queue, it 2313232812Sjmallett * increments the counts appropriately. When the interface MAC has (largely) completed sending 2314232812Sjmallett * the words/packet, PKO decrements the count appropriately.) When PKO_REG_FLAGS[ENA_THROTTLE] 2315232812Sjmallett * is set and the most-significant bit of the WORD or packet count for a interface is set, 2316232812Sjmallett * PKO will not transfer any packets over the interface. Software can limit the amount of 2317232812Sjmallett * packet data and/or the number of packets that OCTEON can send out the chip after receiving backpressure 2318232812Sjmallett * from the interface/pipe via these per-pipe throttle counts when PKO_REG_FLAGS[ENA_THROTTLE]=1. 2319232812Sjmallett * For example, to limit the number of packets outstanding in the interface to N, preset PACKET for 2320232812Sjmallett * the pipe to the value 0x20-N (0x20 is the smallest PACKET value with the most-significant bit set). 2321232812Sjmallett * 2322232812Sjmallett * This CSR is a memory of 32 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2323232812Sjmallett * CSR read operations to this address can be performed. The index to this CSR is an INTERFACE. A read of any 2324232812Sjmallett * entry that has not been previously written is illegal and will result in unpredictable CSR read data. 2325232812Sjmallett */ 2326232812Sjmallettunion cvmx_pko_mem_throttle_int { 2327232812Sjmallett uint64_t u64; 2328232812Sjmallett struct cvmx_pko_mem_throttle_int_s { 2329232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2330232812Sjmallett uint64_t reserved_47_63 : 17; 2331232812Sjmallett uint64_t word : 15; /**< On a write, the amount to add to the interface 2332232812Sjmallett throttle word count selected by INT. On a read, 2333232812Sjmallett returns the current value of the interface throttle 2334232812Sjmallett word count selected by PKO_REG_READ_IDX[IDX]. */ 2335232812Sjmallett uint64_t reserved_14_31 : 18; 2336232812Sjmallett uint64_t packet : 6; /**< On a write, the amount to add to the interface 2337232812Sjmallett throttle packet count selected by INT. On a read, 2338232812Sjmallett returns the current value of the interface throttle 2339232812Sjmallett packet count selected by PKO_REG_READ_IDX[IDX]. */ 2340232812Sjmallett uint64_t reserved_5_7 : 3; 2341232812Sjmallett uint64_t intr : 5; /**< Selected interface for writes. Undefined on a read. 2342232812Sjmallett See PKO_MEM_IPORT_PTRS[INT] for encoding. */ 2343232812Sjmallett#else 2344232812Sjmallett uint64_t intr : 5; 2345232812Sjmallett uint64_t reserved_5_7 : 3; 2346232812Sjmallett uint64_t packet : 6; 2347232812Sjmallett uint64_t reserved_14_31 : 18; 2348232812Sjmallett uint64_t word : 15; 2349232812Sjmallett uint64_t reserved_47_63 : 17; 2350232812Sjmallett#endif 2351232812Sjmallett } s; 2352232812Sjmallett struct cvmx_pko_mem_throttle_int_s cn68xx; 2353232812Sjmallett struct cvmx_pko_mem_throttle_int_s cn68xxp1; 2354232812Sjmallett}; 2355232812Sjmalletttypedef union cvmx_pko_mem_throttle_int cvmx_pko_mem_throttle_int_t; 2356232812Sjmallett 2357232812Sjmallett/** 2358232812Sjmallett * cvmx_pko_mem_throttle_pipe 2359232812Sjmallett * 2360232812Sjmallett * Notes: 2361232812Sjmallett * Writing PACKET and WORD with 0 resets both counts for PIPE to 0 rather than add 0. 2362232812Sjmallett * Otherwise, writes to this CSR add to the existing WORD/PACKET counts for the PKO pipe PIPE. 2363232812Sjmallett * 2364232812Sjmallett * PKO tracks the number of (8-byte) WORD's and PACKET's in-flight (sum total in both PKO 2365232812Sjmallett * and the interface MAC) on the pipe. (When PKO first selects a packet from a PKO queue, it 2366232812Sjmallett * increments the counts appropriately. When the interface MAC has (largely) completed sending 2367232812Sjmallett * the words/packet, PKO decrements the count appropriately.) When PKO_REG_FLAGS[ENA_THROTTLE] 2368232812Sjmallett * is set and the most-significant bit of the WORD or packet count for a PKO pipe is set, 2369232812Sjmallett * PKO will not transfer any packets over the PKO pipe. Software can limit the amount of 2370232812Sjmallett * packet data and/or the number of packets that OCTEON can send out the chip after receiving backpressure 2371232812Sjmallett * from the interface/pipe via these per-pipe throttle counts when PKO_REG_FLAGS[ENA_THROTTLE]=1. 2372232812Sjmallett * For example, to limit the number of packets outstanding in the pipe to N, preset PACKET for 2373232812Sjmallett * the pipe to the value 0x20-N (0x20 is the smallest PACKET value with the most-significant bit set). 2374232812Sjmallett * 2375232812Sjmallett * This CSR is a memory of 128 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2376232812Sjmallett * CSR read operations to this address can be performed. The index to this CSR is a PIPE. A read of any 2377232812Sjmallett * entry that has not been previously written is illegal and will result in unpredictable CSR read data. 2378232812Sjmallett */ 2379232812Sjmallettunion cvmx_pko_mem_throttle_pipe { 2380232812Sjmallett uint64_t u64; 2381232812Sjmallett struct cvmx_pko_mem_throttle_pipe_s { 2382232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2383232812Sjmallett uint64_t reserved_47_63 : 17; 2384232812Sjmallett uint64_t word : 15; /**< On a write, the amount to add to the pipe throttle 2385232812Sjmallett word count selected by PIPE. On a read, returns 2386232812Sjmallett the current value of the pipe throttle word count 2387232812Sjmallett selected by PKO_REG_READ_IDX[IDX]. */ 2388232812Sjmallett uint64_t reserved_14_31 : 18; 2389232812Sjmallett uint64_t packet : 6; /**< On a write, the amount to add to the pipe throttle 2390232812Sjmallett packet count selected by PIPE. On a read, returns 2391232812Sjmallett the current value of the pipe throttle packet count 2392232812Sjmallett selected by PKO_REG_READ_IDX[IDX]. */ 2393232812Sjmallett uint64_t reserved_7_7 : 1; 2394232812Sjmallett uint64_t pipe : 7; /**< Selected PKO pipe for writes. Undefined on a read. */ 2395232812Sjmallett#else 2396232812Sjmallett uint64_t pipe : 7; 2397232812Sjmallett uint64_t reserved_7_7 : 1; 2398232812Sjmallett uint64_t packet : 6; 2399232812Sjmallett uint64_t reserved_14_31 : 18; 2400232812Sjmallett uint64_t word : 15; 2401232812Sjmallett uint64_t reserved_47_63 : 17; 2402232812Sjmallett#endif 2403232812Sjmallett } s; 2404232812Sjmallett struct cvmx_pko_mem_throttle_pipe_s cn68xx; 2405232812Sjmallett struct cvmx_pko_mem_throttle_pipe_s cn68xxp1; 2406232812Sjmallett}; 2407232812Sjmalletttypedef union cvmx_pko_mem_throttle_pipe cvmx_pko_mem_throttle_pipe_t; 2408232812Sjmallett 2409232812Sjmallett/** 2410215976Sjmallett * cvmx_pko_reg_bist_result 2411215976Sjmallett * 2412215976Sjmallett * Notes: 2413215976Sjmallett * Access to the internal BiST results 2414215976Sjmallett * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail). 2415215976Sjmallett */ 2416232812Sjmallettunion cvmx_pko_reg_bist_result { 2417215976Sjmallett uint64_t u64; 2418232812Sjmallett struct cvmx_pko_reg_bist_result_s { 2419232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2420215976Sjmallett uint64_t reserved_0_63 : 64; 2421215976Sjmallett#else 2422215976Sjmallett uint64_t reserved_0_63 : 64; 2423215976Sjmallett#endif 2424215976Sjmallett } s; 2425232812Sjmallett struct cvmx_pko_reg_bist_result_cn30xx { 2426232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2427215976Sjmallett uint64_t reserved_27_63 : 37; 2428215976Sjmallett uint64_t psb2 : 5; /**< BiST result of the PSB memories (0=pass, !0=fail) */ 2429215976Sjmallett uint64_t count : 1; /**< BiST result of the COUNT memories (0=pass, !0=fail) */ 2430215976Sjmallett uint64_t rif : 1; /**< BiST result of the RIF memories (0=pass, !0=fail) */ 2431215976Sjmallett uint64_t wif : 1; /**< BiST result of the WIF memories (0=pass, !0=fail) */ 2432215976Sjmallett uint64_t ncb : 1; /**< BiST result of the NCB memories (0=pass, !0=fail) */ 2433215976Sjmallett uint64_t out : 1; /**< BiST result of the OUT memories (0=pass, !0=fail) */ 2434215976Sjmallett uint64_t crc : 1; /**< BiST result of the CRC memories (0=pass, !0=fail) */ 2435215976Sjmallett uint64_t chk : 1; /**< BiST result of the CHK memories (0=pass, !0=fail) */ 2436215976Sjmallett uint64_t qsb : 2; /**< BiST result of the QSB memories (0=pass, !0=fail) */ 2437215976Sjmallett uint64_t qcb : 2; /**< BiST result of the QCB memories (0=pass, !0=fail) */ 2438215976Sjmallett uint64_t pdb : 4; /**< BiST result of the PDB memories (0=pass, !0=fail) */ 2439215976Sjmallett uint64_t psb : 7; /**< BiST result of the PSB memories (0=pass, !0=fail) */ 2440215976Sjmallett#else 2441215976Sjmallett uint64_t psb : 7; 2442215976Sjmallett uint64_t pdb : 4; 2443215976Sjmallett uint64_t qcb : 2; 2444215976Sjmallett uint64_t qsb : 2; 2445215976Sjmallett uint64_t chk : 1; 2446215976Sjmallett uint64_t crc : 1; 2447215976Sjmallett uint64_t out : 1; 2448215976Sjmallett uint64_t ncb : 1; 2449215976Sjmallett uint64_t wif : 1; 2450215976Sjmallett uint64_t rif : 1; 2451215976Sjmallett uint64_t count : 1; 2452215976Sjmallett uint64_t psb2 : 5; 2453215976Sjmallett uint64_t reserved_27_63 : 37; 2454215976Sjmallett#endif 2455215976Sjmallett } cn30xx; 2456215976Sjmallett struct cvmx_pko_reg_bist_result_cn30xx cn31xx; 2457215976Sjmallett struct cvmx_pko_reg_bist_result_cn30xx cn38xx; 2458215976Sjmallett struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2; 2459232812Sjmallett struct cvmx_pko_reg_bist_result_cn50xx { 2460232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2461215976Sjmallett uint64_t reserved_33_63 : 31; 2462215976Sjmallett uint64_t csr : 1; /**< BiST result of CSR memories (0=pass, !0=fail) */ 2463215976Sjmallett uint64_t iob : 1; /**< BiST result of IOB memories (0=pass, !0=fail) */ 2464215976Sjmallett uint64_t out_crc : 1; /**< BiST result of OUT_CRC memories (0=pass, !0=fail) */ 2465215976Sjmallett uint64_t out_ctl : 3; /**< BiST result of OUT_CTL memories (0=pass, !0=fail) */ 2466215976Sjmallett uint64_t out_sta : 1; /**< BiST result of OUT_STA memories (0=pass, !0=fail) */ 2467215976Sjmallett uint64_t out_wif : 1; /**< BiST result of OUT_WIF memories (0=pass, !0=fail) */ 2468215976Sjmallett uint64_t prt_chk : 3; /**< BiST result of PRT_CHK memories (0=pass, !0=fail) */ 2469215976Sjmallett uint64_t prt_nxt : 1; /**< BiST result of PRT_NXT memories (0=pass, !0=fail) */ 2470215976Sjmallett uint64_t prt_psb : 6; /**< BiST result of PRT_PSB memories (0=pass, !0=fail) */ 2471215976Sjmallett uint64_t ncb_inb : 2; /**< BiST result of NCB_INB memories (0=pass, !0=fail) */ 2472215976Sjmallett uint64_t prt_qcb : 2; /**< BiST result of PRT_QCB memories (0=pass, !0=fail) */ 2473215976Sjmallett uint64_t prt_qsb : 3; /**< BiST result of PRT_QSB memories (0=pass, !0=fail) */ 2474215976Sjmallett uint64_t dat_dat : 4; /**< BiST result of DAT_DAT memories (0=pass, !0=fail) */ 2475215976Sjmallett uint64_t dat_ptr : 4; /**< BiST result of DAT_PTR memories (0=pass, !0=fail) */ 2476215976Sjmallett#else 2477215976Sjmallett uint64_t dat_ptr : 4; 2478215976Sjmallett uint64_t dat_dat : 4; 2479215976Sjmallett uint64_t prt_qsb : 3; 2480215976Sjmallett uint64_t prt_qcb : 2; 2481215976Sjmallett uint64_t ncb_inb : 2; 2482215976Sjmallett uint64_t prt_psb : 6; 2483215976Sjmallett uint64_t prt_nxt : 1; 2484215976Sjmallett uint64_t prt_chk : 3; 2485215976Sjmallett uint64_t out_wif : 1; 2486215976Sjmallett uint64_t out_sta : 1; 2487215976Sjmallett uint64_t out_ctl : 3; 2488215976Sjmallett uint64_t out_crc : 1; 2489215976Sjmallett uint64_t iob : 1; 2490215976Sjmallett uint64_t csr : 1; 2491215976Sjmallett uint64_t reserved_33_63 : 31; 2492215976Sjmallett#endif 2493215976Sjmallett } cn50xx; 2494232812Sjmallett struct cvmx_pko_reg_bist_result_cn52xx { 2495232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2496215976Sjmallett uint64_t reserved_35_63 : 29; 2497215976Sjmallett uint64_t csr : 1; /**< BiST result of CSR memories (0=pass, !0=fail) */ 2498215976Sjmallett uint64_t iob : 1; /**< BiST result of IOB memories (0=pass, !0=fail) */ 2499215976Sjmallett uint64_t out_dat : 1; /**< BiST result of OUT_DAT memories (0=pass, !0=fail) */ 2500215976Sjmallett uint64_t out_ctl : 3; /**< BiST result of OUT_CTL memories (0=pass, !0=fail) */ 2501215976Sjmallett uint64_t out_sta : 1; /**< BiST result of OUT_STA memories (0=pass, !0=fail) */ 2502215976Sjmallett uint64_t out_wif : 1; /**< BiST result of OUT_WIF memories (0=pass, !0=fail) */ 2503215976Sjmallett uint64_t prt_chk : 3; /**< BiST result of PRT_CHK memories (0=pass, !0=fail) */ 2504215976Sjmallett uint64_t prt_nxt : 1; /**< BiST result of PRT_NXT memories (0=pass, !0=fail) */ 2505215976Sjmallett uint64_t prt_psb : 8; /**< BiST result of PRT_PSB memories (0=pass, !0=fail) */ 2506215976Sjmallett uint64_t ncb_inb : 2; /**< BiST result of NCB_INB memories (0=pass, !0=fail) */ 2507215976Sjmallett uint64_t prt_qcb : 2; /**< BiST result of PRT_QCB memories (0=pass, !0=fail) */ 2508215976Sjmallett uint64_t prt_qsb : 3; /**< BiST result of PRT_QSB memories (0=pass, !0=fail) */ 2509215976Sjmallett uint64_t prt_ctl : 2; /**< BiST result of PRT_CTL memories (0=pass, !0=fail) */ 2510215976Sjmallett uint64_t dat_dat : 2; /**< BiST result of DAT_DAT memories (0=pass, !0=fail) */ 2511215976Sjmallett uint64_t dat_ptr : 4; /**< BiST result of DAT_PTR memories (0=pass, !0=fail) */ 2512215976Sjmallett#else 2513215976Sjmallett uint64_t dat_ptr : 4; 2514215976Sjmallett uint64_t dat_dat : 2; 2515215976Sjmallett uint64_t prt_ctl : 2; 2516215976Sjmallett uint64_t prt_qsb : 3; 2517215976Sjmallett uint64_t prt_qcb : 2; 2518215976Sjmallett uint64_t ncb_inb : 2; 2519215976Sjmallett uint64_t prt_psb : 8; 2520215976Sjmallett uint64_t prt_nxt : 1; 2521215976Sjmallett uint64_t prt_chk : 3; 2522215976Sjmallett uint64_t out_wif : 1; 2523215976Sjmallett uint64_t out_sta : 1; 2524215976Sjmallett uint64_t out_ctl : 3; 2525215976Sjmallett uint64_t out_dat : 1; 2526215976Sjmallett uint64_t iob : 1; 2527215976Sjmallett uint64_t csr : 1; 2528215976Sjmallett uint64_t reserved_35_63 : 29; 2529215976Sjmallett#endif 2530215976Sjmallett } cn52xx; 2531215976Sjmallett struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1; 2532215976Sjmallett struct cvmx_pko_reg_bist_result_cn52xx cn56xx; 2533215976Sjmallett struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1; 2534215976Sjmallett struct cvmx_pko_reg_bist_result_cn50xx cn58xx; 2535215976Sjmallett struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1; 2536232812Sjmallett struct cvmx_pko_reg_bist_result_cn52xx cn61xx; 2537215976Sjmallett struct cvmx_pko_reg_bist_result_cn52xx cn63xx; 2538215976Sjmallett struct cvmx_pko_reg_bist_result_cn52xx cn63xxp1; 2539232812Sjmallett struct cvmx_pko_reg_bist_result_cn52xx cn66xx; 2540232812Sjmallett struct cvmx_pko_reg_bist_result_cn68xx { 2541232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2542232812Sjmallett uint64_t reserved_36_63 : 28; 2543232812Sjmallett uint64_t crc : 1; /**< BiST result of CRC memories (0=pass, !0=fail) */ 2544232812Sjmallett uint64_t csr : 1; /**< BiST result of CSR memories (0=pass, !0=fail) */ 2545232812Sjmallett uint64_t iob : 1; /**< BiST result of IOB memories (0=pass, !0=fail) */ 2546232812Sjmallett uint64_t out_dat : 1; /**< BiST result of OUT_DAT memories (0=pass, !0=fail) */ 2547232812Sjmallett uint64_t reserved_31_31 : 1; 2548232812Sjmallett uint64_t out_ctl : 2; /**< BiST result of OUT_CTL memories (0=pass, !0=fail) */ 2549232812Sjmallett uint64_t out_sta : 1; /**< BiST result of OUT_STA memories (0=pass, !0=fail) */ 2550232812Sjmallett uint64_t out_wif : 1; /**< BiST result of OUT_WIF memories (0=pass, !0=fail) */ 2551232812Sjmallett uint64_t prt_chk : 3; /**< BiST result of PRT_CHK memories (0=pass, !0=fail) */ 2552232812Sjmallett uint64_t prt_nxt : 1; /**< BiST result of PRT_NXT memories (0=pass, !0=fail) */ 2553232812Sjmallett uint64_t prt_psb7 : 1; /**< BiST result of PRT_PSB memories (0=pass, !0=fail) */ 2554232812Sjmallett uint64_t reserved_21_21 : 1; 2555232812Sjmallett uint64_t prt_psb : 6; /**< BiST result of PRT_PSB memories (0=pass, !0=fail) */ 2556232812Sjmallett uint64_t ncb_inb : 2; /**< BiST result of NCB_INB memories (0=pass, !0=fail) */ 2557232812Sjmallett uint64_t prt_qcb : 2; /**< BiST result of PRT_QCB memories (0=pass, !0=fail) */ 2558232812Sjmallett uint64_t prt_qsb : 3; /**< BiST result of PRT_QSB memories (0=pass, !0=fail) */ 2559232812Sjmallett uint64_t prt_ctl : 2; /**< BiST result of PRT_CTL memories (0=pass, !0=fail) */ 2560232812Sjmallett uint64_t dat_dat : 2; /**< BiST result of DAT_DAT memories (0=pass, !0=fail) */ 2561232812Sjmallett uint64_t dat_ptr : 4; /**< BiST result of DAT_PTR memories (0=pass, !0=fail) */ 2562232812Sjmallett#else 2563232812Sjmallett uint64_t dat_ptr : 4; 2564232812Sjmallett uint64_t dat_dat : 2; 2565232812Sjmallett uint64_t prt_ctl : 2; 2566232812Sjmallett uint64_t prt_qsb : 3; 2567232812Sjmallett uint64_t prt_qcb : 2; 2568232812Sjmallett uint64_t ncb_inb : 2; 2569232812Sjmallett uint64_t prt_psb : 6; 2570232812Sjmallett uint64_t reserved_21_21 : 1; 2571232812Sjmallett uint64_t prt_psb7 : 1; 2572232812Sjmallett uint64_t prt_nxt : 1; 2573232812Sjmallett uint64_t prt_chk : 3; 2574232812Sjmallett uint64_t out_wif : 1; 2575232812Sjmallett uint64_t out_sta : 1; 2576232812Sjmallett uint64_t out_ctl : 2; 2577232812Sjmallett uint64_t reserved_31_31 : 1; 2578232812Sjmallett uint64_t out_dat : 1; 2579232812Sjmallett uint64_t iob : 1; 2580232812Sjmallett uint64_t csr : 1; 2581232812Sjmallett uint64_t crc : 1; 2582232812Sjmallett uint64_t reserved_36_63 : 28; 2583232812Sjmallett#endif 2584232812Sjmallett } cn68xx; 2585232812Sjmallett struct cvmx_pko_reg_bist_result_cn68xxp1 { 2586232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2587232812Sjmallett uint64_t reserved_35_63 : 29; 2588232812Sjmallett uint64_t csr : 1; /**< BiST result of CSR memories (0=pass, !0=fail) */ 2589232812Sjmallett uint64_t iob : 1; /**< BiST result of IOB memories (0=pass, !0=fail) */ 2590232812Sjmallett uint64_t out_dat : 1; /**< BiST result of OUT_DAT memories (0=pass, !0=fail) */ 2591232812Sjmallett uint64_t reserved_31_31 : 1; 2592232812Sjmallett uint64_t out_ctl : 2; /**< BiST result of OUT_CTL memories (0=pass, !0=fail) */ 2593232812Sjmallett uint64_t out_sta : 1; /**< BiST result of OUT_STA memories (0=pass, !0=fail) */ 2594232812Sjmallett uint64_t out_wif : 1; /**< BiST result of OUT_WIF memories (0=pass, !0=fail) */ 2595232812Sjmallett uint64_t prt_chk : 3; /**< BiST result of PRT_CHK memories (0=pass, !0=fail) */ 2596232812Sjmallett uint64_t prt_nxt : 1; /**< BiST result of PRT_NXT memories (0=pass, !0=fail) */ 2597232812Sjmallett uint64_t prt_psb7 : 1; /**< BiST result of PRT_PSB memories (0=pass, !0=fail) */ 2598232812Sjmallett uint64_t reserved_21_21 : 1; 2599232812Sjmallett uint64_t prt_psb : 6; /**< BiST result of PRT_PSB memories (0=pass, !0=fail) */ 2600232812Sjmallett uint64_t ncb_inb : 2; /**< BiST result of NCB_INB memories (0=pass, !0=fail) */ 2601232812Sjmallett uint64_t prt_qcb : 2; /**< BiST result of PRT_QCB memories (0=pass, !0=fail) */ 2602232812Sjmallett uint64_t prt_qsb : 3; /**< BiST result of PRT_QSB memories (0=pass, !0=fail) */ 2603232812Sjmallett uint64_t prt_ctl : 2; /**< BiST result of PRT_CTL memories (0=pass, !0=fail) */ 2604232812Sjmallett uint64_t dat_dat : 2; /**< BiST result of DAT_DAT memories (0=pass, !0=fail) */ 2605232812Sjmallett uint64_t dat_ptr : 4; /**< BiST result of DAT_PTR memories (0=pass, !0=fail) */ 2606232812Sjmallett#else 2607232812Sjmallett uint64_t dat_ptr : 4; 2608232812Sjmallett uint64_t dat_dat : 2; 2609232812Sjmallett uint64_t prt_ctl : 2; 2610232812Sjmallett uint64_t prt_qsb : 3; 2611232812Sjmallett uint64_t prt_qcb : 2; 2612232812Sjmallett uint64_t ncb_inb : 2; 2613232812Sjmallett uint64_t prt_psb : 6; 2614232812Sjmallett uint64_t reserved_21_21 : 1; 2615232812Sjmallett uint64_t prt_psb7 : 1; 2616232812Sjmallett uint64_t prt_nxt : 1; 2617232812Sjmallett uint64_t prt_chk : 3; 2618232812Sjmallett uint64_t out_wif : 1; 2619232812Sjmallett uint64_t out_sta : 1; 2620232812Sjmallett uint64_t out_ctl : 2; 2621232812Sjmallett uint64_t reserved_31_31 : 1; 2622232812Sjmallett uint64_t out_dat : 1; 2623232812Sjmallett uint64_t iob : 1; 2624232812Sjmallett uint64_t csr : 1; 2625232812Sjmallett uint64_t reserved_35_63 : 29; 2626232812Sjmallett#endif 2627232812Sjmallett } cn68xxp1; 2628232812Sjmallett struct cvmx_pko_reg_bist_result_cn52xx cnf71xx; 2629215976Sjmallett}; 2630215976Sjmalletttypedef union cvmx_pko_reg_bist_result cvmx_pko_reg_bist_result_t; 2631215976Sjmallett 2632215976Sjmallett/** 2633215976Sjmallett * cvmx_pko_reg_cmd_buf 2634215976Sjmallett * 2635215976Sjmallett * Notes: 2636215976Sjmallett * Sets the command buffer parameters 2637215976Sjmallett * The size of the command buffer segments is measured in uint64s. The pool specifies (1 of 8 free 2638215976Sjmallett * lists to be used when freeing command buffer segments. 2639215976Sjmallett */ 2640232812Sjmallettunion cvmx_pko_reg_cmd_buf { 2641215976Sjmallett uint64_t u64; 2642232812Sjmallett struct cvmx_pko_reg_cmd_buf_s { 2643232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2644215976Sjmallett uint64_t reserved_23_63 : 41; 2645215976Sjmallett uint64_t pool : 3; /**< Free list used to free command buffer segments */ 2646215976Sjmallett uint64_t reserved_13_19 : 7; 2647215976Sjmallett uint64_t size : 13; /**< Number of uint64s per command buffer segment */ 2648215976Sjmallett#else 2649215976Sjmallett uint64_t size : 13; 2650215976Sjmallett uint64_t reserved_13_19 : 7; 2651215976Sjmallett uint64_t pool : 3; 2652215976Sjmallett uint64_t reserved_23_63 : 41; 2653215976Sjmallett#endif 2654215976Sjmallett } s; 2655215976Sjmallett struct cvmx_pko_reg_cmd_buf_s cn30xx; 2656215976Sjmallett struct cvmx_pko_reg_cmd_buf_s cn31xx; 2657215976Sjmallett struct cvmx_pko_reg_cmd_buf_s cn38xx; 2658215976Sjmallett struct cvmx_pko_reg_cmd_buf_s cn38xxp2; 2659215976Sjmallett struct cvmx_pko_reg_cmd_buf_s cn50xx; 2660215976Sjmallett struct cvmx_pko_reg_cmd_buf_s cn52xx; 2661215976Sjmallett struct cvmx_pko_reg_cmd_buf_s cn52xxp1; 2662215976Sjmallett struct cvmx_pko_reg_cmd_buf_s cn56xx; 2663215976Sjmallett struct cvmx_pko_reg_cmd_buf_s cn56xxp1; 2664215976Sjmallett struct cvmx_pko_reg_cmd_buf_s cn58xx; 2665215976Sjmallett struct cvmx_pko_reg_cmd_buf_s cn58xxp1; 2666232812Sjmallett struct cvmx_pko_reg_cmd_buf_s cn61xx; 2667215976Sjmallett struct cvmx_pko_reg_cmd_buf_s cn63xx; 2668215976Sjmallett struct cvmx_pko_reg_cmd_buf_s cn63xxp1; 2669232812Sjmallett struct cvmx_pko_reg_cmd_buf_s cn66xx; 2670232812Sjmallett struct cvmx_pko_reg_cmd_buf_s cn68xx; 2671232812Sjmallett struct cvmx_pko_reg_cmd_buf_s cn68xxp1; 2672232812Sjmallett struct cvmx_pko_reg_cmd_buf_s cnf71xx; 2673215976Sjmallett}; 2674215976Sjmalletttypedef union cvmx_pko_reg_cmd_buf cvmx_pko_reg_cmd_buf_t; 2675215976Sjmallett 2676215976Sjmallett/** 2677215976Sjmallett * cvmx_pko_reg_crc_ctl# 2678215976Sjmallett * 2679215976Sjmallett * Notes: 2680215976Sjmallett * Controls datapath reflection when calculating CRC 2681215976Sjmallett * 2682215976Sjmallett */ 2683232812Sjmallettunion cvmx_pko_reg_crc_ctlx { 2684215976Sjmallett uint64_t u64; 2685232812Sjmallett struct cvmx_pko_reg_crc_ctlx_s { 2686232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2687215976Sjmallett uint64_t reserved_2_63 : 62; 2688215976Sjmallett uint64_t invres : 1; /**< Invert the result */ 2689215976Sjmallett uint64_t refin : 1; /**< Reflect the bits in each byte. 2690215976Sjmallett Byte order does not change. 2691215976Sjmallett - 0: CRC is calculated MSB to LSB 2692215976Sjmallett - 1: CRC is calculated MLB to MSB */ 2693215976Sjmallett#else 2694215976Sjmallett uint64_t refin : 1; 2695215976Sjmallett uint64_t invres : 1; 2696215976Sjmallett uint64_t reserved_2_63 : 62; 2697215976Sjmallett#endif 2698215976Sjmallett } s; 2699215976Sjmallett struct cvmx_pko_reg_crc_ctlx_s cn38xx; 2700215976Sjmallett struct cvmx_pko_reg_crc_ctlx_s cn38xxp2; 2701215976Sjmallett struct cvmx_pko_reg_crc_ctlx_s cn58xx; 2702215976Sjmallett struct cvmx_pko_reg_crc_ctlx_s cn58xxp1; 2703215976Sjmallett}; 2704215976Sjmalletttypedef union cvmx_pko_reg_crc_ctlx cvmx_pko_reg_crc_ctlx_t; 2705215976Sjmallett 2706215976Sjmallett/** 2707215976Sjmallett * cvmx_pko_reg_crc_enable 2708215976Sjmallett * 2709215976Sjmallett * Notes: 2710215976Sjmallett * Enables CRC for the GMX ports. 2711215976Sjmallett * 2712215976Sjmallett */ 2713232812Sjmallettunion cvmx_pko_reg_crc_enable { 2714215976Sjmallett uint64_t u64; 2715232812Sjmallett struct cvmx_pko_reg_crc_enable_s { 2716232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2717215976Sjmallett uint64_t reserved_32_63 : 32; 2718215976Sjmallett uint64_t enable : 32; /**< Mask for ports 31-0 to enable CRC 2719215976Sjmallett Mask bit==0 means CRC not enabled 2720215976Sjmallett Mask bit==1 means CRC enabled 2721215976Sjmallett Note that CRC should be enabled only when using SPI4.2 */ 2722215976Sjmallett#else 2723215976Sjmallett uint64_t enable : 32; 2724215976Sjmallett uint64_t reserved_32_63 : 32; 2725215976Sjmallett#endif 2726215976Sjmallett } s; 2727215976Sjmallett struct cvmx_pko_reg_crc_enable_s cn38xx; 2728215976Sjmallett struct cvmx_pko_reg_crc_enable_s cn38xxp2; 2729215976Sjmallett struct cvmx_pko_reg_crc_enable_s cn58xx; 2730215976Sjmallett struct cvmx_pko_reg_crc_enable_s cn58xxp1; 2731215976Sjmallett}; 2732215976Sjmalletttypedef union cvmx_pko_reg_crc_enable cvmx_pko_reg_crc_enable_t; 2733215976Sjmallett 2734215976Sjmallett/** 2735215976Sjmallett * cvmx_pko_reg_crc_iv# 2736215976Sjmallett * 2737215976Sjmallett * Notes: 2738215976Sjmallett * Determines the IV used by the CRC algorithm 2739215976Sjmallett * * PKO_CRC_IV 2740215976Sjmallett * PKO_CRC_IV controls the initial state of the CRC algorithm. Octane can 2741215976Sjmallett * support a wide range of CRC algorithms and as such, the IV must be 2742215976Sjmallett * carefully constructed to meet the specific algorithm. The code below 2743215976Sjmallett * determines the value to program into Octane based on the algorthim's IV 2744215976Sjmallett * and width. In the case of Octane, the width should always be 32. 2745215976Sjmallett * 2746215976Sjmallett * PKO_CRC_IV0 sets the IV for ports 0-15 while PKO_CRC_IV1 sets the IV for 2747215976Sjmallett * ports 16-31. 2748215976Sjmallett * 2749215976Sjmallett * @verbatim 2750215976Sjmallett * unsigned octane_crc_iv(unsigned algorithm_iv, unsigned poly, unsigned w) 2751215976Sjmallett * [ 2752215976Sjmallett * int i; 2753215976Sjmallett * int doit; 2754215976Sjmallett * unsigned int current_val = algorithm_iv; 2755215976Sjmallett * 2756215976Sjmallett * for(i = 0; i < w; i++) [ 2757215976Sjmallett * doit = current_val & 0x1; 2758215976Sjmallett * 2759215976Sjmallett * if(doit) current_val ^= poly; 2760215976Sjmallett * assert(!(current_val & 0x1)); 2761215976Sjmallett * 2762215976Sjmallett * current_val = (current_val >> 1) | (doit << (w-1)); 2763215976Sjmallett * ] 2764215976Sjmallett * 2765215976Sjmallett * return current_val; 2766215976Sjmallett * ] 2767215976Sjmallett * @endverbatim 2768215976Sjmallett */ 2769232812Sjmallettunion cvmx_pko_reg_crc_ivx { 2770215976Sjmallett uint64_t u64; 2771232812Sjmallett struct cvmx_pko_reg_crc_ivx_s { 2772232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2773215976Sjmallett uint64_t reserved_32_63 : 32; 2774215976Sjmallett uint64_t iv : 32; /**< IV used by the CRC algorithm. Default is FCS32. */ 2775215976Sjmallett#else 2776215976Sjmallett uint64_t iv : 32; 2777215976Sjmallett uint64_t reserved_32_63 : 32; 2778215976Sjmallett#endif 2779215976Sjmallett } s; 2780215976Sjmallett struct cvmx_pko_reg_crc_ivx_s cn38xx; 2781215976Sjmallett struct cvmx_pko_reg_crc_ivx_s cn38xxp2; 2782215976Sjmallett struct cvmx_pko_reg_crc_ivx_s cn58xx; 2783215976Sjmallett struct cvmx_pko_reg_crc_ivx_s cn58xxp1; 2784215976Sjmallett}; 2785215976Sjmalletttypedef union cvmx_pko_reg_crc_ivx cvmx_pko_reg_crc_ivx_t; 2786215976Sjmallett 2787215976Sjmallett/** 2788215976Sjmallett * cvmx_pko_reg_debug0 2789215976Sjmallett * 2790215976Sjmallett * Notes: 2791215976Sjmallett * Note that this CSR is present only in chip revisions beginning with pass2. 2792215976Sjmallett * 2793215976Sjmallett */ 2794232812Sjmallettunion cvmx_pko_reg_debug0 { 2795215976Sjmallett uint64_t u64; 2796232812Sjmallett struct cvmx_pko_reg_debug0_s { 2797232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2798215976Sjmallett uint64_t asserts : 64; /**< Various assertion checks */ 2799215976Sjmallett#else 2800215976Sjmallett uint64_t asserts : 64; 2801215976Sjmallett#endif 2802215976Sjmallett } s; 2803232812Sjmallett struct cvmx_pko_reg_debug0_cn30xx { 2804232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2805215976Sjmallett uint64_t reserved_17_63 : 47; 2806215976Sjmallett uint64_t asserts : 17; /**< Various assertion checks */ 2807215976Sjmallett#else 2808215976Sjmallett uint64_t asserts : 17; 2809215976Sjmallett uint64_t reserved_17_63 : 47; 2810215976Sjmallett#endif 2811215976Sjmallett } cn30xx; 2812215976Sjmallett struct cvmx_pko_reg_debug0_cn30xx cn31xx; 2813215976Sjmallett struct cvmx_pko_reg_debug0_cn30xx cn38xx; 2814215976Sjmallett struct cvmx_pko_reg_debug0_cn30xx cn38xxp2; 2815215976Sjmallett struct cvmx_pko_reg_debug0_s cn50xx; 2816215976Sjmallett struct cvmx_pko_reg_debug0_s cn52xx; 2817215976Sjmallett struct cvmx_pko_reg_debug0_s cn52xxp1; 2818215976Sjmallett struct cvmx_pko_reg_debug0_s cn56xx; 2819215976Sjmallett struct cvmx_pko_reg_debug0_s cn56xxp1; 2820215976Sjmallett struct cvmx_pko_reg_debug0_s cn58xx; 2821215976Sjmallett struct cvmx_pko_reg_debug0_s cn58xxp1; 2822232812Sjmallett struct cvmx_pko_reg_debug0_s cn61xx; 2823215976Sjmallett struct cvmx_pko_reg_debug0_s cn63xx; 2824215976Sjmallett struct cvmx_pko_reg_debug0_s cn63xxp1; 2825232812Sjmallett struct cvmx_pko_reg_debug0_s cn66xx; 2826232812Sjmallett struct cvmx_pko_reg_debug0_s cn68xx; 2827232812Sjmallett struct cvmx_pko_reg_debug0_s cn68xxp1; 2828232812Sjmallett struct cvmx_pko_reg_debug0_s cnf71xx; 2829215976Sjmallett}; 2830215976Sjmalletttypedef union cvmx_pko_reg_debug0 cvmx_pko_reg_debug0_t; 2831215976Sjmallett 2832215976Sjmallett/** 2833215976Sjmallett * cvmx_pko_reg_debug1 2834215976Sjmallett */ 2835232812Sjmallettunion cvmx_pko_reg_debug1 { 2836215976Sjmallett uint64_t u64; 2837232812Sjmallett struct cvmx_pko_reg_debug1_s { 2838232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2839215976Sjmallett uint64_t asserts : 64; /**< Various assertion checks */ 2840215976Sjmallett#else 2841215976Sjmallett uint64_t asserts : 64; 2842215976Sjmallett#endif 2843215976Sjmallett } s; 2844215976Sjmallett struct cvmx_pko_reg_debug1_s cn50xx; 2845215976Sjmallett struct cvmx_pko_reg_debug1_s cn52xx; 2846215976Sjmallett struct cvmx_pko_reg_debug1_s cn52xxp1; 2847215976Sjmallett struct cvmx_pko_reg_debug1_s cn56xx; 2848215976Sjmallett struct cvmx_pko_reg_debug1_s cn56xxp1; 2849215976Sjmallett struct cvmx_pko_reg_debug1_s cn58xx; 2850215976Sjmallett struct cvmx_pko_reg_debug1_s cn58xxp1; 2851232812Sjmallett struct cvmx_pko_reg_debug1_s cn61xx; 2852215976Sjmallett struct cvmx_pko_reg_debug1_s cn63xx; 2853215976Sjmallett struct cvmx_pko_reg_debug1_s cn63xxp1; 2854232812Sjmallett struct cvmx_pko_reg_debug1_s cn66xx; 2855232812Sjmallett struct cvmx_pko_reg_debug1_s cn68xx; 2856232812Sjmallett struct cvmx_pko_reg_debug1_s cn68xxp1; 2857232812Sjmallett struct cvmx_pko_reg_debug1_s cnf71xx; 2858215976Sjmallett}; 2859215976Sjmalletttypedef union cvmx_pko_reg_debug1 cvmx_pko_reg_debug1_t; 2860215976Sjmallett 2861215976Sjmallett/** 2862215976Sjmallett * cvmx_pko_reg_debug2 2863215976Sjmallett */ 2864232812Sjmallettunion cvmx_pko_reg_debug2 { 2865215976Sjmallett uint64_t u64; 2866232812Sjmallett struct cvmx_pko_reg_debug2_s { 2867232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2868215976Sjmallett uint64_t asserts : 64; /**< Various assertion checks */ 2869215976Sjmallett#else 2870215976Sjmallett uint64_t asserts : 64; 2871215976Sjmallett#endif 2872215976Sjmallett } s; 2873215976Sjmallett struct cvmx_pko_reg_debug2_s cn50xx; 2874215976Sjmallett struct cvmx_pko_reg_debug2_s cn52xx; 2875215976Sjmallett struct cvmx_pko_reg_debug2_s cn52xxp1; 2876215976Sjmallett struct cvmx_pko_reg_debug2_s cn56xx; 2877215976Sjmallett struct cvmx_pko_reg_debug2_s cn56xxp1; 2878215976Sjmallett struct cvmx_pko_reg_debug2_s cn58xx; 2879215976Sjmallett struct cvmx_pko_reg_debug2_s cn58xxp1; 2880232812Sjmallett struct cvmx_pko_reg_debug2_s cn61xx; 2881215976Sjmallett struct cvmx_pko_reg_debug2_s cn63xx; 2882215976Sjmallett struct cvmx_pko_reg_debug2_s cn63xxp1; 2883232812Sjmallett struct cvmx_pko_reg_debug2_s cn66xx; 2884232812Sjmallett struct cvmx_pko_reg_debug2_s cn68xx; 2885232812Sjmallett struct cvmx_pko_reg_debug2_s cn68xxp1; 2886232812Sjmallett struct cvmx_pko_reg_debug2_s cnf71xx; 2887215976Sjmallett}; 2888215976Sjmalletttypedef union cvmx_pko_reg_debug2 cvmx_pko_reg_debug2_t; 2889215976Sjmallett 2890215976Sjmallett/** 2891215976Sjmallett * cvmx_pko_reg_debug3 2892215976Sjmallett */ 2893232812Sjmallettunion cvmx_pko_reg_debug3 { 2894215976Sjmallett uint64_t u64; 2895232812Sjmallett struct cvmx_pko_reg_debug3_s { 2896232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2897215976Sjmallett uint64_t asserts : 64; /**< Various assertion checks */ 2898215976Sjmallett#else 2899215976Sjmallett uint64_t asserts : 64; 2900215976Sjmallett#endif 2901215976Sjmallett } s; 2902215976Sjmallett struct cvmx_pko_reg_debug3_s cn50xx; 2903215976Sjmallett struct cvmx_pko_reg_debug3_s cn52xx; 2904215976Sjmallett struct cvmx_pko_reg_debug3_s cn52xxp1; 2905215976Sjmallett struct cvmx_pko_reg_debug3_s cn56xx; 2906215976Sjmallett struct cvmx_pko_reg_debug3_s cn56xxp1; 2907215976Sjmallett struct cvmx_pko_reg_debug3_s cn58xx; 2908215976Sjmallett struct cvmx_pko_reg_debug3_s cn58xxp1; 2909232812Sjmallett struct cvmx_pko_reg_debug3_s cn61xx; 2910215976Sjmallett struct cvmx_pko_reg_debug3_s cn63xx; 2911215976Sjmallett struct cvmx_pko_reg_debug3_s cn63xxp1; 2912232812Sjmallett struct cvmx_pko_reg_debug3_s cn66xx; 2913232812Sjmallett struct cvmx_pko_reg_debug3_s cn68xx; 2914232812Sjmallett struct cvmx_pko_reg_debug3_s cn68xxp1; 2915232812Sjmallett struct cvmx_pko_reg_debug3_s cnf71xx; 2916215976Sjmallett}; 2917215976Sjmalletttypedef union cvmx_pko_reg_debug3 cvmx_pko_reg_debug3_t; 2918215976Sjmallett 2919215976Sjmallett/** 2920232812Sjmallett * cvmx_pko_reg_debug4 2921232812Sjmallett */ 2922232812Sjmallettunion cvmx_pko_reg_debug4 { 2923232812Sjmallett uint64_t u64; 2924232812Sjmallett struct cvmx_pko_reg_debug4_s { 2925232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2926232812Sjmallett uint64_t asserts : 64; /**< Various assertion checks */ 2927232812Sjmallett#else 2928232812Sjmallett uint64_t asserts : 64; 2929232812Sjmallett#endif 2930232812Sjmallett } s; 2931232812Sjmallett struct cvmx_pko_reg_debug4_s cn68xx; 2932232812Sjmallett struct cvmx_pko_reg_debug4_s cn68xxp1; 2933232812Sjmallett}; 2934232812Sjmalletttypedef union cvmx_pko_reg_debug4 cvmx_pko_reg_debug4_t; 2935232812Sjmallett 2936232812Sjmallett/** 2937215976Sjmallett * cvmx_pko_reg_engine_inflight 2938215976Sjmallett * 2939215976Sjmallett * Notes: 2940215976Sjmallett * Sets the maximum number of inflight packets, per engine. Values greater than 4 are illegal. 2941215976Sjmallett * Setting an engine's value to 0 effectively stops the engine. 2942215976Sjmallett */ 2943232812Sjmallettunion cvmx_pko_reg_engine_inflight { 2944215976Sjmallett uint64_t u64; 2945232812Sjmallett struct cvmx_pko_reg_engine_inflight_s { 2946232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2947232812Sjmallett uint64_t engine15 : 4; /**< Maximum number of inflight packets for engine15 */ 2948232812Sjmallett uint64_t engine14 : 4; /**< Maximum number of inflight packets for engine14 */ 2949232812Sjmallett uint64_t engine13 : 4; /**< Maximum number of inflight packets for engine13 */ 2950232812Sjmallett uint64_t engine12 : 4; /**< Maximum number of inflight packets for engine12 */ 2951215976Sjmallett uint64_t engine11 : 4; /**< Maximum number of inflight packets for engine11 */ 2952215976Sjmallett uint64_t engine10 : 4; /**< Maximum number of inflight packets for engine10 */ 2953215976Sjmallett uint64_t engine9 : 4; /**< Maximum number of inflight packets for engine9 */ 2954215976Sjmallett uint64_t engine8 : 4; /**< Maximum number of inflight packets for engine8 */ 2955232812Sjmallett uint64_t engine7 : 4; /**< Maximum number of inflight packets for engine7 */ 2956232812Sjmallett uint64_t engine6 : 4; /**< Maximum number of inflight packets for engine6 */ 2957232812Sjmallett uint64_t engine5 : 4; /**< Maximum number of inflight packets for engine5 */ 2958232812Sjmallett uint64_t engine4 : 4; /**< Maximum number of inflight packets for engine4 */ 2959215976Sjmallett uint64_t engine3 : 4; /**< Maximum number of inflight packets for engine3 */ 2960215976Sjmallett uint64_t engine2 : 4; /**< Maximum number of inflight packets for engine2 */ 2961215976Sjmallett uint64_t engine1 : 4; /**< Maximum number of inflight packets for engine1 */ 2962215976Sjmallett uint64_t engine0 : 4; /**< Maximum number of inflight packets for engine0 */ 2963215976Sjmallett#else 2964215976Sjmallett uint64_t engine0 : 4; 2965215976Sjmallett uint64_t engine1 : 4; 2966215976Sjmallett uint64_t engine2 : 4; 2967215976Sjmallett uint64_t engine3 : 4; 2968215976Sjmallett uint64_t engine4 : 4; 2969215976Sjmallett uint64_t engine5 : 4; 2970215976Sjmallett uint64_t engine6 : 4; 2971215976Sjmallett uint64_t engine7 : 4; 2972215976Sjmallett uint64_t engine8 : 4; 2973215976Sjmallett uint64_t engine9 : 4; 2974215976Sjmallett uint64_t engine10 : 4; 2975215976Sjmallett uint64_t engine11 : 4; 2976232812Sjmallett uint64_t engine12 : 4; 2977232812Sjmallett uint64_t engine13 : 4; 2978232812Sjmallett uint64_t engine14 : 4; 2979232812Sjmallett uint64_t engine15 : 4; 2980215976Sjmallett#endif 2981215976Sjmallett } s; 2982232812Sjmallett struct cvmx_pko_reg_engine_inflight_cn52xx { 2983232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2984215976Sjmallett uint64_t reserved_40_63 : 24; 2985215976Sjmallett uint64_t engine9 : 4; /**< Maximum number of inflight packets for engine9 */ 2986215976Sjmallett uint64_t engine8 : 4; /**< Maximum number of inflight packets for engine8 */ 2987215976Sjmallett uint64_t engine7 : 4; /**< MBZ */ 2988215976Sjmallett uint64_t engine6 : 4; /**< MBZ */ 2989215976Sjmallett uint64_t engine5 : 4; /**< MBZ */ 2990215976Sjmallett uint64_t engine4 : 4; /**< MBZ */ 2991215976Sjmallett uint64_t engine3 : 4; /**< Maximum number of inflight packets for engine3 */ 2992215976Sjmallett uint64_t engine2 : 4; /**< Maximum number of inflight packets for engine2 */ 2993215976Sjmallett uint64_t engine1 : 4; /**< Maximum number of inflight packets for engine1 */ 2994215976Sjmallett uint64_t engine0 : 4; /**< Maximum number of inflight packets for engine0 */ 2995215976Sjmallett#else 2996215976Sjmallett uint64_t engine0 : 4; 2997215976Sjmallett uint64_t engine1 : 4; 2998215976Sjmallett uint64_t engine2 : 4; 2999215976Sjmallett uint64_t engine3 : 4; 3000215976Sjmallett uint64_t engine4 : 4; 3001215976Sjmallett uint64_t engine5 : 4; 3002215976Sjmallett uint64_t engine6 : 4; 3003215976Sjmallett uint64_t engine7 : 4; 3004215976Sjmallett uint64_t engine8 : 4; 3005215976Sjmallett uint64_t engine9 : 4; 3006215976Sjmallett uint64_t reserved_40_63 : 24; 3007215976Sjmallett#endif 3008215976Sjmallett } cn52xx; 3009215976Sjmallett struct cvmx_pko_reg_engine_inflight_cn52xx cn52xxp1; 3010215976Sjmallett struct cvmx_pko_reg_engine_inflight_cn52xx cn56xx; 3011215976Sjmallett struct cvmx_pko_reg_engine_inflight_cn52xx cn56xxp1; 3012232812Sjmallett struct cvmx_pko_reg_engine_inflight_cn61xx { 3013232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3014232812Sjmallett uint64_t reserved_56_63 : 8; 3015232812Sjmallett uint64_t engine13 : 4; /**< Maximum number of inflight packets for engine13 */ 3016232812Sjmallett uint64_t engine12 : 4; /**< Maximum number of inflight packets for engine12 */ 3017232812Sjmallett uint64_t engine11 : 4; /**< Maximum number of inflight packets for engine11 */ 3018232812Sjmallett uint64_t engine10 : 4; /**< Maximum number of inflight packets for engine10 */ 3019232812Sjmallett uint64_t engine9 : 4; /**< Maximum number of inflight packets for engine9 */ 3020232812Sjmallett uint64_t engine8 : 4; /**< Maximum number of inflight packets for engine8 */ 3021232812Sjmallett uint64_t engine7 : 4; /**< Maximum number of inflight packets for engine7 */ 3022232812Sjmallett uint64_t engine6 : 4; /**< Maximum number of inflight packets for engine6 */ 3023232812Sjmallett uint64_t engine5 : 4; /**< Maximum number of inflight packets for engine5 */ 3024232812Sjmallett uint64_t engine4 : 4; /**< Maximum number of inflight packets for engine4 */ 3025232812Sjmallett uint64_t engine3 : 4; /**< Maximum number of inflight packets for engine3 */ 3026232812Sjmallett uint64_t engine2 : 4; /**< Maximum number of inflight packets for engine2 */ 3027232812Sjmallett uint64_t engine1 : 4; /**< Maximum number of inflight packets for engine1 */ 3028232812Sjmallett uint64_t engine0 : 4; /**< Maximum number of inflight packets for engine0 */ 3029232812Sjmallett#else 3030232812Sjmallett uint64_t engine0 : 4; 3031232812Sjmallett uint64_t engine1 : 4; 3032232812Sjmallett uint64_t engine2 : 4; 3033232812Sjmallett uint64_t engine3 : 4; 3034232812Sjmallett uint64_t engine4 : 4; 3035232812Sjmallett uint64_t engine5 : 4; 3036232812Sjmallett uint64_t engine6 : 4; 3037232812Sjmallett uint64_t engine7 : 4; 3038232812Sjmallett uint64_t engine8 : 4; 3039232812Sjmallett uint64_t engine9 : 4; 3040232812Sjmallett uint64_t engine10 : 4; 3041232812Sjmallett uint64_t engine11 : 4; 3042232812Sjmallett uint64_t engine12 : 4; 3043232812Sjmallett uint64_t engine13 : 4; 3044232812Sjmallett uint64_t reserved_56_63 : 8; 3045232812Sjmallett#endif 3046232812Sjmallett } cn61xx; 3047232812Sjmallett struct cvmx_pko_reg_engine_inflight_cn63xx { 3048232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3049232812Sjmallett uint64_t reserved_48_63 : 16; 3050232812Sjmallett uint64_t engine11 : 4; /**< Maximum number of inflight packets for engine11 */ 3051232812Sjmallett uint64_t engine10 : 4; /**< Maximum number of inflight packets for engine10 */ 3052232812Sjmallett uint64_t engine9 : 4; /**< Maximum number of inflight packets for engine9 */ 3053232812Sjmallett uint64_t engine8 : 4; /**< Maximum number of inflight packets for engine8 */ 3054232812Sjmallett uint64_t engine7 : 4; /**< MBZ */ 3055232812Sjmallett uint64_t engine6 : 4; /**< MBZ */ 3056232812Sjmallett uint64_t engine5 : 4; /**< MBZ */ 3057232812Sjmallett uint64_t engine4 : 4; /**< MBZ */ 3058232812Sjmallett uint64_t engine3 : 4; /**< Maximum number of inflight packets for engine3 */ 3059232812Sjmallett uint64_t engine2 : 4; /**< Maximum number of inflight packets for engine2 */ 3060232812Sjmallett uint64_t engine1 : 4; /**< Maximum number of inflight packets for engine1 */ 3061232812Sjmallett uint64_t engine0 : 4; /**< Maximum number of inflight packets for engine0 */ 3062232812Sjmallett#else 3063232812Sjmallett uint64_t engine0 : 4; 3064232812Sjmallett uint64_t engine1 : 4; 3065232812Sjmallett uint64_t engine2 : 4; 3066232812Sjmallett uint64_t engine3 : 4; 3067232812Sjmallett uint64_t engine4 : 4; 3068232812Sjmallett uint64_t engine5 : 4; 3069232812Sjmallett uint64_t engine6 : 4; 3070232812Sjmallett uint64_t engine7 : 4; 3071232812Sjmallett uint64_t engine8 : 4; 3072232812Sjmallett uint64_t engine9 : 4; 3073232812Sjmallett uint64_t engine10 : 4; 3074232812Sjmallett uint64_t engine11 : 4; 3075232812Sjmallett uint64_t reserved_48_63 : 16; 3076232812Sjmallett#endif 3077232812Sjmallett } cn63xx; 3078232812Sjmallett struct cvmx_pko_reg_engine_inflight_cn63xx cn63xxp1; 3079232812Sjmallett struct cvmx_pko_reg_engine_inflight_cn61xx cn66xx; 3080232812Sjmallett struct cvmx_pko_reg_engine_inflight_s cn68xx; 3081232812Sjmallett struct cvmx_pko_reg_engine_inflight_s cn68xxp1; 3082232812Sjmallett struct cvmx_pko_reg_engine_inflight_cn61xx cnf71xx; 3083215976Sjmallett}; 3084215976Sjmalletttypedef union cvmx_pko_reg_engine_inflight cvmx_pko_reg_engine_inflight_t; 3085215976Sjmallett 3086215976Sjmallett/** 3087232812Sjmallett * cvmx_pko_reg_engine_inflight1 3088232812Sjmallett * 3089232812Sjmallett * Notes: 3090232812Sjmallett * Sets the maximum number of inflight packets, per engine. Values greater than 8 are illegal. 3091232812Sjmallett * Setting an engine's value to 0 effectively stops the engine. 3092232812Sjmallett */ 3093232812Sjmallettunion cvmx_pko_reg_engine_inflight1 { 3094232812Sjmallett uint64_t u64; 3095232812Sjmallett struct cvmx_pko_reg_engine_inflight1_s { 3096232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3097232812Sjmallett uint64_t reserved_16_63 : 48; 3098232812Sjmallett uint64_t engine19 : 4; /**< Maximum number of inflight packets for engine19 */ 3099232812Sjmallett uint64_t engine18 : 4; /**< Maximum number of inflight packets for engine18 */ 3100232812Sjmallett uint64_t engine17 : 4; /**< Maximum number of inflight packets for engine17 */ 3101232812Sjmallett uint64_t engine16 : 4; /**< Maximum number of inflight packets for engine16 */ 3102232812Sjmallett#else 3103232812Sjmallett uint64_t engine16 : 4; 3104232812Sjmallett uint64_t engine17 : 4; 3105232812Sjmallett uint64_t engine18 : 4; 3106232812Sjmallett uint64_t engine19 : 4; 3107232812Sjmallett uint64_t reserved_16_63 : 48; 3108232812Sjmallett#endif 3109232812Sjmallett } s; 3110232812Sjmallett struct cvmx_pko_reg_engine_inflight1_s cn68xx; 3111232812Sjmallett struct cvmx_pko_reg_engine_inflight1_s cn68xxp1; 3112232812Sjmallett}; 3113232812Sjmalletttypedef union cvmx_pko_reg_engine_inflight1 cvmx_pko_reg_engine_inflight1_t; 3114232812Sjmallett 3115232812Sjmallett/** 3116232812Sjmallett * cvmx_pko_reg_engine_storage# 3117232812Sjmallett * 3118232812Sjmallett * Notes: 3119232812Sjmallett * The PKO has 40KB of local storage, consisting of 20, 2KB chunks. Up to 15 contiguous chunks may be mapped per engine. 3120232812Sjmallett * The total of all mapped storage must not exceed 40KB. 3121232812Sjmallett */ 3122232812Sjmallettunion cvmx_pko_reg_engine_storagex { 3123232812Sjmallett uint64_t u64; 3124232812Sjmallett struct cvmx_pko_reg_engine_storagex_s { 3125232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3126232812Sjmallett uint64_t engine15 : 4; /**< Number of contiguous 2KB chunks allocated to 3127232812Sjmallett engine (X * 16) + 15. 3128232812Sjmallett ENGINE15 does not exist and is reserved in 3129232812Sjmallett PKO_REG_ENGINE_STORAGE1. */ 3130232812Sjmallett uint64_t engine14 : 4; /**< Number of contiguous 2KB chunks allocated to 3131232812Sjmallett engine (X * 16) + 14. 3132232812Sjmallett ENGINE14 does not exist and is reserved in 3133232812Sjmallett PKO_REG_ENGINE_STORAGE1. */ 3134232812Sjmallett uint64_t engine13 : 4; /**< Number of contiguous 2KB chunks allocated to 3135232812Sjmallett engine (X * 16) + 13. 3136232812Sjmallett ENGINE13 does not exist and is reserved in 3137232812Sjmallett PKO_REG_ENGINE_STORAGE1. */ 3138232812Sjmallett uint64_t engine12 : 4; /**< Number of contiguous 2KB chunks allocated to 3139232812Sjmallett engine (X * 16) + 12. 3140232812Sjmallett ENGINE12 does not exist and is reserved in 3141232812Sjmallett PKO_REG_ENGINE_STORAGE1. */ 3142232812Sjmallett uint64_t engine11 : 4; /**< Number of contiguous 2KB chunks allocated to 3143232812Sjmallett engine (X * 16) + 11. 3144232812Sjmallett ENGINE11 does not exist and is reserved in 3145232812Sjmallett PKO_REG_ENGINE_STORAGE1. */ 3146232812Sjmallett uint64_t engine10 : 4; /**< Number of contiguous 2KB chunks allocated to 3147232812Sjmallett engine (X * 16) + 10. 3148232812Sjmallett ENGINE10 does not exist and is reserved in 3149232812Sjmallett PKO_REG_ENGINE_STORAGE1. */ 3150232812Sjmallett uint64_t engine9 : 4; /**< Number of contiguous 2KB chunks allocated to 3151232812Sjmallett engine (X * 16) + 9. 3152232812Sjmallett ENGINE9 does not exist and is reserved in 3153232812Sjmallett PKO_REG_ENGINE_STORAGE1. */ 3154232812Sjmallett uint64_t engine8 : 4; /**< Number of contiguous 2KB chunks allocated to 3155232812Sjmallett engine (X * 16) + 8. 3156232812Sjmallett ENGINE8 does not exist and is reserved in 3157232812Sjmallett PKO_REG_ENGINE_STORAGE1. */ 3158232812Sjmallett uint64_t engine7 : 4; /**< Number of contiguous 2KB chunks allocated to 3159232812Sjmallett engine (X * 16) + 7. 3160232812Sjmallett ENGINE7 does not exist and is reserved in 3161232812Sjmallett PKO_REG_ENGINE_STORAGE1. */ 3162232812Sjmallett uint64_t engine6 : 4; /**< Number of contiguous 2KB chunks allocated to 3163232812Sjmallett engine (X * 16) + 6. 3164232812Sjmallett ENGINE6 does not exist and is reserved in 3165232812Sjmallett PKO_REG_ENGINE_STORAGE1. */ 3166232812Sjmallett uint64_t engine5 : 4; /**< Number of contiguous 2KB chunks allocated to 3167232812Sjmallett engine (X * 16) + 5. 3168232812Sjmallett ENGINE5 does not exist and is reserved in 3169232812Sjmallett PKO_REG_ENGINE_STORAGE1. */ 3170232812Sjmallett uint64_t engine4 : 4; /**< Number of contiguous 2KB chunks allocated to 3171232812Sjmallett engine (X * 16) + 4. 3172232812Sjmallett ENGINE4 does not exist and is reserved in 3173232812Sjmallett PKO_REG_ENGINE_STORAGE1. */ 3174232812Sjmallett uint64_t engine3 : 4; /**< Number of contiguous 2KB chunks allocated to 3175232812Sjmallett engine (X * 16) + 3. */ 3176232812Sjmallett uint64_t engine2 : 4; /**< Number of contiguous 2KB chunks allocated to 3177232812Sjmallett engine (X * 16) + 2. */ 3178232812Sjmallett uint64_t engine1 : 4; /**< Number of contiguous 2KB chunks allocated to 3179232812Sjmallett engine (X * 16) + 1. */ 3180232812Sjmallett uint64_t engine0 : 4; /**< Number of contiguous 2KB chunks allocated to 3181232812Sjmallett engine (X * 16) + 0. */ 3182232812Sjmallett#else 3183232812Sjmallett uint64_t engine0 : 4; 3184232812Sjmallett uint64_t engine1 : 4; 3185232812Sjmallett uint64_t engine2 : 4; 3186232812Sjmallett uint64_t engine3 : 4; 3187232812Sjmallett uint64_t engine4 : 4; 3188232812Sjmallett uint64_t engine5 : 4; 3189232812Sjmallett uint64_t engine6 : 4; 3190232812Sjmallett uint64_t engine7 : 4; 3191232812Sjmallett uint64_t engine8 : 4; 3192232812Sjmallett uint64_t engine9 : 4; 3193232812Sjmallett uint64_t engine10 : 4; 3194232812Sjmallett uint64_t engine11 : 4; 3195232812Sjmallett uint64_t engine12 : 4; 3196232812Sjmallett uint64_t engine13 : 4; 3197232812Sjmallett uint64_t engine14 : 4; 3198232812Sjmallett uint64_t engine15 : 4; 3199232812Sjmallett#endif 3200232812Sjmallett } s; 3201232812Sjmallett struct cvmx_pko_reg_engine_storagex_s cn68xx; 3202232812Sjmallett struct cvmx_pko_reg_engine_storagex_s cn68xxp1; 3203232812Sjmallett}; 3204232812Sjmalletttypedef union cvmx_pko_reg_engine_storagex cvmx_pko_reg_engine_storagex_t; 3205232812Sjmallett 3206232812Sjmallett/** 3207215976Sjmallett * cvmx_pko_reg_engine_thresh 3208215976Sjmallett * 3209215976Sjmallett * Notes: 3210215976Sjmallett * When not enabled, packet data may be sent as soon as it is written into PKO's internal buffers. 3211215976Sjmallett * When enabled and the packet fits entirely in the PKO's internal buffer, none of the packet data will 3212215976Sjmallett * be sent until all of it has been written into the PKO's internal buffer. Note that a packet is 3213215976Sjmallett * considered to fit entirely only if the packet's size is <= BUFFER_SIZE-8. When enabled and the 3214215976Sjmallett * packet does not fit entirely in the PKO's internal buffer, none of the packet data will be sent until 3215215976Sjmallett * at least BUFFER_SIZE-256 bytes of the packet have been written into the PKO's internal buffer 3216215976Sjmallett * (note that BUFFER_SIZE is a function of PKO_REG_GMX_PORT_MODE above) 3217215976Sjmallett */ 3218232812Sjmallettunion cvmx_pko_reg_engine_thresh { 3219215976Sjmallett uint64_t u64; 3220232812Sjmallett struct cvmx_pko_reg_engine_thresh_s { 3221232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3222232812Sjmallett uint64_t reserved_20_63 : 44; 3223232812Sjmallett uint64_t mask : 20; /**< Mask[n]=0 disables packet send threshold for engine n 3224232812Sjmallett Mask[n]=1 enables packet send threshold for engine n $PR NS */ 3225215976Sjmallett#else 3226232812Sjmallett uint64_t mask : 20; 3227232812Sjmallett uint64_t reserved_20_63 : 44; 3228215976Sjmallett#endif 3229215976Sjmallett } s; 3230232812Sjmallett struct cvmx_pko_reg_engine_thresh_cn52xx { 3231232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3232215976Sjmallett uint64_t reserved_10_63 : 54; 3233215976Sjmallett uint64_t mask : 10; /**< Mask[n]=0 disables packet send threshold for eng n 3234215976Sjmallett Mask[n]=1 enables packet send threshold for eng n $PR NS 3235215976Sjmallett Mask[n] MBZ for n = 4-7, as engines 4-7 dont exist */ 3236215976Sjmallett#else 3237215976Sjmallett uint64_t mask : 10; 3238215976Sjmallett uint64_t reserved_10_63 : 54; 3239215976Sjmallett#endif 3240215976Sjmallett } cn52xx; 3241215976Sjmallett struct cvmx_pko_reg_engine_thresh_cn52xx cn52xxp1; 3242215976Sjmallett struct cvmx_pko_reg_engine_thresh_cn52xx cn56xx; 3243215976Sjmallett struct cvmx_pko_reg_engine_thresh_cn52xx cn56xxp1; 3244232812Sjmallett struct cvmx_pko_reg_engine_thresh_cn61xx { 3245232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3246232812Sjmallett uint64_t reserved_14_63 : 50; 3247232812Sjmallett uint64_t mask : 14; /**< Mask[n]=0 disables packet send threshold for engine n 3248232812Sjmallett Mask[n]=1 enables packet send threshold for engine n $PR NS */ 3249232812Sjmallett#else 3250232812Sjmallett uint64_t mask : 14; 3251232812Sjmallett uint64_t reserved_14_63 : 50; 3252232812Sjmallett#endif 3253232812Sjmallett } cn61xx; 3254232812Sjmallett struct cvmx_pko_reg_engine_thresh_cn63xx { 3255232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3256232812Sjmallett uint64_t reserved_12_63 : 52; 3257232812Sjmallett uint64_t mask : 12; /**< Mask[n]=0 disables packet send threshold for engine n 3258232812Sjmallett Mask[n]=1 enables packet send threshold for engine n $PR NS 3259232812Sjmallett Mask[n] MBZ for n = 4-7, as engines 4-7 dont exist */ 3260232812Sjmallett#else 3261232812Sjmallett uint64_t mask : 12; 3262232812Sjmallett uint64_t reserved_12_63 : 52; 3263232812Sjmallett#endif 3264232812Sjmallett } cn63xx; 3265232812Sjmallett struct cvmx_pko_reg_engine_thresh_cn63xx cn63xxp1; 3266232812Sjmallett struct cvmx_pko_reg_engine_thresh_cn61xx cn66xx; 3267232812Sjmallett struct cvmx_pko_reg_engine_thresh_s cn68xx; 3268232812Sjmallett struct cvmx_pko_reg_engine_thresh_s cn68xxp1; 3269232812Sjmallett struct cvmx_pko_reg_engine_thresh_cn61xx cnf71xx; 3270215976Sjmallett}; 3271215976Sjmalletttypedef union cvmx_pko_reg_engine_thresh cvmx_pko_reg_engine_thresh_t; 3272215976Sjmallett 3273215976Sjmallett/** 3274215976Sjmallett * cvmx_pko_reg_error 3275215976Sjmallett * 3276215976Sjmallett * Notes: 3277215976Sjmallett * Note that this CSR is present only in chip revisions beginning with pass2. 3278215976Sjmallett * 3279215976Sjmallett */ 3280232812Sjmallettunion cvmx_pko_reg_error { 3281215976Sjmallett uint64_t u64; 3282232812Sjmallett struct cvmx_pko_reg_error_s { 3283232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3284232812Sjmallett uint64_t reserved_4_63 : 60; 3285232812Sjmallett uint64_t loopback : 1; /**< A packet was sent to an illegal loopback port */ 3286215976Sjmallett uint64_t currzero : 1; /**< A packet data pointer has size=0 */ 3287215976Sjmallett uint64_t doorbell : 1; /**< A doorbell count has overflowed */ 3288215976Sjmallett uint64_t parity : 1; /**< Read parity error at port data buffer */ 3289215976Sjmallett#else 3290215976Sjmallett uint64_t parity : 1; 3291215976Sjmallett uint64_t doorbell : 1; 3292215976Sjmallett uint64_t currzero : 1; 3293232812Sjmallett uint64_t loopback : 1; 3294232812Sjmallett uint64_t reserved_4_63 : 60; 3295215976Sjmallett#endif 3296215976Sjmallett } s; 3297232812Sjmallett struct cvmx_pko_reg_error_cn30xx { 3298232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3299215976Sjmallett uint64_t reserved_2_63 : 62; 3300215976Sjmallett uint64_t doorbell : 1; /**< A doorbell count has overflowed */ 3301215976Sjmallett uint64_t parity : 1; /**< Read parity error at port data buffer */ 3302215976Sjmallett#else 3303215976Sjmallett uint64_t parity : 1; 3304215976Sjmallett uint64_t doorbell : 1; 3305215976Sjmallett uint64_t reserved_2_63 : 62; 3306215976Sjmallett#endif 3307215976Sjmallett } cn30xx; 3308215976Sjmallett struct cvmx_pko_reg_error_cn30xx cn31xx; 3309215976Sjmallett struct cvmx_pko_reg_error_cn30xx cn38xx; 3310215976Sjmallett struct cvmx_pko_reg_error_cn30xx cn38xxp2; 3311232812Sjmallett struct cvmx_pko_reg_error_cn50xx { 3312232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3313232812Sjmallett uint64_t reserved_3_63 : 61; 3314232812Sjmallett uint64_t currzero : 1; /**< A packet data pointer has size=0 */ 3315232812Sjmallett uint64_t doorbell : 1; /**< A doorbell count has overflowed */ 3316232812Sjmallett uint64_t parity : 1; /**< Read parity error at port data buffer */ 3317232812Sjmallett#else 3318232812Sjmallett uint64_t parity : 1; 3319232812Sjmallett uint64_t doorbell : 1; 3320232812Sjmallett uint64_t currzero : 1; 3321232812Sjmallett uint64_t reserved_3_63 : 61; 3322232812Sjmallett#endif 3323232812Sjmallett } cn50xx; 3324232812Sjmallett struct cvmx_pko_reg_error_cn50xx cn52xx; 3325232812Sjmallett struct cvmx_pko_reg_error_cn50xx cn52xxp1; 3326232812Sjmallett struct cvmx_pko_reg_error_cn50xx cn56xx; 3327232812Sjmallett struct cvmx_pko_reg_error_cn50xx cn56xxp1; 3328232812Sjmallett struct cvmx_pko_reg_error_cn50xx cn58xx; 3329232812Sjmallett struct cvmx_pko_reg_error_cn50xx cn58xxp1; 3330232812Sjmallett struct cvmx_pko_reg_error_cn50xx cn61xx; 3331232812Sjmallett struct cvmx_pko_reg_error_cn50xx cn63xx; 3332232812Sjmallett struct cvmx_pko_reg_error_cn50xx cn63xxp1; 3333232812Sjmallett struct cvmx_pko_reg_error_cn50xx cn66xx; 3334232812Sjmallett struct cvmx_pko_reg_error_s cn68xx; 3335232812Sjmallett struct cvmx_pko_reg_error_s cn68xxp1; 3336232812Sjmallett struct cvmx_pko_reg_error_cn50xx cnf71xx; 3337215976Sjmallett}; 3338215976Sjmalletttypedef union cvmx_pko_reg_error cvmx_pko_reg_error_t; 3339215976Sjmallett 3340215976Sjmallett/** 3341215976Sjmallett * cvmx_pko_reg_flags 3342215976Sjmallett * 3343215976Sjmallett * Notes: 3344215976Sjmallett * When set, ENA_PKO enables the PKO picker and places the PKO in normal operation. When set, ENA_DWB 3345215976Sjmallett * enables the use of DontWriteBacks during the buffer freeing operations. When not set, STORE_BE inverts 3346215976Sjmallett * bits[2:0] of the STORE0 byte write address. When set, RESET causes a 4-cycle reset pulse to the 3347215976Sjmallett * entire box. 3348215976Sjmallett */ 3349232812Sjmallettunion cvmx_pko_reg_flags { 3350215976Sjmallett uint64_t u64; 3351232812Sjmallett struct cvmx_pko_reg_flags_s { 3352232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3353232812Sjmallett uint64_t reserved_9_63 : 55; 3354232812Sjmallett uint64_t dis_perf3 : 1; /**< Set to disable inactive queue QOS skipping */ 3355232812Sjmallett uint64_t dis_perf2 : 1; /**< Set to disable inactive queue skipping */ 3356232812Sjmallett uint64_t dis_perf1 : 1; /**< Set to disable command word prefetching */ 3357232812Sjmallett uint64_t dis_perf0 : 1; /**< Set to disable read performance optimizations */ 3358232812Sjmallett uint64_t ena_throttle : 1; /**< Set to enable the PKO picker throttle logic 3359232812Sjmallett When ENA_THROTTLE=1 and the most-significant 3360232812Sjmallett bit of any of the pipe or interface, word or 3361232812Sjmallett packet throttle count is set, then PKO will 3362232812Sjmallett not output any packets to the interface/pipe. 3363232812Sjmallett See PKO_MEM_THROTTLE_PIPE and 3364232812Sjmallett PKO_MEM_THROTTLE_INT. */ 3365232812Sjmallett uint64_t reset : 1; /**< Reset oneshot pulse */ 3366232812Sjmallett uint64_t store_be : 1; /**< Force STORE0 byte write address to big endian */ 3367232812Sjmallett uint64_t ena_dwb : 1; /**< Set to enable DontWriteBacks */ 3368232812Sjmallett uint64_t ena_pko : 1; /**< Set to enable the PKO picker */ 3369232812Sjmallett#else 3370232812Sjmallett uint64_t ena_pko : 1; 3371232812Sjmallett uint64_t ena_dwb : 1; 3372232812Sjmallett uint64_t store_be : 1; 3373232812Sjmallett uint64_t reset : 1; 3374232812Sjmallett uint64_t ena_throttle : 1; 3375232812Sjmallett uint64_t dis_perf0 : 1; 3376232812Sjmallett uint64_t dis_perf1 : 1; 3377232812Sjmallett uint64_t dis_perf2 : 1; 3378232812Sjmallett uint64_t dis_perf3 : 1; 3379232812Sjmallett uint64_t reserved_9_63 : 55; 3380232812Sjmallett#endif 3381232812Sjmallett } s; 3382232812Sjmallett struct cvmx_pko_reg_flags_cn30xx { 3383232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3384215976Sjmallett uint64_t reserved_4_63 : 60; 3385215976Sjmallett uint64_t reset : 1; /**< Reset oneshot pulse */ 3386215976Sjmallett uint64_t store_be : 1; /**< Force STORE0 byte write address to big endian */ 3387215976Sjmallett uint64_t ena_dwb : 1; /**< Set to enable DontWriteBacks */ 3388215976Sjmallett uint64_t ena_pko : 1; /**< Set to enable the PKO picker */ 3389215976Sjmallett#else 3390215976Sjmallett uint64_t ena_pko : 1; 3391215976Sjmallett uint64_t ena_dwb : 1; 3392215976Sjmallett uint64_t store_be : 1; 3393215976Sjmallett uint64_t reset : 1; 3394215976Sjmallett uint64_t reserved_4_63 : 60; 3395215976Sjmallett#endif 3396232812Sjmallett } cn30xx; 3397232812Sjmallett struct cvmx_pko_reg_flags_cn30xx cn31xx; 3398232812Sjmallett struct cvmx_pko_reg_flags_cn30xx cn38xx; 3399232812Sjmallett struct cvmx_pko_reg_flags_cn30xx cn38xxp2; 3400232812Sjmallett struct cvmx_pko_reg_flags_cn30xx cn50xx; 3401232812Sjmallett struct cvmx_pko_reg_flags_cn30xx cn52xx; 3402232812Sjmallett struct cvmx_pko_reg_flags_cn30xx cn52xxp1; 3403232812Sjmallett struct cvmx_pko_reg_flags_cn30xx cn56xx; 3404232812Sjmallett struct cvmx_pko_reg_flags_cn30xx cn56xxp1; 3405232812Sjmallett struct cvmx_pko_reg_flags_cn30xx cn58xx; 3406232812Sjmallett struct cvmx_pko_reg_flags_cn30xx cn58xxp1; 3407232812Sjmallett struct cvmx_pko_reg_flags_cn61xx { 3408232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3409232812Sjmallett uint64_t reserved_9_63 : 55; 3410232812Sjmallett uint64_t dis_perf3 : 1; /**< Set to disable inactive queue QOS skipping */ 3411232812Sjmallett uint64_t dis_perf2 : 1; /**< Set to disable inactive queue skipping */ 3412232812Sjmallett uint64_t reserved_4_6 : 3; 3413232812Sjmallett uint64_t reset : 1; /**< Reset oneshot pulse */ 3414232812Sjmallett uint64_t store_be : 1; /**< Force STORE0 byte write address to big endian */ 3415232812Sjmallett uint64_t ena_dwb : 1; /**< Set to enable DontWriteBacks */ 3416232812Sjmallett uint64_t ena_pko : 1; /**< Set to enable the PKO picker */ 3417232812Sjmallett#else 3418232812Sjmallett uint64_t ena_pko : 1; 3419232812Sjmallett uint64_t ena_dwb : 1; 3420232812Sjmallett uint64_t store_be : 1; 3421232812Sjmallett uint64_t reset : 1; 3422232812Sjmallett uint64_t reserved_4_6 : 3; 3423232812Sjmallett uint64_t dis_perf2 : 1; 3424232812Sjmallett uint64_t dis_perf3 : 1; 3425232812Sjmallett uint64_t reserved_9_63 : 55; 3426232812Sjmallett#endif 3427232812Sjmallett } cn61xx; 3428232812Sjmallett struct cvmx_pko_reg_flags_cn30xx cn63xx; 3429232812Sjmallett struct cvmx_pko_reg_flags_cn30xx cn63xxp1; 3430232812Sjmallett struct cvmx_pko_reg_flags_cn61xx cn66xx; 3431232812Sjmallett struct cvmx_pko_reg_flags_s cn68xx; 3432232812Sjmallett struct cvmx_pko_reg_flags_cn68xxp1 { 3433232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3434232812Sjmallett uint64_t reserved_7_63 : 57; 3435232812Sjmallett uint64_t dis_perf1 : 1; /**< Set to disable command word prefetching */ 3436232812Sjmallett uint64_t dis_perf0 : 1; /**< Set to disable read performance optimizations */ 3437232812Sjmallett uint64_t ena_throttle : 1; /**< Set to enable the PKO picker throttle logic 3438232812Sjmallett When ENA_THROTTLE=1 and the most-significant 3439232812Sjmallett bit of any of the pipe or interface, word or 3440232812Sjmallett packet throttle count is set, then PKO will 3441232812Sjmallett not output any packets to the interface/pipe. 3442232812Sjmallett See PKO_MEM_THROTTLE_PIPE and 3443232812Sjmallett PKO_MEM_THROTTLE_INT. */ 3444232812Sjmallett uint64_t reset : 1; /**< Reset oneshot pulse */ 3445232812Sjmallett uint64_t store_be : 1; /**< Force STORE0 byte write address to big endian */ 3446232812Sjmallett uint64_t ena_dwb : 1; /**< Set to enable DontWriteBacks */ 3447232812Sjmallett uint64_t ena_pko : 1; /**< Set to enable the PKO picker */ 3448232812Sjmallett#else 3449232812Sjmallett uint64_t ena_pko : 1; 3450232812Sjmallett uint64_t ena_dwb : 1; 3451232812Sjmallett uint64_t store_be : 1; 3452232812Sjmallett uint64_t reset : 1; 3453232812Sjmallett uint64_t ena_throttle : 1; 3454232812Sjmallett uint64_t dis_perf0 : 1; 3455232812Sjmallett uint64_t dis_perf1 : 1; 3456232812Sjmallett uint64_t reserved_7_63 : 57; 3457232812Sjmallett#endif 3458232812Sjmallett } cn68xxp1; 3459232812Sjmallett struct cvmx_pko_reg_flags_cn61xx cnf71xx; 3460215976Sjmallett}; 3461215976Sjmalletttypedef union cvmx_pko_reg_flags cvmx_pko_reg_flags_t; 3462215976Sjmallett 3463215976Sjmallett/** 3464215976Sjmallett * cvmx_pko_reg_gmx_port_mode 3465215976Sjmallett * 3466215976Sjmallett * Notes: 3467232812Sjmallett * The system has a total of 4 + 4 + 4 + 4 + 4 ports and 4 + 4 + 1 + 1 + 1 + 1 engines (GM0 + GM1 + PCI + LOOP + SRIO0 + SRIO1 + SRIO2 + SRIO3). 3468232812Sjmallett * This CSR sets the number of GMX0/GMX1 ports and amount of local storage per engine. 3469215976Sjmallett * It has no effect on the number of ports or amount of local storage per engine for PCI, LOOP, 3470232812Sjmallett * SRIO0, SRIO1, SRIO2, or SRIO3. When all GMX ports are used (MODE0=2), each GMX engine has 2.5kB of local 3471215976Sjmallett * storage. Increasing the value of MODEn by 1 decreases the number of GMX ports by a power of 2 and 3472232812Sjmallett * increases the local storage per PKO GMX engine by a power of 2. If one of the modes is 5, then only 3473232812Sjmallett * one of interfaces GM0 or GM1 is present and the storage per engine of the existing interface is 3474232812Sjmallett * doubled. Modes 0 and 1 are illegal and, if selected, are treated as mode 2. 3475215976Sjmallett * 3476232812Sjmallett * MODE[n] GM[n] PCI LOOP GM[n] PCI LOOP SRIO[n] 3477232812Sjmallett * ports ports ports storage/engine storage/engine storage/engine storage/engine 3478232812Sjmallett * 0 4 4 4 ( 2.5kB << (MODE[1-n]==5)) 2.5kB 2.5kB 2.5kB 3479232812Sjmallett * 1 4 4 4 ( 2.5kB << (MODE[1-n]==5)) 2.5kB 2.5kB 2.5kB 3480232812Sjmallett * 2 4 4 4 ( 2.5kB << (MODE[1-n]==5)) 2.5kB 2.5kB 2.5kB 3481232812Sjmallett * 3 2 4 4 ( 5.0kB << (MODE[1-n]==5)) 2.5kB 2.5kB 2.5kB 3482232812Sjmallett * 4 1 4 4 (10.0kB << (MODE[1-n]==5)) 2.5kB 2.5kB 2.5kB 3483232812Sjmallett * 5 0 4 4 ( 0kB ) 2.5kB 2.5kB 2.5kB 3484232812Sjmallett * where 0 <= n <= 1 3485215976Sjmallett */ 3486232812Sjmallettunion cvmx_pko_reg_gmx_port_mode { 3487215976Sjmallett uint64_t u64; 3488232812Sjmallett struct cvmx_pko_reg_gmx_port_mode_s { 3489232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3490215976Sjmallett uint64_t reserved_6_63 : 58; 3491232812Sjmallett uint64_t mode1 : 3; /**< # of GM1 ports = 16 >> MODE0, 0 <= MODE0 <= 4 */ 3492215976Sjmallett uint64_t mode0 : 3; /**< # of GM0 ports = 16 >> MODE0, 0 <= MODE0 <= 4 */ 3493215976Sjmallett#else 3494215976Sjmallett uint64_t mode0 : 3; 3495215976Sjmallett uint64_t mode1 : 3; 3496215976Sjmallett uint64_t reserved_6_63 : 58; 3497215976Sjmallett#endif 3498215976Sjmallett } s; 3499215976Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cn30xx; 3500215976Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cn31xx; 3501215976Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cn38xx; 3502215976Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2; 3503215976Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cn50xx; 3504215976Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cn52xx; 3505215976Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1; 3506215976Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cn56xx; 3507215976Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1; 3508215976Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cn58xx; 3509215976Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1; 3510232812Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cn61xx; 3511215976Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cn63xx; 3512215976Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cn63xxp1; 3513232812Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cn66xx; 3514232812Sjmallett struct cvmx_pko_reg_gmx_port_mode_s cnf71xx; 3515215976Sjmallett}; 3516215976Sjmalletttypedef union cvmx_pko_reg_gmx_port_mode cvmx_pko_reg_gmx_port_mode_t; 3517215976Sjmallett 3518215976Sjmallett/** 3519215976Sjmallett * cvmx_pko_reg_int_mask 3520215976Sjmallett * 3521215976Sjmallett * Notes: 3522215976Sjmallett * When a mask bit is set, the corresponding interrupt is enabled. 3523215976Sjmallett * 3524215976Sjmallett */ 3525232812Sjmallettunion cvmx_pko_reg_int_mask { 3526215976Sjmallett uint64_t u64; 3527232812Sjmallett struct cvmx_pko_reg_int_mask_s { 3528232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3529232812Sjmallett uint64_t reserved_4_63 : 60; 3530232812Sjmallett uint64_t loopback : 1; /**< Bit mask corresponding to PKO_REG_ERROR[3] above */ 3531215976Sjmallett uint64_t currzero : 1; /**< Bit mask corresponding to PKO_REG_ERROR[2] above */ 3532215976Sjmallett uint64_t doorbell : 1; /**< Bit mask corresponding to PKO_REG_ERROR[1] above */ 3533215976Sjmallett uint64_t parity : 1; /**< Bit mask corresponding to PKO_REG_ERROR[0] above */ 3534215976Sjmallett#else 3535215976Sjmallett uint64_t parity : 1; 3536215976Sjmallett uint64_t doorbell : 1; 3537215976Sjmallett uint64_t currzero : 1; 3538232812Sjmallett uint64_t loopback : 1; 3539232812Sjmallett uint64_t reserved_4_63 : 60; 3540215976Sjmallett#endif 3541215976Sjmallett } s; 3542232812Sjmallett struct cvmx_pko_reg_int_mask_cn30xx { 3543232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3544215976Sjmallett uint64_t reserved_2_63 : 62; 3545215976Sjmallett uint64_t doorbell : 1; /**< Bit mask corresponding to PKO_REG_ERROR[1] above */ 3546215976Sjmallett uint64_t parity : 1; /**< Bit mask corresponding to PKO_REG_ERROR[0] above */ 3547215976Sjmallett#else 3548215976Sjmallett uint64_t parity : 1; 3549215976Sjmallett uint64_t doorbell : 1; 3550215976Sjmallett uint64_t reserved_2_63 : 62; 3551215976Sjmallett#endif 3552215976Sjmallett } cn30xx; 3553215976Sjmallett struct cvmx_pko_reg_int_mask_cn30xx cn31xx; 3554215976Sjmallett struct cvmx_pko_reg_int_mask_cn30xx cn38xx; 3555215976Sjmallett struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2; 3556232812Sjmallett struct cvmx_pko_reg_int_mask_cn50xx { 3557232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3558232812Sjmallett uint64_t reserved_3_63 : 61; 3559232812Sjmallett uint64_t currzero : 1; /**< Bit mask corresponding to PKO_REG_ERROR[2] above */ 3560232812Sjmallett uint64_t doorbell : 1; /**< Bit mask corresponding to PKO_REG_ERROR[1] above */ 3561232812Sjmallett uint64_t parity : 1; /**< Bit mask corresponding to PKO_REG_ERROR[0] above */ 3562232812Sjmallett#else 3563232812Sjmallett uint64_t parity : 1; 3564232812Sjmallett uint64_t doorbell : 1; 3565232812Sjmallett uint64_t currzero : 1; 3566232812Sjmallett uint64_t reserved_3_63 : 61; 3567232812Sjmallett#endif 3568232812Sjmallett } cn50xx; 3569232812Sjmallett struct cvmx_pko_reg_int_mask_cn50xx cn52xx; 3570232812Sjmallett struct cvmx_pko_reg_int_mask_cn50xx cn52xxp1; 3571232812Sjmallett struct cvmx_pko_reg_int_mask_cn50xx cn56xx; 3572232812Sjmallett struct cvmx_pko_reg_int_mask_cn50xx cn56xxp1; 3573232812Sjmallett struct cvmx_pko_reg_int_mask_cn50xx cn58xx; 3574232812Sjmallett struct cvmx_pko_reg_int_mask_cn50xx cn58xxp1; 3575232812Sjmallett struct cvmx_pko_reg_int_mask_cn50xx cn61xx; 3576232812Sjmallett struct cvmx_pko_reg_int_mask_cn50xx cn63xx; 3577232812Sjmallett struct cvmx_pko_reg_int_mask_cn50xx cn63xxp1; 3578232812Sjmallett struct cvmx_pko_reg_int_mask_cn50xx cn66xx; 3579232812Sjmallett struct cvmx_pko_reg_int_mask_s cn68xx; 3580232812Sjmallett struct cvmx_pko_reg_int_mask_s cn68xxp1; 3581232812Sjmallett struct cvmx_pko_reg_int_mask_cn50xx cnf71xx; 3582215976Sjmallett}; 3583215976Sjmalletttypedef union cvmx_pko_reg_int_mask cvmx_pko_reg_int_mask_t; 3584215976Sjmallett 3585215976Sjmallett/** 3586232812Sjmallett * cvmx_pko_reg_loopback_bpid 3587232812Sjmallett * 3588232812Sjmallett * Notes: 3589232812Sjmallett * None. 3590232812Sjmallett * 3591232812Sjmallett */ 3592232812Sjmallettunion cvmx_pko_reg_loopback_bpid { 3593232812Sjmallett uint64_t u64; 3594232812Sjmallett struct cvmx_pko_reg_loopback_bpid_s { 3595232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3596232812Sjmallett uint64_t reserved_59_63 : 5; 3597232812Sjmallett uint64_t bpid7 : 6; /**< Loopback port 7 backpressure-ID */ 3598232812Sjmallett uint64_t reserved_52_52 : 1; 3599232812Sjmallett uint64_t bpid6 : 6; /**< Loopback port 6 backpressure-ID */ 3600232812Sjmallett uint64_t reserved_45_45 : 1; 3601232812Sjmallett uint64_t bpid5 : 6; /**< Loopback port 5 backpressure-ID */ 3602232812Sjmallett uint64_t reserved_38_38 : 1; 3603232812Sjmallett uint64_t bpid4 : 6; /**< Loopback port 4 backpressure-ID */ 3604232812Sjmallett uint64_t reserved_31_31 : 1; 3605232812Sjmallett uint64_t bpid3 : 6; /**< Loopback port 3 backpressure-ID */ 3606232812Sjmallett uint64_t reserved_24_24 : 1; 3607232812Sjmallett uint64_t bpid2 : 6; /**< Loopback port 2 backpressure-ID */ 3608232812Sjmallett uint64_t reserved_17_17 : 1; 3609232812Sjmallett uint64_t bpid1 : 6; /**< Loopback port 1 backpressure-ID */ 3610232812Sjmallett uint64_t reserved_10_10 : 1; 3611232812Sjmallett uint64_t bpid0 : 6; /**< Loopback port 0 backpressure-ID */ 3612232812Sjmallett uint64_t reserved_0_3 : 4; 3613232812Sjmallett#else 3614232812Sjmallett uint64_t reserved_0_3 : 4; 3615232812Sjmallett uint64_t bpid0 : 6; 3616232812Sjmallett uint64_t reserved_10_10 : 1; 3617232812Sjmallett uint64_t bpid1 : 6; 3618232812Sjmallett uint64_t reserved_17_17 : 1; 3619232812Sjmallett uint64_t bpid2 : 6; 3620232812Sjmallett uint64_t reserved_24_24 : 1; 3621232812Sjmallett uint64_t bpid3 : 6; 3622232812Sjmallett uint64_t reserved_31_31 : 1; 3623232812Sjmallett uint64_t bpid4 : 6; 3624232812Sjmallett uint64_t reserved_38_38 : 1; 3625232812Sjmallett uint64_t bpid5 : 6; 3626232812Sjmallett uint64_t reserved_45_45 : 1; 3627232812Sjmallett uint64_t bpid6 : 6; 3628232812Sjmallett uint64_t reserved_52_52 : 1; 3629232812Sjmallett uint64_t bpid7 : 6; 3630232812Sjmallett uint64_t reserved_59_63 : 5; 3631232812Sjmallett#endif 3632232812Sjmallett } s; 3633232812Sjmallett struct cvmx_pko_reg_loopback_bpid_s cn68xx; 3634232812Sjmallett struct cvmx_pko_reg_loopback_bpid_s cn68xxp1; 3635232812Sjmallett}; 3636232812Sjmalletttypedef union cvmx_pko_reg_loopback_bpid cvmx_pko_reg_loopback_bpid_t; 3637232812Sjmallett 3638232812Sjmallett/** 3639232812Sjmallett * cvmx_pko_reg_loopback_pkind 3640232812Sjmallett * 3641232812Sjmallett * Notes: 3642232812Sjmallett * None. 3643232812Sjmallett * 3644232812Sjmallett */ 3645232812Sjmallettunion cvmx_pko_reg_loopback_pkind { 3646232812Sjmallett uint64_t u64; 3647232812Sjmallett struct cvmx_pko_reg_loopback_pkind_s { 3648232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3649232812Sjmallett uint64_t reserved_59_63 : 5; 3650232812Sjmallett uint64_t pkind7 : 6; /**< Loopback port 7 port-kind */ 3651232812Sjmallett uint64_t reserved_52_52 : 1; 3652232812Sjmallett uint64_t pkind6 : 6; /**< Loopback port 6 port-kind */ 3653232812Sjmallett uint64_t reserved_45_45 : 1; 3654232812Sjmallett uint64_t pkind5 : 6; /**< Loopback port 5 port-kind */ 3655232812Sjmallett uint64_t reserved_38_38 : 1; 3656232812Sjmallett uint64_t pkind4 : 6; /**< Loopback port 4 port-kind */ 3657232812Sjmallett uint64_t reserved_31_31 : 1; 3658232812Sjmallett uint64_t pkind3 : 6; /**< Loopback port 3 port-kind */ 3659232812Sjmallett uint64_t reserved_24_24 : 1; 3660232812Sjmallett uint64_t pkind2 : 6; /**< Loopback port 2 port-kind */ 3661232812Sjmallett uint64_t reserved_17_17 : 1; 3662232812Sjmallett uint64_t pkind1 : 6; /**< Loopback port 1 port-kind */ 3663232812Sjmallett uint64_t reserved_10_10 : 1; 3664232812Sjmallett uint64_t pkind0 : 6; /**< Loopback port 0 port-kind */ 3665232812Sjmallett uint64_t num_ports : 4; /**< Number of loopback ports, 0 <= NUM_PORTS <= 8 */ 3666232812Sjmallett#else 3667232812Sjmallett uint64_t num_ports : 4; 3668232812Sjmallett uint64_t pkind0 : 6; 3669232812Sjmallett uint64_t reserved_10_10 : 1; 3670232812Sjmallett uint64_t pkind1 : 6; 3671232812Sjmallett uint64_t reserved_17_17 : 1; 3672232812Sjmallett uint64_t pkind2 : 6; 3673232812Sjmallett uint64_t reserved_24_24 : 1; 3674232812Sjmallett uint64_t pkind3 : 6; 3675232812Sjmallett uint64_t reserved_31_31 : 1; 3676232812Sjmallett uint64_t pkind4 : 6; 3677232812Sjmallett uint64_t reserved_38_38 : 1; 3678232812Sjmallett uint64_t pkind5 : 6; 3679232812Sjmallett uint64_t reserved_45_45 : 1; 3680232812Sjmallett uint64_t pkind6 : 6; 3681232812Sjmallett uint64_t reserved_52_52 : 1; 3682232812Sjmallett uint64_t pkind7 : 6; 3683232812Sjmallett uint64_t reserved_59_63 : 5; 3684232812Sjmallett#endif 3685232812Sjmallett } s; 3686232812Sjmallett struct cvmx_pko_reg_loopback_pkind_s cn68xx; 3687232812Sjmallett struct cvmx_pko_reg_loopback_pkind_s cn68xxp1; 3688232812Sjmallett}; 3689232812Sjmalletttypedef union cvmx_pko_reg_loopback_pkind cvmx_pko_reg_loopback_pkind_t; 3690232812Sjmallett 3691232812Sjmallett/** 3692232812Sjmallett * cvmx_pko_reg_min_pkt 3693232812Sjmallett * 3694232812Sjmallett * Notes: 3695232812Sjmallett * This CSR is used with PKO_MEM_IPORT_PTRS[MIN_PKT] to select the minimum packet size. Packets whose 3696232812Sjmallett * size in bytes < (SIZEn+1) are zero-padded to (SIZEn+1) bytes. Note that this does not include CRC bytes. 3697232812Sjmallett * SIZE0=0 is read-only and is used when no padding is desired. 3698232812Sjmallett */ 3699232812Sjmallettunion cvmx_pko_reg_min_pkt { 3700232812Sjmallett uint64_t u64; 3701232812Sjmallett struct cvmx_pko_reg_min_pkt_s { 3702232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3703232812Sjmallett uint64_t size7 : 8; /**< Minimum packet size-1 in bytes NS */ 3704232812Sjmallett uint64_t size6 : 8; /**< Minimum packet size-1 in bytes NS */ 3705232812Sjmallett uint64_t size5 : 8; /**< Minimum packet size-1 in bytes NS */ 3706232812Sjmallett uint64_t size4 : 8; /**< Minimum packet size-1 in bytes NS */ 3707232812Sjmallett uint64_t size3 : 8; /**< Minimum packet size-1 in bytes NS */ 3708232812Sjmallett uint64_t size2 : 8; /**< Minimum packet size-1 in bytes NS */ 3709232812Sjmallett uint64_t size1 : 8; /**< Minimum packet size-1 in bytes NS */ 3710232812Sjmallett uint64_t size0 : 8; /**< Minimum packet size-1 in bytes NS */ 3711232812Sjmallett#else 3712232812Sjmallett uint64_t size0 : 8; 3713232812Sjmallett uint64_t size1 : 8; 3714232812Sjmallett uint64_t size2 : 8; 3715232812Sjmallett uint64_t size3 : 8; 3716232812Sjmallett uint64_t size4 : 8; 3717232812Sjmallett uint64_t size5 : 8; 3718232812Sjmallett uint64_t size6 : 8; 3719232812Sjmallett uint64_t size7 : 8; 3720232812Sjmallett#endif 3721232812Sjmallett } s; 3722232812Sjmallett struct cvmx_pko_reg_min_pkt_s cn68xx; 3723232812Sjmallett struct cvmx_pko_reg_min_pkt_s cn68xxp1; 3724232812Sjmallett}; 3725232812Sjmalletttypedef union cvmx_pko_reg_min_pkt cvmx_pko_reg_min_pkt_t; 3726232812Sjmallett 3727232812Sjmallett/** 3728232812Sjmallett * cvmx_pko_reg_preempt 3729232812Sjmallett */ 3730232812Sjmallettunion cvmx_pko_reg_preempt { 3731232812Sjmallett uint64_t u64; 3732232812Sjmallett struct cvmx_pko_reg_preempt_s { 3733232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3734232812Sjmallett uint64_t reserved_16_63 : 48; 3735232812Sjmallett uint64_t min_size : 16; /**< Threshhold for packet preemption, measured in bytes. 3736232812Sjmallett Only packets which have at least MIN_SIZE bytes 3737232812Sjmallett remaining to be read can be preempted. */ 3738232812Sjmallett#else 3739232812Sjmallett uint64_t min_size : 16; 3740232812Sjmallett uint64_t reserved_16_63 : 48; 3741232812Sjmallett#endif 3742232812Sjmallett } s; 3743232812Sjmallett struct cvmx_pko_reg_preempt_s cn52xx; 3744232812Sjmallett struct cvmx_pko_reg_preempt_s cn52xxp1; 3745232812Sjmallett struct cvmx_pko_reg_preempt_s cn56xx; 3746232812Sjmallett struct cvmx_pko_reg_preempt_s cn56xxp1; 3747232812Sjmallett struct cvmx_pko_reg_preempt_s cn61xx; 3748232812Sjmallett struct cvmx_pko_reg_preempt_s cn63xx; 3749232812Sjmallett struct cvmx_pko_reg_preempt_s cn63xxp1; 3750232812Sjmallett struct cvmx_pko_reg_preempt_s cn66xx; 3751232812Sjmallett struct cvmx_pko_reg_preempt_s cn68xx; 3752232812Sjmallett struct cvmx_pko_reg_preempt_s cn68xxp1; 3753232812Sjmallett struct cvmx_pko_reg_preempt_s cnf71xx; 3754232812Sjmallett}; 3755232812Sjmalletttypedef union cvmx_pko_reg_preempt cvmx_pko_reg_preempt_t; 3756232812Sjmallett 3757232812Sjmallett/** 3758215976Sjmallett * cvmx_pko_reg_queue_mode 3759215976Sjmallett * 3760215976Sjmallett * Notes: 3761215976Sjmallett * Sets the number of queues and amount of local storage per queue 3762215976Sjmallett * The system has a total of 256 queues and (256*8) words of local command storage. This CSR sets the 3763215976Sjmallett * number of queues that are used. Increasing the value of MODE by 1 decreases the number of queues 3764215976Sjmallett * by a power of 2 and increases the local storage per queue by a power of 2. 3765215976Sjmallett * MODEn queues storage/queue 3766215976Sjmallett * 0 256 64B ( 8 words) 3767215976Sjmallett * 1 128 128B (16 words) 3768215976Sjmallett * 2 64 256B (32 words) 3769215976Sjmallett */ 3770232812Sjmallettunion cvmx_pko_reg_queue_mode { 3771215976Sjmallett uint64_t u64; 3772232812Sjmallett struct cvmx_pko_reg_queue_mode_s { 3773232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3774215976Sjmallett uint64_t reserved_2_63 : 62; 3775215976Sjmallett uint64_t mode : 2; /**< # of queues = 256 >> MODE, 0 <= MODE <=2 */ 3776215976Sjmallett#else 3777215976Sjmallett uint64_t mode : 2; 3778215976Sjmallett uint64_t reserved_2_63 : 62; 3779215976Sjmallett#endif 3780215976Sjmallett } s; 3781215976Sjmallett struct cvmx_pko_reg_queue_mode_s cn30xx; 3782215976Sjmallett struct cvmx_pko_reg_queue_mode_s cn31xx; 3783215976Sjmallett struct cvmx_pko_reg_queue_mode_s cn38xx; 3784215976Sjmallett struct cvmx_pko_reg_queue_mode_s cn38xxp2; 3785215976Sjmallett struct cvmx_pko_reg_queue_mode_s cn50xx; 3786215976Sjmallett struct cvmx_pko_reg_queue_mode_s cn52xx; 3787215976Sjmallett struct cvmx_pko_reg_queue_mode_s cn52xxp1; 3788215976Sjmallett struct cvmx_pko_reg_queue_mode_s cn56xx; 3789215976Sjmallett struct cvmx_pko_reg_queue_mode_s cn56xxp1; 3790215976Sjmallett struct cvmx_pko_reg_queue_mode_s cn58xx; 3791215976Sjmallett struct cvmx_pko_reg_queue_mode_s cn58xxp1; 3792232812Sjmallett struct cvmx_pko_reg_queue_mode_s cn61xx; 3793215976Sjmallett struct cvmx_pko_reg_queue_mode_s cn63xx; 3794215976Sjmallett struct cvmx_pko_reg_queue_mode_s cn63xxp1; 3795232812Sjmallett struct cvmx_pko_reg_queue_mode_s cn66xx; 3796232812Sjmallett struct cvmx_pko_reg_queue_mode_s cn68xx; 3797232812Sjmallett struct cvmx_pko_reg_queue_mode_s cn68xxp1; 3798232812Sjmallett struct cvmx_pko_reg_queue_mode_s cnf71xx; 3799215976Sjmallett}; 3800215976Sjmalletttypedef union cvmx_pko_reg_queue_mode cvmx_pko_reg_queue_mode_t; 3801215976Sjmallett 3802215976Sjmallett/** 3803232812Sjmallett * cvmx_pko_reg_queue_preempt 3804232812Sjmallett * 3805232812Sjmallett * Notes: 3806232812Sjmallett * Per QID, setting both PREEMPTER=1 and PREEMPTEE=1 is illegal and sets only PREEMPTER=1. 3807232812Sjmallett * This CSR is used with PKO_MEM_QUEUE_PTRS and PKO_REG_QUEUE_PTRS1. When programming queues, the 3808232812Sjmallett * programming sequence must first write PKO_REG_QUEUE_PREEMPT, then PKO_REG_QUEUE_PTRS1 and then 3809232812Sjmallett * PKO_MEM_QUEUE_PTRS for each queue. Preemption is supported only on queues that are ultimately 3810232812Sjmallett * mapped to engines 0-7. It is illegal to set preemptee or preempter for a queue that is ultimately 3811232812Sjmallett * mapped to engines 8-11. 3812232812Sjmallett * 3813232812Sjmallett * Also, PKO_REG_ENGINE_INFLIGHT must be at least 2 for any engine on which preemption is enabled. 3814232812Sjmallett * 3815232812Sjmallett * See the descriptions of PKO_MEM_QUEUE_PTRS for further explanation of queue programming. 3816232812Sjmallett */ 3817232812Sjmallettunion cvmx_pko_reg_queue_preempt { 3818232812Sjmallett uint64_t u64; 3819232812Sjmallett struct cvmx_pko_reg_queue_preempt_s { 3820232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3821232812Sjmallett uint64_t reserved_2_63 : 62; 3822232812Sjmallett uint64_t preemptee : 1; /**< Allow this QID to be preempted. 3823232812Sjmallett 0=cannot be preempted, 1=can be preempted */ 3824232812Sjmallett uint64_t preempter : 1; /**< Preempts the servicing of packet on PID to 3825232812Sjmallett allow this QID immediate servicing. 0=do not cause 3826232812Sjmallett preemption, 1=cause preemption. Per PID, at most 3827232812Sjmallett 1 QID can have this bit set. */ 3828232812Sjmallett#else 3829232812Sjmallett uint64_t preempter : 1; 3830232812Sjmallett uint64_t preemptee : 1; 3831232812Sjmallett uint64_t reserved_2_63 : 62; 3832232812Sjmallett#endif 3833232812Sjmallett } s; 3834232812Sjmallett struct cvmx_pko_reg_queue_preempt_s cn52xx; 3835232812Sjmallett struct cvmx_pko_reg_queue_preempt_s cn52xxp1; 3836232812Sjmallett struct cvmx_pko_reg_queue_preempt_s cn56xx; 3837232812Sjmallett struct cvmx_pko_reg_queue_preempt_s cn56xxp1; 3838232812Sjmallett struct cvmx_pko_reg_queue_preempt_s cn61xx; 3839232812Sjmallett struct cvmx_pko_reg_queue_preempt_s cn63xx; 3840232812Sjmallett struct cvmx_pko_reg_queue_preempt_s cn63xxp1; 3841232812Sjmallett struct cvmx_pko_reg_queue_preempt_s cn66xx; 3842232812Sjmallett struct cvmx_pko_reg_queue_preempt_s cn68xx; 3843232812Sjmallett struct cvmx_pko_reg_queue_preempt_s cn68xxp1; 3844232812Sjmallett struct cvmx_pko_reg_queue_preempt_s cnf71xx; 3845232812Sjmallett}; 3846232812Sjmalletttypedef union cvmx_pko_reg_queue_preempt cvmx_pko_reg_queue_preempt_t; 3847232812Sjmallett 3848232812Sjmallett/** 3849215976Sjmallett * cvmx_pko_reg_queue_ptrs1 3850215976Sjmallett * 3851215976Sjmallett * Notes: 3852215976Sjmallett * This CSR is used with PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS to allow access to queues 128-255 3853215976Sjmallett * and to allow up mapping of up to 16 queues per port. When programming queues 128-255, the 3854215976Sjmallett * programming sequence must first write PKO_REG_QUEUE_PTRS1 and then write PKO_MEM_QUEUE_PTRS or 3855215976Sjmallett * PKO_MEM_QUEUE_QOS for each queue. 3856215976Sjmallett * See the descriptions of PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS for further explanation of queue 3857215976Sjmallett * programming. 3858215976Sjmallett */ 3859232812Sjmallettunion cvmx_pko_reg_queue_ptrs1 { 3860215976Sjmallett uint64_t u64; 3861232812Sjmallett struct cvmx_pko_reg_queue_ptrs1_s { 3862232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3863215976Sjmallett uint64_t reserved_2_63 : 62; 3864215976Sjmallett uint64_t idx3 : 1; /**< [3] of Index (distance from head) in the queue array */ 3865215976Sjmallett uint64_t qid7 : 1; /**< [7] of Queue ID */ 3866215976Sjmallett#else 3867215976Sjmallett uint64_t qid7 : 1; 3868215976Sjmallett uint64_t idx3 : 1; 3869215976Sjmallett uint64_t reserved_2_63 : 62; 3870215976Sjmallett#endif 3871215976Sjmallett } s; 3872215976Sjmallett struct cvmx_pko_reg_queue_ptrs1_s cn50xx; 3873215976Sjmallett struct cvmx_pko_reg_queue_ptrs1_s cn52xx; 3874215976Sjmallett struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1; 3875215976Sjmallett struct cvmx_pko_reg_queue_ptrs1_s cn56xx; 3876215976Sjmallett struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1; 3877215976Sjmallett struct cvmx_pko_reg_queue_ptrs1_s cn58xx; 3878215976Sjmallett struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1; 3879232812Sjmallett struct cvmx_pko_reg_queue_ptrs1_s cn61xx; 3880215976Sjmallett struct cvmx_pko_reg_queue_ptrs1_s cn63xx; 3881215976Sjmallett struct cvmx_pko_reg_queue_ptrs1_s cn63xxp1; 3882232812Sjmallett struct cvmx_pko_reg_queue_ptrs1_s cn66xx; 3883232812Sjmallett struct cvmx_pko_reg_queue_ptrs1_s cnf71xx; 3884215976Sjmallett}; 3885215976Sjmalletttypedef union cvmx_pko_reg_queue_ptrs1 cvmx_pko_reg_queue_ptrs1_t; 3886215976Sjmallett 3887215976Sjmallett/** 3888215976Sjmallett * cvmx_pko_reg_read_idx 3889215976Sjmallett * 3890215976Sjmallett * Notes: 3891215976Sjmallett * Provides the read index during a CSR read operation to any of the CSRs that are physically stored 3892215976Sjmallett * as memories. The names of these CSRs begin with the prefix "PKO_MEM_". 3893215976Sjmallett * IDX[7:0] is the read index. INC[7:0] is an increment that is added to IDX[7:0] after any CSR read. 3894215976Sjmallett * The intended use is to initially write this CSR such that IDX=0 and INC=1. Then, the entire 3895215976Sjmallett * contents of a CSR memory can be read with consecutive CSR read commands. 3896215976Sjmallett */ 3897232812Sjmallettunion cvmx_pko_reg_read_idx { 3898215976Sjmallett uint64_t u64; 3899232812Sjmallett struct cvmx_pko_reg_read_idx_s { 3900232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3901215976Sjmallett uint64_t reserved_16_63 : 48; 3902215976Sjmallett uint64_t inc : 8; /**< Increment to add to current index for next index */ 3903215976Sjmallett uint64_t index : 8; /**< Index to use for next memory CSR read */ 3904215976Sjmallett#else 3905215976Sjmallett uint64_t index : 8; 3906215976Sjmallett uint64_t inc : 8; 3907215976Sjmallett uint64_t reserved_16_63 : 48; 3908215976Sjmallett#endif 3909215976Sjmallett } s; 3910215976Sjmallett struct cvmx_pko_reg_read_idx_s cn30xx; 3911215976Sjmallett struct cvmx_pko_reg_read_idx_s cn31xx; 3912215976Sjmallett struct cvmx_pko_reg_read_idx_s cn38xx; 3913215976Sjmallett struct cvmx_pko_reg_read_idx_s cn38xxp2; 3914215976Sjmallett struct cvmx_pko_reg_read_idx_s cn50xx; 3915215976Sjmallett struct cvmx_pko_reg_read_idx_s cn52xx; 3916215976Sjmallett struct cvmx_pko_reg_read_idx_s cn52xxp1; 3917215976Sjmallett struct cvmx_pko_reg_read_idx_s cn56xx; 3918215976Sjmallett struct cvmx_pko_reg_read_idx_s cn56xxp1; 3919215976Sjmallett struct cvmx_pko_reg_read_idx_s cn58xx; 3920215976Sjmallett struct cvmx_pko_reg_read_idx_s cn58xxp1; 3921232812Sjmallett struct cvmx_pko_reg_read_idx_s cn61xx; 3922215976Sjmallett struct cvmx_pko_reg_read_idx_s cn63xx; 3923215976Sjmallett struct cvmx_pko_reg_read_idx_s cn63xxp1; 3924232812Sjmallett struct cvmx_pko_reg_read_idx_s cn66xx; 3925232812Sjmallett struct cvmx_pko_reg_read_idx_s cn68xx; 3926232812Sjmallett struct cvmx_pko_reg_read_idx_s cn68xxp1; 3927232812Sjmallett struct cvmx_pko_reg_read_idx_s cnf71xx; 3928215976Sjmallett}; 3929215976Sjmalletttypedef union cvmx_pko_reg_read_idx cvmx_pko_reg_read_idx_t; 3930215976Sjmallett 3931215976Sjmallett/** 3932232812Sjmallett * cvmx_pko_reg_throttle 3933232812Sjmallett * 3934232812Sjmallett * Notes: 3935232812Sjmallett * This CSR is used with PKO_MEM_THROTTLE_PIPE and PKO_MEM_THROTTLE_INT. INT_MASK corresponds to the 3936232812Sjmallett * interfaces listed in the description for PKO_MEM_IPORT_PTRS[INT]. Set INT_MASK[N] to enable the 3937232812Sjmallett * updating of PKO_MEM_THROTTLE_PIPE and PKO_MEM_THROTTLE_INT counts for packets destined for 3938232812Sjmallett * interface N. INT_MASK has no effect on the updates caused by CSR writes to PKO_MEM_THROTTLE_PIPE 3939232812Sjmallett * and PKO_MEM_THROTTLE_INT. Note that this does not disable the throttle logic, just the updating of 3940232812Sjmallett * the interface counts. 3941232812Sjmallett */ 3942232812Sjmallettunion cvmx_pko_reg_throttle { 3943232812Sjmallett uint64_t u64; 3944232812Sjmallett struct cvmx_pko_reg_throttle_s { 3945232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3946232812Sjmallett uint64_t reserved_32_63 : 32; 3947232812Sjmallett uint64_t int_mask : 32; /**< Mask to enable THROTTLE count updates per interface NS */ 3948232812Sjmallett#else 3949232812Sjmallett uint64_t int_mask : 32; 3950232812Sjmallett uint64_t reserved_32_63 : 32; 3951232812Sjmallett#endif 3952232812Sjmallett } s; 3953232812Sjmallett struct cvmx_pko_reg_throttle_s cn68xx; 3954232812Sjmallett struct cvmx_pko_reg_throttle_s cn68xxp1; 3955232812Sjmallett}; 3956232812Sjmalletttypedef union cvmx_pko_reg_throttle cvmx_pko_reg_throttle_t; 3957232812Sjmallett 3958232812Sjmallett/** 3959215976Sjmallett * cvmx_pko_reg_timestamp 3960215976Sjmallett * 3961215976Sjmallett * Notes: 3962215976Sjmallett * None. 3963215976Sjmallett * 3964215976Sjmallett */ 3965232812Sjmallettunion cvmx_pko_reg_timestamp { 3966215976Sjmallett uint64_t u64; 3967232812Sjmallett struct cvmx_pko_reg_timestamp_s { 3968232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3969215976Sjmallett uint64_t reserved_4_63 : 60; 3970215976Sjmallett uint64_t wqe_word : 4; /**< Specifies the 8-byte word in the WQE to which a PTP 3971215976Sjmallett timestamp is written. Values 0 and 1 are illegal. */ 3972215976Sjmallett#else 3973215976Sjmallett uint64_t wqe_word : 4; 3974215976Sjmallett uint64_t reserved_4_63 : 60; 3975215976Sjmallett#endif 3976215976Sjmallett } s; 3977232812Sjmallett struct cvmx_pko_reg_timestamp_s cn61xx; 3978215976Sjmallett struct cvmx_pko_reg_timestamp_s cn63xx; 3979215976Sjmallett struct cvmx_pko_reg_timestamp_s cn63xxp1; 3980232812Sjmallett struct cvmx_pko_reg_timestamp_s cn66xx; 3981232812Sjmallett struct cvmx_pko_reg_timestamp_s cn68xx; 3982232812Sjmallett struct cvmx_pko_reg_timestamp_s cn68xxp1; 3983232812Sjmallett struct cvmx_pko_reg_timestamp_s cnf71xx; 3984215976Sjmallett}; 3985215976Sjmalletttypedef union cvmx_pko_reg_timestamp cvmx_pko_reg_timestamp_t; 3986215976Sjmallett 3987215976Sjmallett#endif 3988