1331722Seadler/* 2150849Sscottl * $FreeBSD$ 3150849Sscottl * 4150849Sscottl * Copyright (c) 2002-2004 David Boggs. (boggs@boggs.palo-alto.ca.us) 5150849Sscottl * All rights reserved. 6150849Sscottl * 7150849Sscottl * BSD License: 8150849Sscottl * 9150849Sscottl * Redistribution and use in source and binary forms, with or without 10150849Sscottl * modification, are permitted provided that the following conditions 11150849Sscottl * are met: 12150849Sscottl * 1. Redistributions of source code must retain the above copyright 13150849Sscottl * notice, this list of conditions and the following disclaimer. 14150849Sscottl * 2. Redistributions in binary form must reproduce the above copyright 15150849Sscottl * notice, this list of conditions and the following disclaimer in the 16150849Sscottl * documentation and/or other materials provided with the distribution. 17150849Sscottl * 18150849Sscottl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19150849Sscottl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20150849Sscottl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21150849Sscottl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22150849Sscottl * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23150849Sscottl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24150849Sscottl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25150849Sscottl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26150849Sscottl * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27150849Sscottl * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28150849Sscottl * SUCH DAMAGE. 29150849Sscottl * 30150849Sscottl * GNU General Public License: 31150849Sscottl * 32150849Sscottl * This program is free software; you can redistribute it and/or modify it 33150849Sscottl * under the terms of the GNU General Public License as published by the Free 34150849Sscottl * Software Foundation; either version 2 of the License, or (at your option) 35150849Sscottl * any later version. 36150849Sscottl * 37150849Sscottl * This program is distributed in the hope that it will be useful, but WITHOUT 38150849Sscottl * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 39150849Sscottl * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 40150849Sscottl * more details. 41150849Sscottl * 42150849Sscottl * You should have received a copy of the GNU General Public License along with 43150849Sscottl * this program; if not, write to the Free Software Foundation, Inc., 59 44150849Sscottl * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 45150849Sscottl */ 46150849Sscottl 47150849Sscottl#ifndef IF_LMC_H 48150849Sscottl#define IF_LMC_H 49150849Sscottl 50150849Sscottl#define DEVICE_NAME "lmc" 51150849Sscottl 52150849Sscottl/* Linux RPM-style version information */ 53150849Sscottl#define DRIVER_MAJOR_VERSION 2005 /* year */ 54150849Sscottl#define DRIVER_MINOR_VERSION 9 /* month */ 55150849Sscottl#define DRIVER_SUB_VERSION 29 /* day */ 56150849Sscottl 57150849Sscottl/* netgraph stuff */ 58150849Sscottl#define NG_LMC_NODE_TYPE DEVICE_NAME 59150849Sscottl#define NGM_LMC_COOKIE 1128054761 /* date -u +'%s' */ 60150849Sscottl 61150849Sscottl/* Tulip PCI configuration registers */ 62150849Sscottl#define TLP_CFID 0x00 /* 0: CFg ID register */ 63150849Sscottl#define TLP_CFCS 0x04 /* 1: CFg Command/Status */ 64150849Sscottl#define TLP_CFRV 0x08 /* 2: CFg ReVision */ 65150849Sscottl#define TLP_CFLT 0x0C /* 3: CFg Latency Timer */ 66150849Sscottl#define TLP_CBIO 0x10 /* 4: Cfg Base IO address */ 67150849Sscottl#define TLP_CBMA 0x14 /* 5: Cfg Base Mem Addr */ 68150849Sscottl#define TLP_CSID 0x2C /* 11: Cfg Subsys ID reg */ 69150849Sscottl#define TLP_CFIT 0x3C /* 15: CFg InTerrupt */ 70150849Sscottl#define TLP_CFDD 0x40 /* 16: CFg Driver Data */ 71150849Sscottl 72150849Sscottl#define TLP_CFID_TULIP 0x00091011 /* DEC 21140A Ethernet chip */ 73150849Sscottl 74150849Sscottl#define TLP_CFCS_MSTR_ABORT 0x20000000 75150849Sscottl#define TLP_CFCS_TARG_ABORT 0x10000000 76150849Sscottl#define TLP_CFCS_SYS_ERROR 0x00000100 77150849Sscottl#define TLP_CFCS_PAR_ERROR 0x00000040 78150849Sscottl#define TLP_CFCS_MWI_ENABLE 0x00000010 79150849Sscottl#define TLP_CFCS_BUS_MASTER 0x00000004 80150849Sscottl#define TLP_CFCS_MEM_ENABLE 0x00000002 81150849Sscottl#define TLP_CFCS_IO_ENABLE 0x00000001 82150849Sscottl 83150849Sscottl#define TLP_CFLT_LATENCY 0x0000FF00 84150849Sscottl#define TLP_CFLT_CACHE 0x000000FF 85150849Sscottl 86150849Sscottl#define TLP_CSID_HSSI 0x00031376 /* LMC 5200 HSSI card */ 87150849Sscottl#define TLP_CSID_T3 0x00041376 /* LMC 5245 T3 card */ 88150849Sscottl#define TLP_CSID_SSI 0x00051376 /* LMC 1000 SSI card */ 89150849Sscottl#define TLP_CSID_T1E1 0x00061376 /* LMC 1200 T1E1 card */ 90150849Sscottl#define TLP_CSID_HSSIc 0x00071376 /* LMC 5200 HSSI cPCI */ 91150849Sscottl#define TLP_CSID_SDSL 0x00081376 /* LMC 1168 SDSL card */ 92150849Sscottl 93150849Sscottl#define TLP_CFIT_MAX_LAT 0xFF000000 94150849Sscottl 95150849Sscottl#define TLP_CFDD_SLEEP 0x80000000 96150849Sscottl#define TLP_CFDD_SNOOZE 0x40000000 97150849Sscottl 98150849Sscottl/* Tulip Control and Status Registers */ 99150849Sscottl#define TLP_CSR_STRIDE 8 /* 64 bits */ 100150849Sscottl#define TLP_BUS_MODE 0 * TLP_CSR_STRIDE 101150849Sscottl#define TLP_TX_POLL 1 * TLP_CSR_STRIDE 102150849Sscottl#define TLP_RX_POLL 2 * TLP_CSR_STRIDE 103150849Sscottl#define TLP_RX_LIST 3 * TLP_CSR_STRIDE 104150849Sscottl#define TLP_TX_LIST 4 * TLP_CSR_STRIDE 105150849Sscottl#define TLP_STATUS 5 * TLP_CSR_STRIDE 106150849Sscottl#define TLP_OP_MODE 6 * TLP_CSR_STRIDE 107150849Sscottl#define TLP_INT_ENBL 7 * TLP_CSR_STRIDE 108150849Sscottl#define TLP_MISSED 8 * TLP_CSR_STRIDE 109150849Sscottl#define TLP_SROM_MII 9 * TLP_CSR_STRIDE 110150849Sscottl#define TLP_BIOS_ROM 10 * TLP_CSR_STRIDE 111150849Sscottl#define TLP_TIMER 11 * TLP_CSR_STRIDE 112150849Sscottl#define TLP_GPIO 12 * TLP_CSR_STRIDE 113150849Sscottl#define TLP_CSR13 13 * TLP_CSR_STRIDE 114150849Sscottl#define TLP_CSR14 14 * TLP_CSR_STRIDE 115150849Sscottl#define TLP_WDOG 15 * TLP_CSR_STRIDE 116150849Sscottl#define TLP_CSR_SIZE 128 /* IO bus space size */ 117150849Sscottl 118150849Sscottl/* CSR 0 - PCI Bus Mode Register */ 119150849Sscottl#define TLP_BUS_WRITE_INVAL 0x01000000 /* DONT USE! */ 120150849Sscottl#define TLP_BUS_READ_LINE 0x00800000 121150849Sscottl#define TLP_BUS_READ_MULT 0x00200000 122150849Sscottl#define TLP_BUS_DESC_BIGEND 0x00100000 123150849Sscottl#define TLP_BUS_TAP 0x000E0000 124150849Sscottl#define TLP_BUS_CAL 0x0000C000 125150849Sscottl#define TLP_BUS_PBL 0x00003F00 126150849Sscottl#define TLP_BUS_DATA_BIGEND 0x00000080 127150849Sscottl#define TLP_BUS_DSL 0x0000007C 128150849Sscottl#define TLP_BUS_ARB 0x00000002 129150849Sscottl#define TLP_BUS_RESET 0x00000001 130150849Sscottl#define TLP_BUS_CAL_SHIFT 14 131150849Sscottl#define TLP_BUS_PBL_SHIFT 8 132150849Sscottl 133150849Sscottl/* CSR 5 - Status Register */ 134150849Sscottl#define TLP_STAT_FATAL_BITS 0x03800000 135150849Sscottl#define TLP_STAT_TX_FSM 0x00700000 136150849Sscottl#define TLP_STAT_RX_FSM 0x000E0000 137150849Sscottl#define TLP_STAT_FATAL_ERROR 0x00002000 138150849Sscottl#define TLP_STAT_TX_UNDERRUN 0x00000020 139150849Sscottl#define TLP_STAT_FATAL_SHIFT 23 140150849Sscottl 141150849Sscottl/* CSR 6 - Operating Mode Register */ 142150849Sscottl#define TLP_OP_RECEIVE_ALL 0x40000000 143150849Sscottl#define TLP_OP_MUST_BE_ONE 0x02000000 144150849Sscottl#define TLP_OP_NO_HEART_BEAT 0x00080000 145150849Sscottl#define TLP_OP_PORT_SELECT 0x00040000 146150849Sscottl#define TLP_OP_TX_THRESH 0x0000C000 147150849Sscottl#define TLP_OP_TX_RUN 0x00002000 148150849Sscottl#define TLP_OP_LOOP_MODE 0x00000C00 149150849Sscottl#define TLP_OP_EXT_LOOP 0x00000800 150150849Sscottl#define TLP_OP_INT_LOOP 0x00000400 151150849Sscottl#define TLP_OP_FULL_DUPLEX 0x00000200 152150849Sscottl#define TLP_OP_PROMISCUOUS 0x00000040 153150849Sscottl#define TLP_OP_PASS_BAD_PKT 0x00000008 154150849Sscottl#define TLP_OP_RX_RUN 0x00000002 155150849Sscottl#define TLP_OP_TR_SHIFT 14 156150849Sscottl#define TLP_OP_INIT (TLP_OP_PORT_SELECT | \ 157150849Sscottl TLP_OP_FULL_DUPLEX | \ 158150849Sscottl TLP_OP_MUST_BE_ONE | \ 159150849Sscottl TLP_OP_NO_HEART_BEAT | \ 160150849Sscottl TLP_OP_RECEIVE_ALL | \ 161150849Sscottl TLP_OP_PROMISCUOUS | \ 162150849Sscottl TLP_OP_PASS_BAD_PKT | \ 163150849Sscottl TLP_OP_RX_RUN | \ 164150849Sscottl TLP_OP_TX_RUN) 165150849Sscottl 166150849Sscottl/* CSR 7 - Interrupt Enable Register */ 167150849Sscottl#define TLP_INT_NORMAL_INTR 0x00010000 168150849Sscottl#define TLP_INT_ABNRML_INTR 0x00008000 169150849Sscottl#define TLP_INT_FATAL_ERROR 0x00002000 170150849Sscottl#define TLP_INT_RX_NO_BUFS 0x00000080 171150849Sscottl#define TLP_INT_RX_INTR 0x00000040 172150849Sscottl#define TLP_INT_TX_UNDERRUN 0x00000020 173150849Sscottl#define TLP_INT_TX_INTR 0x00000001 174150849Sscottl#define TLP_INT_DISABLE 0 175150849Sscottl#define TLP_INT_TX (TLP_INT_NORMAL_INTR | \ 176150849Sscottl TLP_INT_ABNRML_INTR | \ 177150849Sscottl TLP_INT_FATAL_ERROR | \ 178150849Sscottl TLP_INT_TX_UNDERRUN | \ 179150849Sscottl TLP_INT_TX_INTR) 180150849Sscottl#define TLP_INT_RX (TLP_INT_NORMAL_INTR | \ 181150849Sscottl TLP_INT_ABNRML_INTR | \ 182150849Sscottl TLP_INT_FATAL_ERROR | \ 183150849Sscottl TLP_INT_RX_NO_BUFS | \ 184150849Sscottl TLP_INT_RX_INTR) 185150849Sscottl#define TLP_INT_TXRX (TLP_INT_TX | TLP_INT_RX) 186150849Sscottl 187150849Sscottl/* CSR 8 - RX Missed Frames & Overrun Register */ 188150849Sscottl#define TLP_MISS_OCO 0x10000000 189150849Sscottl#define TLP_MISS_OVERRUN 0x0FFE0000 190150849Sscottl#define TLP_MISS_MFO 0x00010000 191150849Sscottl#define TLP_MISS_MISSED 0x0000FFFF 192150849Sscottl#define TLP_OVERRUN_SHIFT 17 193150849Sscottl 194150849Sscottl/* CSR 9 - SROM & MII & Boot ROM Register */ 195150849Sscottl#define TLP_MII_MDIN 0x00080000 196150849Sscottl#define TLP_MII_MDOE 0x00040000 197150849Sscottl#define TLP_MII_MDOUT 0x00020000 198150849Sscottl#define TLP_MII_MDC 0x00010000 199150849Sscottl 200150849Sscottl#define TLP_BIOS_RD 0x00004000 201150849Sscottl#define TLP_BIOS_WR 0x00002000 202150849Sscottl#define TLP_BIOS_SEL 0x00001000 203150849Sscottl 204150849Sscottl#define TLP_SROM_RD 0x00004000 205150849Sscottl#define TLP_SROM_SEL 0x00000800 206150849Sscottl#define TLP_SROM_DOUT 0x00000008 207150849Sscottl#define TLP_SROM_DIN 0x00000004 208150849Sscottl#define TLP_SROM_CLK 0x00000002 209150849Sscottl#define TLP_SROM_CS 0x00000001 210150849Sscottl 211150849Sscottl/* CSR 12 - General Purpose IO register */ 212150849Sscottl#define TLP_GPIO_DIR 0x00000100 213150849Sscottl 214150849Sscottl/* CSR 15 - Watchdog Timer Register */ 215150849Sscottl#define TLP_WDOG_RX_OFF 0x00000010 216150849Sscottl#define TLP_WDOG_TX_OFF 0x00000001 217150849Sscottl#define TLP_WDOG_INIT (TLP_WDOG_TX_OFF | \ 218150849Sscottl TLP_WDOG_RX_OFF) 219150849Sscottl 220150849Sscottl/* GPIO bits common to all cards */ 221150849Sscottl#define GPIO_INIT 0x01 /* from Xilinx */ 222150849Sscottl#define GPIO_RESET 0x02 /* to Xilinx */ 223150849Sscottl/* bits 2 and 3 vary with board type -- see below */ 224150849Sscottl#define GPIO_MODE 0x10 /* to Xilinx */ 225150849Sscottl#define GPIO_DP 0x20 /* to/from Xilinx */ 226150849Sscottl#define GPIO_DATA 0x40 /* serial data */ 227150849Sscottl#define GPIO_CLK 0x80 /* serial clock */ 228150849Sscottl 229150849Sscottl/* HSSI GPIO bits */ 230150849Sscottl#define GPIO_HSSI_ST 0x04 /* send timing sense (deprecated) */ 231150849Sscottl#define GPIO_HSSI_TXCLK 0x08 /* clock source */ 232150849Sscottl 233150849Sscottl/* HSSIc GPIO bits */ 234150849Sscottl#define GPIO_HSSI_SYNTH 0x04 /* Synth osc chip select */ 235150849Sscottl#define GPIO_HSSI_DCE 0x08 /* provide clock on TXCLOCK output */ 236150849Sscottl 237150849Sscottl/* T3 GPIO bits */ 238150849Sscottl#define GPIO_T3_DAC 0x04 /* DAC chip select */ 239298955Spfg#define GPIO_T3_INTEN 0x08 /* Framer Interrupt enable */ 240150849Sscottl 241150849Sscottl/* SSI GPIO bits */ 242150849Sscottl#define GPIO_SSI_SYNTH 0x04 /* Synth osc chip select */ 243150849Sscottl#define GPIO_SSI_DCE 0x08 /* provide clock on TXCLOCK output */ 244150849Sscottl 245150849Sscottl/* T1E1 GPIO bits */ 246298955Spfg#define GPIO_T1_INTEN 0x08 /* Framer Interrupt enable */ 247150849Sscottl 248150849Sscottl/* MII register 16 bits common to all cards */ 249150849Sscottl/* NB: LEDs for HSSI & SSI are in DIFFERENT bits than for T1E1 & T3; oops */ 250150849Sscottl/* NB: CRC32 for HSSI & SSI is in DIFFERENT bit than for T1E1 & T3; oops */ 251150849Sscottl#define MII16_LED_ALL 0x0780 /* RW: LED bit mask */ 252150849Sscottl#define MII16_FIFO 0x0800 /* RW: 1=reset, 0=not reset */ 253150849Sscottl 254150849Sscottl/* MII register 16 bits for HSSI */ 255150849Sscottl#define MII16_HSSI_TA 0x0001 /* RW: host ready; host->modem */ 256150849Sscottl#define MII16_HSSI_CA 0x0002 /* RO: modem ready; modem->host */ 257150849Sscottl#define MII16_HSSI_LA 0x0004 /* RW: loopback A; host->modem */ 258150849Sscottl#define MII16_HSSI_LB 0x0008 /* RW: loopback B; host->modem */ 259150849Sscottl#define MII16_HSSI_LC 0x0010 /* RO: loopback C; modem->host */ 260150849Sscottl#define MII16_HSSI_TM 0x0020 /* RO: test mode; modem->host */ 261150849Sscottl#define MII16_HSSI_CRC32 0x0040 /* RW: CRC length 16/32 */ 262150849Sscottl#define MII16_HSSI_LED_LL 0x0080 /* RW: lower left - green */ 263150849Sscottl#define MII16_HSSI_LED_LR 0x0100 /* RW: lower right - green */ 264150849Sscottl#define MII16_HSSI_LED_UL 0x0200 /* RW: upper left - green */ 265150849Sscottl#define MII16_HSSI_LED_UR 0x0400 /* RW: upper right - red */ 266150849Sscottl#define MII16_HSSI_FIFO 0x0800 /* RW: reset fifos */ 267150849Sscottl#define MII16_HSSI_FORCECA 0x1000 /* RW: [cPCI] force CA on */ 268150849Sscottl#define MII16_HSSI_CLKMUX 0x6000 /* RW: [cPCI] TX clock selection */ 269150849Sscottl#define MII16_HSSI_LOOP 0x8000 /* RW: [cPCI] LOOP TX into RX */ 270150849Sscottl#define MII16_HSSI_MODEM 0x003F /* TA+CA+LA+LB+LC+TM */ 271150849Sscottl 272150849Sscottl/* MII register 16 bits for DS3 */ 273150849Sscottl#define MII16_DS3_ZERO 0x0001 /* RW: short/long cables */ 274150849Sscottl#define MII16_DS3_TRLBK 0x0002 /* RW: loop towards host */ 275150849Sscottl#define MII16_DS3_LNLBK 0x0004 /* RW: loop towards net */ 276150849Sscottl#define MII16_DS3_RAIS 0x0008 /* RO: LIU receive AIS (depr) */ 277150849Sscottl#define MII16_DS3_TAIS 0x0010 /* RW: LIU transmit AIS (depr) */ 278150849Sscottl#define MII16_DS3_BIST 0x0020 /* RO: LIU QRSS patt match (depr) */ 279150849Sscottl#define MII16_DS3_DLOS 0x0040 /* RO: LIU Digital LOS (depr) */ 280150849Sscottl#define MII16_DS3_LED_BLU 0x0080 /* RW: lower right - blue */ 281150849Sscottl#define MII16_DS3_LED_YEL 0x0100 /* RW: lower left - yellow */ 282150849Sscottl#define MII16_DS3_LED_RED 0x0200 /* RW: upper right - red */ 283150849Sscottl#define MII16_DS3_LED_GRN 0x0400 /* RW: upper left - green */ 284150849Sscottl#define MII16_DS3_FIFO 0x0800 /* RW: reset fifos */ 285150849Sscottl#define MII16_DS3_CRC32 0x1000 /* RW: CRC length 16/32 */ 286150849Sscottl#define MII16_DS3_SCRAM 0x2000 /* RW: payload scrambler */ 287150849Sscottl#define MII16_DS3_POLY 0x4000 /* RW: 1=Larse, 0=DigLink|Kentrox */ 288150849Sscottl#define MII16_DS3_FRAME 0x8000 /* RW: 1=stop txframe pulses */ 289150849Sscottl 290150849Sscottl/* MII register 16 bits for SSI */ 291150849Sscottl#define MII16_SSI_DTR 0x0001 /* RW: DTR host->modem */ 292150849Sscottl#define MII16_SSI_DSR 0x0002 /* RO: DSR modem->host */ 293150849Sscottl#define MII16_SSI_RTS 0x0004 /* RW: RTS host->modem */ 294150849Sscottl#define MII16_SSI_CTS 0x0008 /* RO: CTS modem->host */ 295150849Sscottl#define MII16_SSI_DCD 0x0010 /* RW: DCD modem<->host */ 296150849Sscottl#define MII16_SSI_RI 0x0020 /* RO: RI modem->host */ 297150849Sscottl#define MII16_SSI_CRC32 0x0040 /* RW: CRC length 16/32 */ 298150849Sscottl#define MII16_SSI_LED_LL 0x0080 /* RW: lower left - green */ 299150849Sscottl#define MII16_SSI_LED_LR 0x0100 /* RW: lower right - green */ 300150849Sscottl#define MII16_SSI_LED_UL 0x0200 /* RW: upper left - green */ 301150849Sscottl#define MII16_SSI_LED_UR 0x0400 /* RW: upper right - red */ 302150849Sscottl#define MII16_SSI_FIFO 0x0800 /* RW: reset fifos */ 303150849Sscottl#define MII16_SSI_LL 0x1000 /* RW: LL: host->modem */ 304150849Sscottl#define MII16_SSI_RL 0x2000 /* RW: RL: host->modem */ 305150849Sscottl#define MII16_SSI_TM 0x4000 /* RO: TM: modem->host */ 306150849Sscottl#define MII16_SSI_LOOP 0x8000 /* RW: Loop at ext conn */ 307150849Sscottl#define MII16_SSI_MODEM 0x703F /* DTR+DSR+RTS+CTS+DCD+RI+LL+RL+TM */ 308150849Sscottl 309150849Sscottl/* Mii register 17 has the SSI cable bits */ 310150849Sscottl#define MII17_SSI_CABLE_SHIFT 3 /* shift to get cable type */ 311150849Sscottl#define MII17_SSI_CABLE_MASK 0x0038 /* RO: mask to get cable type */ 312150849Sscottl#define MII17_SSI_PRESCALE 0x0040 /* RW: divide by: 0=16; 1=512 */ 313150849Sscottl#define MII17_SSI_ITF 0x0100 /* RW: fill with: 0=flags; 1=ones */ 314150849Sscottl#define MII17_SSI_NRZI 0x0400 /* RW: coding: NRZ= 0; NRZI=1 */ 315150849Sscottl 316150849Sscottl/* MII register 16 bits for T1/E1 */ 317150849Sscottl#define MII16_T1_UNUSED1 0x0001 318150849Sscottl#define MII16_T1_INVERT 0x0002 /* RW: invert data (for SF/AMI) */ 319150849Sscottl#define MII16_T1_XOE 0x0004 /* RW: TX Output Enable; 0=disable */ 320150849Sscottl#define MII16_T1_RST 0x0008 /* RW: Bt8370 chip reset */ 321150849Sscottl#define MII16_T1_Z 0x0010 /* RW: output impedance T1=1 E1=0 */ 322150849Sscottl#define MII16_T1_INTR 0x0020 /* RO: interrupt from Bt8370 */ 323150849Sscottl#define MII16_T1_ONESEC 0x0040 /* RO: one second square wave */ 324150849Sscottl#define MII16_T1_LED_BLU 0x0080 /* RW: lower right - blue */ 325150849Sscottl#define MII16_T1_LED_YEL 0x0100 /* RW: lower left - yellow */ 326150849Sscottl#define MII16_T1_LED_RED 0x0200 /* RW: upper right - red */ 327150849Sscottl#define MII16_T1_LED_GRN 0x0400 /* RW: upper left - green */ 328150849Sscottl#define MII16_T1_FIFO 0x0800 /* RW: reset fifos */ 329150849Sscottl#define MII16_T1_CRC32 0x1000 /* RW: CRC length 16/32 */ 330150849Sscottl#define MII16_T1_UNUSED2 0xE000 331150849Sscottl 332150849Sscottl/* T3 framer: RW=Read/Write; RO=Read-Only; RC=Read/Clr; WO=Write-Only */ 333150849Sscottl#define T3CSR_STAT0 0x00 /* RO: real-time status */ 334150849Sscottl#define T3CSR_CTL1 0x01 /* RW: global control bits */ 335150849Sscottl#define T3CSR_FEBE 0x02 /* RC: Far End Block Error Counter */ 336150849Sscottl#define T3CSR_CERR 0x03 /* RC: C-bit Parity Error Counter */ 337150849Sscottl#define T3CSR_PERR 0x04 /* RC: P-bit Parity Error Counter */ 338150849Sscottl#define T3CSR_TX_FEAC 0x05 /* RW: Far End Alarm & Control */ 339150849Sscottl#define T3CSR_RX_FEAC 0x06 /* RO: Far End Alarm & Control */ 340150849Sscottl#define T3CSR_STAT7 0x07 /* RL: latched real-time status */ 341150849Sscottl#define T3CSR_CTL8 0x08 /* RW: extended global ctl bits */ 342150849Sscottl#define T3CSR_STAT9 0x09 /* RL: extended status bits */ 343150849Sscottl#define T3CSR_FERR 0x0A /* RC: F-bit Error Counter */ 344150849Sscottl#define T3CSR_MERR 0x0B /* RC: M-bit Error Counter */ 345150849Sscottl#define T3CSR_CTL12 0x0C /* RW: more extended ctl bits */ 346150849Sscottl#define T3CSR_DBL_FEAC 0x0D /* RW: TX double FEAC */ 347150849Sscottl#define T3CSR_CTL14 0x0E /* RW: even more extended ctl bits */ 348150849Sscottl#define T3CSR_FEAC_STK 0x0F /* RO: RX FEAC stack */ 349150849Sscottl#define T3CSR_STAT16 0x10 /* RL: extended latched status */ 350150849Sscottl#define T3CSR_INTEN 0x11 /* RW: interrupt enable */ 351150849Sscottl#define T3CSR_CVLO 0x12 /* RC: coding violation cntr LSB */ 352150849Sscottl#define T3CSR_CVHI 0x13 /* RC: coding violation cntr MSB */ 353150849Sscottl#define T3CSR_CTL20 0x14 /* RW: yet more extended ctl bits */ 354150849Sscottl 355150849Sscottl#define CTL1_XTX 0x01 /* Transmit X-bit value */ 356150849Sscottl#define CTL1_3LOOP 0x02 /* framer loop back */ 357150849Sscottl#define CTL1_SER 0x04 /* SERial interface selected */ 358150849Sscottl#define CTL1_M13MODE 0x08 /* M13 frame format */ 359150849Sscottl#define CTL1_TXIDL 0x10 /* Transmit Idle signal */ 360150849Sscottl#define CTL1_ENAIS 0x20 /* Enable AIS upon LOS */ 361150849Sscottl#define CTL1_TXAIS 0x40 /* Transmit Alarm Indication Sig */ 362150849Sscottl#define CTL1_NOFEBE 0x80 /* No Far End Block Errors */ 363150849Sscottl 364150849Sscottl#define CTL5_EMODE 0x80 /* rev B Extended features enabled */ 365150849Sscottl#define CTL5_START 0x40 /* transmit the FEAC msg now */ 366150849Sscottl 367150849Sscottl#define CTL8_FBEC 0x80 /* F-Bit Error Count control */ 368150849Sscottl#define CTL8_TBLU 0x20 /* Transmit Blue signal */ 369150849Sscottl 370150849Sscottl#define STAT9_SEF 0x80 /* Severely Errored Frame */ 371150849Sscottl#define STAT9_RBLU 0x20 /* Receive Blue signal */ 372150849Sscottl 373150849Sscottl#define CTL12_RTPLLEN 0x80 /* Rx-to-Tx Payload Lpbk Lock ENbl */ 374150849Sscottl#define CTL12_RTPLOOP 0x40 /* Rx-to-Tx Payload Loopback */ 375150849Sscottl#define CTL12_DLCB1 0x08 /* Data Link C-Bits forced to 1 */ 376150849Sscottl#define CTL12_C21 0x04 /* C2 forced to 1 */ 377150849Sscottl#define CTL12_MCB1 0x02 /* Most C-Bits forced to 1 */ 378150849Sscottl 379150849Sscottl#define CTL13_DFEXEC 0x40 /* Execute Double FEAC */ 380150849Sscottl 381150849Sscottl#define CTL14_FEAC10 0x80 /* Transmit FEAC word 10 times */ 382150849Sscottl#define CTL14_RGCEN 0x20 /* Receive Gapped Clock Out Enbl */ 383150849Sscottl#define CTL14_TGCEN 0x10 /* Timing Gen Gapped Clk Out Enbl */ 384150849Sscottl 385150849Sscottl#define FEAC_STK_MORE 0x80 /* FEAC stack has more FEACs */ 386150849Sscottl#define FEAC_STK_VALID 0x40 /* FEAC stack is valid */ 387150849Sscottl#define FEAC_STK_FEAC 0x3F /* FEAC stack FEAC data */ 388150849Sscottl 389150849Sscottl#define STAT16_XERR 0x01 /* X-bit Error */ 390150849Sscottl#define STAT16_SEF 0x02 /* Severely Errored Frame */ 391150849Sscottl#define STAT16_RTLOC 0x04 /* Rx/Tx Loss Of Clock */ 392150849Sscottl#define STAT16_FEAC 0x08 /* new FEAC msg */ 393150849Sscottl#define STAT16_RIDL 0x10 /* channel IDLe signal */ 394150849Sscottl#define STAT16_RAIS 0x20 /* Alarm Indication Signal */ 395150849Sscottl#define STAT16_ROOF 0x40 /* Out Of Frame sync */ 396150849Sscottl#define STAT16_RLOS 0x80 /* Loss Of Signal */ 397150849Sscottl 398150849Sscottl#define CTL20_CVEN 0x01 /* Coding Violation Counter Enbl */ 399150849Sscottl 400150849Sscottl/* T1.107 Bit Oriented C-Bit Parity Far End Alarm Control and Status codes */ 401150849Sscottl#define T3BOP_OOF 0x00 /* Yellow alarm status */ 402150849Sscottl#define T3BOP_LINE_UP 0x07 /* line loopback activate */ 403150849Sscottl#define T3BOP_LINE_DOWN 0x1C /* line loopback deactivate */ 404150849Sscottl#define T3BOP_LOOP_DS3 0x1B /* loopback full DS3 */ 405150849Sscottl#define T3BOP_IDLE 0x1A /* IDLE alarm status */ 406150849Sscottl#define T3BOP_AIS 0x16 /* AIS alarm status */ 407150849Sscottl#define T3BOP_LOS 0x0E /* LOS alarm status */ 408150849Sscottl 409150849Sscottl/* T1E1 regs; RW=Read/Write; RO=Read-Only; RC=Read/Clr; WO=Write-Only */ 410150849Sscottl#define Bt8370_DID 0x000 /* RO: Device ID */ 411150849Sscottl#define Bt8370_CR0 0x001 /* RW; Primary Control Register */ 412150849Sscottl#define Bt8370_JAT_CR 0x002 /* RW: Jitter Attenuator CR */ 413150849Sscottl#define Bt8370_IRR 0x003 /* RO: Interrupt Request Reg */ 414150849Sscottl#define Bt8370_ISR7 0x004 /* RC: Alarm 1 Interrupt Status */ 415150849Sscottl#define Bt8370_ISR6 0x005 /* RC: Alarm 2 Interrupt Status */ 416150849Sscottl#define Bt8370_ISR5 0x006 /* RC: Error Interrupt Status */ 417150849Sscottl#define Bt8370_ISR4 0x007 /* RC; Cntr Ovfl Interrupt Status */ 418150849Sscottl#define Bt8370_ISR3 0x008 /* RC: Timer Interrupt Status */ 419150849Sscottl#define Bt8370_ISR2 0x009 /* RC: Data Link 1 Int Status */ 420150849Sscottl#define Bt8370_ISR1 0x00A /* RC: Data Link 2 Int Status */ 421150849Sscottl#define Bt8370_ISR0 0x00B /* RC: Pattrn Interrupt Status */ 422150849Sscottl#define Bt8370_IER7 0x00C /* RW: Alarm 1 Interrupt Enable */ 423150849Sscottl#define Bt8370_IER6 0x00D /* RW: Alarm 2 Interrupt Enable */ 424150849Sscottl#define Bt8370_IER5 0x00E /* RW: Error Interrupt Enable */ 425150849Sscottl#define Bt8370_IER4 0x00F /* RW: Cntr Ovfl Interrupt Enable */ 426150849Sscottl 427150849Sscottl#define Bt8370_IER3 0x010 /* RW: Timer Interrupt Enable */ 428150849Sscottl#define Bt8370_IER2 0x011 /* RW: Data Link 1 Int Enable */ 429150849Sscottl#define Bt8370_IER1 0x012 /* RW: Data Link 2 Int Enable */ 430150849Sscottl#define Bt8370_IER0 0x013 /* RW: Pattern Interrupt Enable */ 431150849Sscottl#define Bt8370_LOOP 0x014 /* RW: Loopback Config Reg */ 432150849Sscottl#define Bt8370_DL3_TS 0x015 /* RW: External Data Link Channel */ 433150849Sscottl#define Bt8370_DL3_BIT 0x016 /* RW: External Data Link Bit */ 434150849Sscottl#define Bt8370_FSTAT 0x017 /* RO: Offline Framer Status */ 435150849Sscottl#define Bt8370_PIO 0x018 /* RW: Programmable Input/Output */ 436150849Sscottl#define Bt8370_POE 0x019 /* RW: Programmable Output Enable */ 437150849Sscottl#define Bt8370_CMUX 0x01A /* RW: Clock Input Mux */ 438150849Sscottl#define Bt8370_TMUX 0x01B /* RW: Test Mux Config */ 439150849Sscottl#define Bt8370_TEST 0x01C /* RW: Test Config */ 440150849Sscottl 441150849Sscottl#define Bt8370_LIU_CR 0x020 /* RW: Line Intf Unit Config Reg */ 442150849Sscottl#define Bt8370_RSTAT 0x021 /* RO; Receive LIU Status */ 443150849Sscottl#define Bt8370_RLIU_CR 0x022 /* RW: Receive LIU Config */ 444150849Sscottl#define Bt8370_LPF 0x023 /* RW: RPLL Low Pass Filter */ 445150849Sscottl#define Bt8370_VGA_MAX 0x024 /* RW: Variable Gain Amplifier Max */ 446150849Sscottl#define Bt8370_EQ_DAT 0x025 /* RW: Equalizer Coeff Data Reg */ 447150849Sscottl#define Bt8370_EQ_PTR 0x026 /* RW: Equzlizer Coeff Table Ptr */ 448150849Sscottl#define Bt8370_DSLICE 0x027 /* RW: Data Slicer Threshold */ 449150849Sscottl#define Bt8370_EQ_OUT 0x028 /* RW: Equalizer Output Levels */ 450150849Sscottl#define Bt8370_VGA 0x029 /* RO: Variable Gain Ampl Status */ 451150849Sscottl#define Bt8370_PRE_EQ 0x02A /* RW: Pre-Equalizer */ 452150849Sscottl 453150849Sscottl#define Bt8370_COEFF0 0x030 /* RO: LMS Adj Eq Coeff Status */ 454150849Sscottl#define Bt8370_GAIN0 0x038 /* RW: Equalizer Gain Thresh */ 455150849Sscottl#define Bt8370_GAIN1 0x039 /* RW: Equalizer Gain Thresh */ 456150849Sscottl#define Bt8370_GAIN2 0x03A /* RW: Equalizer Gain Thresh */ 457150849Sscottl#define Bt8370_GAIN3 0x03B /* RW: Equalizer Gain Thresh */ 458150849Sscottl#define Bt8370_GAIN4 0x03C /* RW: Equalizer Gain Thresh */ 459150849Sscottl 460150849Sscottl#define Bt8370_RCR0 0x040 /* RW: Rx Configuration */ 461150849Sscottl#define Bt8370_RPATT 0x041 /* RW: Rx Test Pattern Config */ 462150849Sscottl#define Bt8370_RLB 0x042 /* RW: Rx Loopback Code Detr Conf */ 463150849Sscottl#define Bt8370_LBA 0x043 /* RW: Loopback Activate Code Patt */ 464150849Sscottl#define Bt8370_LBD 0x044 /* RW: Loopback Deact Code Patt */ 465150849Sscottl#define Bt8370_RALM 0x045 /* RW: Rx Alarm Signal Config */ 466150849Sscottl#define Bt8370_LATCH 0x046 /* RW: Alarm/Err/Cntr Latch Config */ 467150849Sscottl#define Bt8370_ALM1 0x047 /* RO: Alarm 1 Status */ 468150849Sscottl#define Bt8370_ALM2 0x048 /* RO: Alarm 2 Status */ 469150849Sscottl#define Bt8370_ALM3 0x049 /* RO: Alarm 3 Status */ 470150849Sscottl 471150849Sscottl#define Bt8370_FERR_LO 0x050 /* RC: Framing Bit Error Cntr LSB */ 472150849Sscottl#define Bt8370_FERR_HI 0x051 /* RC: Framing Bit Error Cntr MSB */ 473150849Sscottl#define Bt8370_CRC_LO 0x052 /* RC: CRC Error Counter LSB */ 474150849Sscottl#define Bt8370_CRC_HI 0x053 /* RC: CRC Error Counter MSB */ 475150849Sscottl#define Bt8370_LCV_LO 0x054 /* RC: Line Code Viol Counter LSB */ 476150849Sscottl#define Bt8370_LCV_HI 0x055 /* RC: Line Code Viol Counter MSB */ 477150849Sscottl#define Bt8370_FEBE_LO 0x056 /* RC: Far End Block Err Cntr LSB */ 478150849Sscottl#define Bt8370_FEBE_HI 0x057 /* RC: Far End Block Err Cntr MSB */ 479150849Sscottl#define Bt8370_BERR_LO 0x058 /* RC: PRBS Bit Error Counter LSB */ 480150849Sscottl#define Bt8370_BERR_HI 0x059 /* RC: PRBS Bit Error Counter MSB */ 481150849Sscottl#define Bt8370_AERR 0x05A /* RC: SEF/LOF/COFA counter */ 482150849Sscottl#define Bt8370_RSA4 0x05B /* RO: Rx Sa4 Byte Buffer */ 483150849Sscottl#define Bt8370_RSA5 0x05C /* RO: Rx Sa5 Byte Buffer */ 484150849Sscottl#define Bt8370_RSA6 0x05D /* RO: Rx Sa6 Byte Buffer */ 485150849Sscottl#define Bt8370_RSA7 0x05E /* RO: Rx Sa7 Byte Buffer */ 486150849Sscottl#define Bt8370_RSA8 0x05F /* RO: Rx Sa8 Byte Buffer */ 487150849Sscottl 488150849Sscottl#define Bt8370_SHAPE0 0x060 /* RW: Tx Pulse Shape Config */ 489150849Sscottl#define Bt8370_TLIU_CR 0x068 /* RW: Tx LIU Config Reg */ 490150849Sscottl 491150849Sscottl#define Bt8370_TCR0 0x070 /* RW: Tx Framer Config */ 492150849Sscottl#define Bt8370_TCR1 0x071 /* RW: Txter Configuration */ 493150849Sscottl#define Bt8370_TFRM 0x072 /* RW: Tx Frame Format */ 494150849Sscottl#define Bt8370_TERROR 0x073 /* RW: Tx Error Insert */ 495150849Sscottl#define Bt8370_TMAN 0x074 /* RW: Tx Manual Sa/FEBE Config */ 496150849Sscottl#define Bt8370_TALM 0x075 /* RW: Tx Alarm Signal Config */ 497150849Sscottl#define Bt8370_TPATT 0x076 /* RW: Tx Test Pattern Config */ 498150849Sscottl#define Bt8370_TLB 0x077 /* RW: Tx Inband Loopback Config */ 499150849Sscottl#define Bt8370_LBP 0x078 /* RW: Tx Inband Loopback Patt */ 500150849Sscottl#define Bt8370_TSA4 0x07B /* RW: Tx Sa4 Byte Buffer */ 501150849Sscottl#define Bt8370_TSA5 0x07C /* RW: Tx Sa5 Byte Buffer */ 502150849Sscottl#define Bt8370_TSA6 0x07D /* RW: Tx Sa6 Byte Buffer */ 503150849Sscottl#define Bt8370_TSA7 0x07E /* RW: Tx Sa7 Byte Buffer */ 504150849Sscottl#define Bt8370_TSA8 0x07F /* RW: Tx Sa8 Byte Buffer */ 505150849Sscottl 506150849Sscottl#define Bt8370_CLAD_CR 0x090 /* RW: Clock Rate Adapter Config */ 507150849Sscottl#define Bt8370_CSEL 0x091 /* RW: CLAD Frequency Select */ 508150849Sscottl#define Bt8370_CPHASE 0x092 /* RW: CLAD Phase Det Scale Factor */ 509150849Sscottl#define Bt8370_CTEST 0x093 /* RW: CLAD Test */ 510150849Sscottl 511150849Sscottl#define Bt8370_BOP 0x0A0 /* RW: Bit Oriented Protocol Xcvr */ 512150849Sscottl#define Bt8370_TBOP 0x0A1 /* RW: Tx BOP Codeword */ 513150849Sscottl#define Bt8370_RBOP 0x0A2 /* RO; Rx BOP Codeword */ 514150849Sscottl#define Bt8370_BOP_STAT 0x0A3 /* RO: BOP Status */ 515150849Sscottl#define Bt8370_DL1_TS 0x0A4 /* RW: DL1 Time Slot Enable */ 516150849Sscottl#define Bt8370_DL1_BIT 0x0A5 /* RW: DL1 Bit Enable */ 517150849Sscottl#define Bt8370_DL1_CTL 0x0A6 /* RW: DL1 Control */ 518150849Sscottl#define Bt8370_RDL1_FFC 0x0A7 /* RW: RDL1 FIFO Fill Control */ 519150849Sscottl#define Bt8370_RDL1 0x0A8 /* RO: RDL1 FIFO */ 520150849Sscottl#define Bt8370_RDL1_STAT 0x0A9 /* RO: RDL1 Status */ 521150849Sscottl#define Bt8370_PRM 0x0AA /* RW: Performance Report Message */ 522150849Sscottl#define Bt8370_TDL1_FEC 0x0AB /* RW: TDL1 FIFO Empty Control */ 523150849Sscottl#define Bt8370_TDL1_EOM 0x0AC /* WO: TDL1 End Of Message Control */ 524150849Sscottl#define Bt8370_TDL1 0x0AD /* RW: TDL1 FIFO */ 525150849Sscottl#define Bt8370_TDL1_STAT 0x0AE /* RO: TDL1 Status */ 526150849Sscottl#define Bt8370_DL2_TS 0x0AF /* RW: DL2 Time Slot Enable */ 527150849Sscottl 528150849Sscottl#define Bt8370_DL2_BIT 0x0B0 /* RW: DL2 Bit Enable */ 529150849Sscottl#define Bt8370_DL2_CTL 0x0B1 /* RW: DL2 Control */ 530150849Sscottl#define Bt8370_RDL2_FFC 0x0B2 /* RW: RDL2 FIFO Fill Control */ 531150849Sscottl#define Bt8370_RDL2 0x0B3 /* RO: RDL2 FIFO */ 532150849Sscottl#define Bt8370_RDL2_STAT 0x0B4 /* RO: RDL2 Status */ 533150849Sscottl#define Bt8370_TDL2_FEC 0x0B6 /* RW: TDL2 FIFO Empty Control */ 534150849Sscottl#define Bt8370_TDL2_EOM 0x0B7 /* WO; TDL2 End Of Message Control */ 535150849Sscottl#define Bt8370_TDL2 0x0B8 /* RW: TDL2 FIFO */ 536150849Sscottl#define Bt8370_TDL2_STAT 0x0B9 /* RO: TDL2 Status */ 537150849Sscottl#define Bt8370_DL_TEST1 0x0BA /* RW: DLINK Test Config */ 538150849Sscottl#define Bt8370_DL_TEST2 0x0BB /* RW: DLINK Test Status */ 539150849Sscottl#define Bt8370_DL_TEST3 0x0BC /* RW: DLINK Test Status */ 540150849Sscottl#define Bt8370_DL_TEST4 0x0BD /* RW: DLINK Test Control */ 541150849Sscottl#define Bt8370_DL_TEST5 0x0BE /* RW: DLINK Test Control */ 542150849Sscottl 543150849Sscottl#define Bt8370_SBI_CR 0x0D0 /* RW: System Bus Interface Config */ 544150849Sscottl#define Bt8370_RSB_CR 0x0D1 /* RW: Rx System Bus Config */ 545150849Sscottl#define Bt8370_RSYNC_BIT 0x0D2 /* RW: Rx System Bus Sync Bit Offs */ 546150849Sscottl#define Bt8370_RSYNC_TS 0x0D3 /* RW: Rx System Bus Sync TS Offs */ 547150849Sscottl#define Bt8370_TSB_CR 0x0D4 /* RW: Tx System Bus Config */ 548150849Sscottl#define Bt8370_TSYNC_BIT 0x0D5 /* RW: Tx System Bus Sync Bit OFfs */ 549150849Sscottl#define Bt8370_TSYNC_TS 0x0D6 /* RW: Tx System Bus Sync TS Offs */ 550150849Sscottl#define Bt8370_RSIG_CR 0x0D7 /* RW: Rx Siganalling Config */ 551150849Sscottl#define Bt8370_RSYNC_FRM 0x0D8 /* RW: Sig Reinsertion Frame Offs */ 552150849Sscottl#define Bt8370_SSTAT 0x0D9 /* RO: Slip Buffer Status */ 553150849Sscottl#define Bt8370_STACK 0x0DA /* RO: Rx Signalling Stack */ 554150849Sscottl#define Bt8370_RPHASE 0x0DB /* RO: RSLIP Phase Status */ 555150849Sscottl#define Bt8370_TPHASE 0x0DC /* RO: TSLIP Phase Status */ 556150849Sscottl#define Bt8370_PERR 0x0DD /* RO: RAM Parity Status */ 557150849Sscottl 558150849Sscottl#define Bt8370_SBCn 0x0E0 /* RW: System Bus Per-Channel Ctl */ 559150849Sscottl#define Bt8370_TPCn 0x100 /* RW: Tx Per-Channel Control */ 560150849Sscottl#define Bt8370_TSIGn 0x120 /* RW: Tx Signalling Buffer */ 561150849Sscottl#define Bt8370_TSLIP_LOn 0x140 /* RW: Tx PCM Slip Buffer Lo */ 562150849Sscottl#define Bt8370_TSLIP_HIn 0x160 /* RW: Tx PCM Slip Buffer Hi */ 563150849Sscottl#define Bt8370_RPCn 0x180 /* RW: Rx Per-Channel Control */ 564150849Sscottl#define Bt8370_RSIGn 0x1A0 /* RW: Rx Signalling Buffer */ 565150849Sscottl#define Bt8370_RSLIP_LOn 0x1C0 /* RW: Rx PCM Slip Buffer Lo */ 566150849Sscottl#define Bt8370_RSLIP_HIn 0x1E0 /* RW: Rx PCM Slip Buffer Hi */ 567150849Sscottl 568150849Sscottl/* Bt8370_LOOP (0x14) framer loopback control register bits */ 569150849Sscottl#define LOOP_ANALOG 0x01 /* inward loop thru LIU */ 570150849Sscottl#define LOOP_FRAMER 0x02 /* inward loop thru framer */ 571150849Sscottl#define LOOP_LINE 0x04 /* outward loop thru LIU */ 572150849Sscottl#define LOOP_PAYLOAD 0x08 /* outward loop of payload */ 573150849Sscottl#define LOOP_DUAL 0x06 /* inward framer + outward line */ 574150849Sscottl 575150849Sscottl/* Bt8370_ALM1 (0x47) receiver alarm status register bits */ 576150849Sscottl#define ALM1_SIGFRZ 0x01 /* Rx Signalling Freeze */ 577150849Sscottl#define ALM1_RLOF 0x02 /* Rx loss of frame alignment */ 578150849Sscottl#define ALM1_RLOS 0x04 /* Rx digital loss of signal */ 579150849Sscottl#define ALM1_RALOS 0x08 /* Rx analog loss of signal */ 580150849Sscottl#define ALM1_RAIS 0x10 /* Rx Alarm Indication Signal */ 581150849Sscottl#define ALM1_RYEL 0x40 /* Rx Yellow alarm indication */ 582150849Sscottl#define ALM1_RMYEL 0x80 /* Rx multiframe YELLOW alarm */ 583150849Sscottl 584150849Sscottl/* Bt8370_ALM3 (0x49) receive framer status register bits */ 585150849Sscottl#define ALM3_FRED 0x04 /* Rx Out Of T1/FAS alignment */ 586150849Sscottl#define ALM3_MRED 0x08 /* Rx Out Of MFAS alignment */ 587150849Sscottl#define ALM3_SRED 0x10 /* Rx Out Of CAS alignment */ 588150849Sscottl#define ALM3_SEF 0x20 /* Rx Severely Errored Frame */ 589150849Sscottl#define ALM3_RMAIS 0x40 /* Rx TS16 AIS (CAS) */ 590150849Sscottl 591150849Sscottl/* Bt8370_TALM (0x75) transmit alarm control register bits */ 592150849Sscottl#define TALM_TAIS 0x01 /* Tx Alarm Indication Signal */ 593150849Sscottl#define TALM_TYEL 0x02 /* Tx Yellow alarm */ 594150849Sscottl#define TALM_TMYEL 0x04 /* Tx Multiframe Yellow alarm */ 595150849Sscottl#define TALM_AUTO_AIS 0x08 /* auto send AIS on LOS */ 596150849Sscottl#define TALM_AUTO_YEL 0x10 /* auto send YEL on LOF */ 597150849Sscottl#define TALM_AUTO_MYEL 0x20 /* auto send E1-Y16 on loss-of-CAS */ 598150849Sscottl 599150849Sscottl/* 8370 BOP (Bit Oriented Protocol) command fragments */ 600150849Sscottl#define RBOP_OFF 0x00 /* BOP Rx disabled */ 601150849Sscottl#define RBOP_25 0xE0 /* BOP Rx requires 25 BOPs */ 602150849Sscottl#define TBOP_OFF 0x00 /* BOP Tx disabled */ 603150849Sscottl#define TBOP_25 0x0B /* BOP Tx sends 25 BOPs */ 604150849Sscottl#define TBOP_CONT 0x0F /* BOP Tx sends continuously */ 605150849Sscottl 606150849Sscottl/* T1.403 Bit-Oriented ESF Data-Link Message codes */ 607150849Sscottl#define T1BOP_OOF 0x00 /* Yellow alarm status */ 608150849Sscottl#define T1BOP_LINE_UP 0x07 /* line loopback activate */ 609150849Sscottl#define T1BOP_LINE_DOWN 0x1C /* line loopback deactivate */ 610150849Sscottl#define T1BOP_PAY_UP 0x0A /* payload loopback activate */ 611150849Sscottl#define T1BOP_PAY_DOWN 0x19 /* payload loopback deactivate */ 612150849Sscottl#define T1BOP_NET_UP 0x09 /* network loopback activate */ 613150849Sscottl#define T1BOP_NET_DOWN 0x12 /* network loopback deactivate */ 614150849Sscottl 615150849Sscottl/* Unix & Linux reserve 16 device-private IOCTLs */ 616150849Sscottl#if BSD 617150849Sscottl# define LMCIOCGSTAT _IOWR('i', 240, struct status) 618150849Sscottl# define LMCIOCGCFG _IOWR('i', 241, struct config) 619150849Sscottl# define LMCIOCSCFG _IOW('i', 242, struct config) 620150849Sscottl# define LMCIOCREAD _IOWR('i', 243, struct ioctl) 621150849Sscottl# define LMCIOCWRITE _IOW('i', 244, struct ioctl) 622150849Sscottl# define LMCIOCTL _IOWR('i', 245, struct ioctl) 623150849Sscottl#endif 624150849Sscottl 625150849Sscottlstruct iohdr /* all LMCIOCs begin with this */ 626150849Sscottl { 627150849Sscottl char ifname[IFNAMSIZ]; /* interface name, e.g. "lmc0" */ 628150849Sscottl u_int32_t cookie; /* interface version number */ 629150849Sscottl u_int16_t direction; /* missing in Linux IOCTL */ 630150849Sscottl u_int16_t length; /* missing in Linux IOCTL */ 631150849Sscottl struct iohdr *iohdr; /* missing in Linux IOCTL */ 632150849Sscottl u_int32_t spare; /* pad this struct to **32 bytes** */ 633150849Sscottl }; 634150849Sscottl 635150849Sscottl#define DIR_IO 0 636150849Sscottl#define DIR_IOW 1 /* copy data user->kernel */ 637150849Sscottl#define DIR_IOR 2 /* copy data kernel->user */ 638150849Sscottl#define DIR_IOWR 3 /* copy data kernel<->user */ 639150849Sscottl 640150849Sscottlstruct hssi_snmp 641150849Sscottl { 642150849Sscottl u_int16_t sigs; /* MII16_HSSI & MII16_HSSI_MODEM */ 643150849Sscottl }; 644150849Sscottl 645150849Sscottlstruct ssi_snmp 646150849Sscottl { 647150849Sscottl u_int16_t sigs; /* MII16_SSI & MII16_SSI_MODEM */ 648150849Sscottl }; 649150849Sscottl 650150849Sscottlstruct t3_snmp 651150849Sscottl { 652150849Sscottl u_int16_t febe; /* 8 bits - Far End Block err cnt */ 653150849Sscottl u_int16_t lcv; /* 16 bits - BPV err cnt */ 654150849Sscottl u_int16_t pcv; /* 8 bits - P-bit err cnt */ 655150849Sscottl u_int16_t ccv; /* 8 bits - C-bit err cnt */ 656150849Sscottl u_int16_t line; /* line status bit vector */ 657150849Sscottl u_int16_t loop; /* loop status bit vector */ 658150849Sscottl }; 659150849Sscottl 660150849Sscottlstruct t1_snmp 661150849Sscottl { 662150849Sscottl u_int16_t prm[4]; /* T1.403 Performance Report Msg */ 663150849Sscottl u_int16_t febe; /* 10 bits - E1 FAR CRC err cnt */ 664150849Sscottl u_int16_t lcv; /* 16 bits - BPV + EXZ err cnt */ 665150849Sscottl u_int16_t fe; /* 12 bits - Ft/Fs/FPS/FAS err cnt */ 666150849Sscottl u_int16_t crc; /* 10 bits - CRC6/CRC4 err cnt */ 667150849Sscottl u_int16_t line; /* line status bit vector */ 668150849Sscottl u_int16_t loop; /* loop status bit vector */ 669150849Sscottl }; 670150849Sscottl 671150849Sscottl/* SNMP trunk MIB Send codes */ 672150849Sscottl#define TSEND_NORMAL 1 /* Send data (normal or looped) */ 673150849Sscottl#define TSEND_LINE 2 /* Send 'line loopback activate' */ 674150849Sscottl#define TSEND_PAYLOAD 3 /* Send 'payload loop activate' */ 675150849Sscottl#define TSEND_RESET 4 /* Send 'loopback deactivate' */ 676150849Sscottl#define TSEND_QRS 5 /* Send Quasi Random Signal */ 677150849Sscottl 678150849Sscottl/* ANSI T1.403 Performance Report Msg -- once a second from the far end */ 679150849Sscottl#define T1PRM_FE 0x8000 /* Frame Sync Bit Error Event >= 1 */ 680150849Sscottl#define T1PRM_SE 0x4000 /* Severely Err Framing Event >= 1 */ 681150849Sscottl#define T1PRM_LB 0x2000 /* Payload Loopback Activated */ 682150849Sscottl#define T1PRM_G1 0x1000 /* CRC Error Event = 1 */ 683150849Sscottl#define T1PRM_R 0x0800 /* Reserved */ 684150849Sscottl#define T1PRM_G2 0x0400 /* 1 < CRC Error Event <= 5 */ 685150849Sscottl#define T1PRM_SEQ 0x0300 /* modulo 4 counter */ 686150849Sscottl#define T1PRM_G3 0x0080 /* 5 < CRC Error Event <= 10 */ 687150849Sscottl#define T1PRM_LV 0x0040 /* Line Code Violation Event >= 1 */ 688150849Sscottl#define T1PRM_G4 0x0020 /* 10 < CRC Error Event <= 100 */ 689150849Sscottl#define T1PRM_U 0x0018 /* Under study for synchronization */ 690150849Sscottl#define T1PRM_G5 0x0004 /* 100 < CRC Error Event <= 319 */ 691150849Sscottl#define T1PRM_SL 0x0002 /* Slip Event >= 1 */ 692150849Sscottl#define T1PRM_G6 0x0001 /* CRC Error Event >= 320 */ 693150849Sscottl 694150849Sscottl/* SNMP Line Status */ 695150849Sscottl#define TLINE_NORM 0x0001 /* no alarm present */ 696150849Sscottl#define TLINE_RX_RAI 0x0002 /* receiving RAI = Yellow alarm */ 697150849Sscottl#define TLINE_TX_RAI 0x0004 /* sending RAI = Yellow alarm */ 698150849Sscottl#define TLINE_RX_AIS 0x0008 /* receiving AIS = blue alarm */ 699150849Sscottl#define TLINE_TX_AIS 0x0010 /* sending AIS = blue alarm */ 700150849Sscottl#define TLINE_LOF 0x0020 /* near end LOF = red alarm */ 701150849Sscottl#define TLINE_LOS 0x0040 /* near end loss of Signal */ 702150849Sscottl#define TLINE_LOOP 0x0080 /* near end is looped */ 703150849Sscottl#define T1LINE_RX_TS16_AIS 0x0100 /* near end receiving TS16 AIS */ 704150849Sscottl#define T1LINE_RX_TS16_LOMF 0x0200 /* near end sending TS16 LOMF */ 705150849Sscottl#define T1LINE_TX_TS16_LOMF 0x0400 /* near end receiving TS16 LOMF */ 706150849Sscottl#define T1LINE_RX_TEST 0x0800 /* near end receiving QRS Signal */ 707150849Sscottl#define T1LINE_SEF 0x1000 /* near end severely errored frame */ 708150849Sscottl#define T3LINE_RX_IDLE 0x0100 /* near end receiving IDLE signal */ 709150849Sscottl#define T3LINE_SEF 0x0200 /* near end severely errored frame */ 710150849Sscottl 711150849Sscottl/* SNMP Loopback Status */ 712150849Sscottl#define TLOOP_NONE 0x01 /* no loopback */ 713150849Sscottl#define TLOOP_NEAR_PAYLOAD 0x02 /* near end payload loopback */ 714150849Sscottl#define TLOOP_NEAR_LINE 0x04 /* near end line loopback */ 715150849Sscottl#define TLOOP_NEAR_OTHER 0x08 /* near end looped somehow */ 716150849Sscottl#define TLOOP_NEAR_INWARD 0x10 /* near end looped inward */ 717150849Sscottl#define TLOOP_FAR_PAYLOAD 0x20 /* far end payload loopback */ 718150849Sscottl#define TLOOP_FAR_LINE 0x40 /* far end line loopback */ 719150849Sscottl 720150849Sscottl/* event counters record interesting statistics */ 721150849Sscottlstruct event_cntrs 722150849Sscottl { 723150849Sscottl struct timeval reset_time; /* time when cntrs were reset */ 724150849Sscottl u_int64_t ibytes; /* Rx bytes with good status */ 725150849Sscottl u_int64_t obytes; /* Tx bytes */ 726150849Sscottl u_int64_t ipackets; /* Rx packets with good status */ 727150849Sscottl u_int64_t opackets; /* Tx packets */ 728150849Sscottl u_int32_t ierrors; /* Rx packets with bad status */ 729150849Sscottl u_int32_t oerrors; /* Tx packets with bad status */ 730150849Sscottl u_int32_t idiscards; /* Rx packets discarded */ 731150849Sscottl u_int32_t odiscards; /* Tx packets discarded */ 732150849Sscottl u_int32_t fifo_over; /* Rx fifo overruns */ 733150849Sscottl u_int32_t fifo_under; /* Tx fifo underruns */ 734150849Sscottl u_int32_t missed; /* Rx pkts missed: no DMA descs */ 735150849Sscottl u_int32_t overruns; /* Rx pkts missed: fifo overrun */ 736150849Sscottl u_int32_t fdl_pkts; /* Rx T1 Facility Data Link pkts */ 737150849Sscottl u_int32_t crc_errs; /* Rx T1 frame CRC errors */ 738150849Sscottl u_int32_t lcv_errs; /* Rx T1 T3 Line Coding Violation */ 739150849Sscottl u_int32_t frm_errs; /* Rx T1 T3 Frame bit errors */ 740150849Sscottl u_int32_t febe_errs; /* Rx T1 T3 Far End Bit Errors */ 741150849Sscottl u_int32_t par_errs; /* Rx T3 P-bit parity errors */ 742150849Sscottl u_int32_t cpar_errs; /* Rx T3 C-bit parity errors */ 743150849Sscottl u_int32_t mfrm_errs; /* Rx T3 Multi-frame bit errors */ 744150849Sscottl u_int32_t rxdma; /* Rx out of kernel buffers */ 745150849Sscottl u_int32_t txdma; /* Tx out of DMA desciptors */ 746150849Sscottl u_int32_t lck_watch; /* try_lock conflict in watchdog */ 747150849Sscottl u_int32_t lck_ioctl; /* try_lock conflict in ioctl */ 748150849Sscottl u_int32_t lck_intr; /* try_lock conflict in interrupt */ 749150849Sscottl }; 750150849Sscottl 751150849Sscottl/* sc->status is the READ ONLY status of the card. */ 752150849Sscottl/* Accessed using socket IO control calls or netgraph control messages. */ 753150849Sscottlstruct status 754150849Sscottl { 755150849Sscottl struct iohdr iohdr; /* common ioctl header */ 756150849Sscottl u_int32_t card_type; /* PCI device number */ 757150849Sscottl u_int16_t ieee[3]; /* IEEE MAC-addr from Tulip SROM */ 758150849Sscottl u_int16_t oper_status; /* actual state: up, down, test */ 759150849Sscottl u_int32_t tx_speed; /* measured TX bits/sec */ 760150849Sscottl u_int32_t cable_type; /* SSI only: cable type */ 761150849Sscottl u_int32_t line_pkg; /* actual line pkg in use */ 762150849Sscottl u_int32_t line_prot; /* actual line proto in use */ 763150849Sscottl u_int32_t ticks; /* incremented by watchdog @ 1 Hz */ 764150849Sscottl struct event_cntrs cntrs; /* event counters */ 765150849Sscottl union 766150849Sscottl { 767150849Sscottl struct hssi_snmp hssi; /* data for RFC-???? HSSI MIB */ 768150849Sscottl struct t3_snmp t3; /* data for RFC-2496 T3 MIB */ 769150849Sscottl struct ssi_snmp ssi; /* data for RFC-1659 RS232 MIB */ 770150849Sscottl struct t1_snmp t1; /* data for RFC-2495 T1 MIB */ 771150849Sscottl } snmp; 772150849Sscottl }; 773150849Sscottl 774150849Sscottl/* line protocol package codes fnobl */ 775150849Sscottl#define PKG_RAWIP 1 /* driver yyyyy */ 776150849Sscottl#define PKG_SPPP 2 /* fbsd, nbsd, obsd yyynn */ 777150849Sscottl#define PKG_P2P 3 /* bsd/os nnnyn */ 778150849Sscottl#define PKG_NG 4 /* fbsd ynnnn */ 779150849Sscottl#define PKG_GEN_HDLC 5 /* linux nnnny */ 780150849Sscottl 781150849Sscottl/* line protocol codes fnobl */ 782150849Sscottl#define PROT_PPP 1 /* Point-to-Point Protocol yyyyy */ 783150849Sscottl#define PROT_C_HDLC 2 /* Cisco HDLC Protocol yyyyy */ 784150849Sscottl#define PROT_FRM_RLY 3 /* Frame Relay Protocol ynnyy */ 785150849Sscottl#define PROT_X25 4 /* X.25/LAPB Protocol nnnny */ 786150849Sscottl#define PROT_ETH_HDLC 5 /* raw Ether pkts in HDLC nnnny */ 787150849Sscottl#define PROT_IP_HDLC 6 /* raw IP4/6 pkts in HDLC yyyyy */ 788150849Sscottl 789150849Sscottl/* oper_status codes (same as SNMP status codes) */ 790150849Sscottl#define STATUS_UP 1 /* may/will tx/rx pkts */ 791150849Sscottl#define STATUS_DOWN 2 /* can't/won't tx/rx pkts */ 792150849Sscottl#define STATUS_TEST 3 /* currently not used */ 793150849Sscottl 794150849Sscottlstruct synth /* programmable oscillator params */ 795150849Sscottl { 796150849Sscottl unsigned n :7; /* numerator (3..127) */ 797150849Sscottl unsigned m :7; /* denominator (3..127) */ 798150849Sscottl unsigned v :1; /* mul by 1|8 */ 799150849Sscottl unsigned x :2; /* div by 1|2|4|8 */ 800150849Sscottl unsigned r :2; /* div by 1|2|4|8 */ 801150849Sscottl unsigned prescale :13; /* log(final divisor): 2, 4 or 9 */ 802150849Sscottl } __attribute__ ((packed)); 803150849Sscottl 804150849Sscottl#define SYNTH_FREF 20e6 /* reference xtal = 20 MHz */ 805150849Sscottl#define SYNTH_FMIN 50e6 /* internal VCO min 50 MHz */ 806150849Sscottl#define SYNTH_FMAX 250e6 /* internal VCO max 250 MHz */ 807150849Sscottl 808150849Sscottl/* sc->config is the READ/WRITE configuration of the card. */ 809150849Sscottl/* Accessed using socket IO control calls or netgraph control messages. */ 810150849Sscottlstruct config 811150849Sscottl { 812150849Sscottl struct iohdr iohdr; /* common ioctl header */ 813150849Sscottl u_int32_t crc_len; /* ALL: CRC-16 or CRC-32 or none */ 814150849Sscottl u_int32_t loop_back; /* ALL: many kinds of loopbacks */ 815150849Sscottl u_int32_t tx_clk_src; /* T1, HSSI: ST, RT, int, ext */ 816150849Sscottl u_int32_t format; /* T3, T1: ckt framing format */ 817150849Sscottl u_int32_t time_slots; /* T1: 64Kb time slot config */ 818150849Sscottl u_int32_t cable_len; /* T3, T1: cable length in meters */ 819150849Sscottl u_int32_t scrambler; /* T3: payload scrambler config */ 820150849Sscottl u_int32_t dte_dce; /* SSI, HSSIc: drive TXCLK */ 821150849Sscottl struct synth synth; /* SSI, HSSIc: synth oscil params */ 822150849Sscottl u_int32_t rx_gain; /* T1: receiver gain limit 0-50 dB */ 823150849Sscottl u_int32_t tx_pulse; /* T1: transmitter pulse shape */ 824150849Sscottl u_int32_t tx_lbo; /* T1: transmitter atten 0-22.5 dB */ 825150849Sscottl u_int32_t debug; /* ALL: extra printout */ 826150849Sscottl u_int32_t line_pkg; /* ALL: use this line pkg */ 827150849Sscottl u_int32_t line_prot; /* SPPP: use this line proto */ 828150849Sscottl u_int32_t keep_alive; /* SPPP: use keep-alive packets */ 829150849Sscottl }; 830150849Sscottl 831150849Sscottl#define CFG_CRC_0 0 /* no CRC */ 832150849Sscottl#define CFG_CRC_16 2 /* X^16+X^12+X^5+1 (default) */ 833150849Sscottl#define CFG_CRC_32 4 /* X^32+X^26+X^23+X^22+X^16+X^12+ */ 834150849Sscottl /* X^11+X^10+X^8+X^7+X^5+X^4+X^2+X+1 */ 835150849Sscottl#define CFG_LOOP_NONE 1 /* SNMP don't loop back anything */ 836150849Sscottl#define CFG_LOOP_PAYLOAD 2 /* SNMP loop outward thru framer */ 837150849Sscottl#define CFG_LOOP_LINE 3 /* SNMP loop outward thru LIU */ 838150849Sscottl#define CFG_LOOP_OTHER 4 /* SNMP loop inward thru LIU */ 839150849Sscottl#define CFG_LOOP_INWARD 5 /* SNMP loop inward thru framer */ 840150849Sscottl#define CFG_LOOP_DUAL 6 /* SNMP loop inward & outward */ 841150849Sscottl#define CFG_LOOP_TULIP 16 /* ALL: loop inward thru Tulip */ 842150849Sscottl#define CFG_LOOP_PINS 17 /* HSSIc, SSI: loop inward-pins */ 843150849Sscottl#define CFG_LOOP_LL 18 /* HSSI, SSI: assert LA/LL mdm pin */ 844150849Sscottl#define CFG_LOOP_RL 19 /* HSSI, SSI: assert LB/RL mdm pin */ 845150849Sscottl 846150849Sscottl#define CFG_CLKMUX_ST 1 /* TX clk <- Send timing */ 847150849Sscottl#define CFG_CLKMUX_INT 2 /* TX clk <- internal source */ 848150849Sscottl#define CFG_CLKMUX_RT 3 /* TX clk <- Receive (loop) timing */ 849150849Sscottl#define CFG_CLKMUX_EXT 4 /* TX clk <- ext connector */ 850150849Sscottl 851150849Sscottl/* values 0-31 are Bt8370 CR0 register values (LSB is zero if E1). */ 852150849Sscottl/* values 32-99 are reserved for other T1E1 formats, (even number if E1) */ 853150849Sscottl/* values 100 and up are used for T3 frame formats. */ 854150849Sscottl#define CFG_FORMAT_T1SF 9 /* T1-SF AMI */ 855150849Sscottl#define CFG_FORMAT_T1ESF 27 /* T1-ESF+CRC B8ZS X^6+X+1 */ 856150849Sscottl#define CFG_FORMAT_E1FAS 0 /* E1-FAS HDB3 TS0 */ 857150849Sscottl#define CFG_FORMAT_E1FASCRC 8 /* E1-FAS+CRC HDB3 TS0 X^4+X+1 */ 858150849Sscottl#define CFG_FORMAT_E1FASCAS 16 /* E1-FAS +CAS HDB3 TS0 & TS16 */ 859150849Sscottl#define CFG_FORMAT_E1FASCRCCAS 24 /* E1-FAS+CRC+CAS HDB3 TS0 & TS16 */ 860150849Sscottl#define CFG_FORMAT_E1NONE 32 /* E1-NO framing HDB3 */ 861150849Sscottl#define CFG_FORMAT_T3CPAR 100 /* T3-C-Bit par B3ZS */ 862150849Sscottl#define CFG_FORMAT_T3M13 101 /* T3-M13 format B3ZS */ 863150849Sscottl 864150849Sscottl/* format aliases that improve code readability */ 865150849Sscottl#define FORMAT_T1ANY ((sc->config.format & 1)==1) 866150849Sscottl#define FORMAT_E1ANY ((sc->config.format & 1)==0) 867150849Sscottl#define FORMAT_E1CAS ((sc->config.format & 0x11)==0x10) 868150849Sscottl#define FORMAT_E1CRC ((sc->config.format & 0x09)==0x08) 869150849Sscottl#define FORMAT_E1NONE (sc->config.format == CFG_FORMAT_E1NONE) 870150849Sscottl#define FORMAT_T1ESF (sc->config.format == CFG_FORMAT_T1ESF) 871150849Sscottl#define FORMAT_T1SF (sc->config.format == CFG_FORMAT_T1SF) 872150849Sscottl#define FORMAT_T3CPAR (sc->config.format == CFG_FORMAT_T3CPAR) 873150849Sscottl 874150849Sscottl#define CFG_SCRAM_OFF 1 /* DS3 payload scrambler off */ 875150849Sscottl#define CFG_SCRAM_DL_KEN 2 /* DS3 DigitalLink/Kentrox X^43+1 */ 876150849Sscottl#define CFG_SCRAM_LARS 3 /* DS3 Larscom X^20+X^17+1 w/28ZS */ 877150849Sscottl 878150849Sscottl#define CFG_DTE 1 /* HSSIc, SSI: rcv TXCLK; rcv DCD */ 879150849Sscottl#define CFG_DCE 2 /* HSSIc, SSI: drv TXCLK; drv DCD */ 880150849Sscottl 881150849Sscottl#define CFG_GAIN_SHORT 0x24 /* 0-20 dB of equalized gain */ 882150849Sscottl#define CFG_GAIN_MEDIUM 0x2C /* 0-30 dB of equalized gain */ 883150849Sscottl#define CFG_GAIN_LONG 0x34 /* 0-40 dB of equalized gain */ 884150849Sscottl#define CFG_GAIN_EXTEND 0x3F /* 0-64 dB of equalized gain */ 885150849Sscottl#define CFG_GAIN_AUTO 0xFF /* auto-set based on cable length */ 886150849Sscottl 887150849Sscottl#define CFG_PULSE_T1DSX0 0 /* T1 DSX 0- 40 meters */ 888150849Sscottl#define CFG_PULSE_T1DSX1 2 /* T1 DSX 40- 80 meters */ 889150849Sscottl#define CFG_PULSE_T1DSX2 4 /* T1 DSX 80-120 meters */ 890150849Sscottl#define CFG_PULSE_T1DSX3 6 /* T1 DSX 120-160 meters */ 891150849Sscottl#define CFG_PULSE_T1DSX4 8 /* T1 DSX 160-200 meters */ 892150849Sscottl#define CFG_PULSE_E1COAX 10 /* E1 75 ohm coax pair */ 893150849Sscottl#define CFG_PULSE_E1TWIST 12 /* E1 120 ohm twisted pairs */ 894150849Sscottl#define CFG_PULSE_T1CSU 14 /* T1 CSU 200-2000 meters; set LBO */ 895150849Sscottl#define CFG_PULSE_AUTO 0xFF /* auto-set based on cable length */ 896150849Sscottl 897150849Sscottl#define CFG_LBO_0DB 0 /* T1CSU LBO = 0.0 dB; FCC opt A */ 898150849Sscottl#define CFG_LBO_7DB 16 /* T1CSU LBO = 7.5 dB; FCC opt B */ 899150849Sscottl#define CFG_LBO_15DB 32 /* T1CSU LBO = 15.0 dB; FCC opt C */ 900150849Sscottl#define CFG_LBO_22DB 48 /* T1CSU LBO = 22.5 dB; final span */ 901150849Sscottl#define CFG_LBO_AUTO 0xFF /* auto-set based on cable length */ 902150849Sscottl 903150849Sscottlstruct ioctl 904150849Sscottl { 905150849Sscottl struct iohdr iohdr; /* common ioctl header */ 906150849Sscottl u_int32_t cmd; /* command */ 907150849Sscottl u_int32_t address; /* command address */ 908150849Sscottl u_int32_t data; /* command data */ 909150849Sscottl char *ucode; /* user-land address of ucode */ 910150849Sscottl }; 911150849Sscottl 912150849Sscottl#define IOCTL_RW_PCI 1 /* RW: Tulip PCI config registers */ 913150849Sscottl#define IOCTL_RW_CSR 2 /* RW: Tulip Control & Status Regs */ 914150849Sscottl#define IOCTL_RW_SROM 3 /* RW: Tulip Serial Rom */ 915150849Sscottl#define IOCTL_RW_BIOS 4 /* RW: Tulip Boot rom */ 916150849Sscottl#define IOCTL_RW_MII 5 /* RW: MII registers */ 917150849Sscottl#define IOCTL_RW_FRAME 6 /* RW: Framer registers */ 918150849Sscottl#define IOCTL_WO_SYNTH 7 /* WO: Synthesized oscillator */ 919150849Sscottl#define IOCTL_WO_DAC 8 /* WO: Digital/Analog Converter */ 920150849Sscottl 921150849Sscottl#define IOCTL_XILINX_RESET 16 /* reset Xilinx: all FFs set to 0 */ 922150849Sscottl#define IOCTL_XILINX_ROM 17 /* load Xilinx program from ROM */ 923150849Sscottl#define IOCTL_XILINX_FILE 18 /* load Xilinx program from file */ 924150849Sscottl 925150849Sscottl#define IOCTL_SET_STATUS 50 /* set mdm ctrl bits (internal use)*/ 926150849Sscottl#define IOCTL_SNMP_SEND 51 /* trunk MIB send code */ 927150849Sscottl#define IOCTL_SNMP_LOOP 52 /* trunk MIB loop configuration */ 928150849Sscottl#define IOCTL_SNMP_SIGS 53 /* RS232-like modem control sigs */ 929150849Sscottl#define IOCTL_RESET_CNTRS 54 /* reset event counters */ 930150849Sscottl 931150849Sscottl/* storage for these strings is allocated here! */ 932257236Ssbrunostatic const char *ssi_cables[] = 933150849Sscottl { 934150849Sscottl "V.10/EIA423", 935150849Sscottl "V.11/EIA530A", 936150849Sscottl "RESERVED", 937150849Sscottl "X.21", 938150849Sscottl "V.35", 939150849Sscottl "V.36/EIA449", 940150849Sscottl "V.28/EIA232", 941150849Sscottl "NO CABLE", 942150849Sscottl NULL, 943150849Sscottl }; 944150849Sscottl 945150849Sscottl/***************************************************************************/ 946150849Sscottl/* Declarations above here are shared with the user lmcconfig program. */ 947150849Sscottl/* Declarations below here are private to the kernel device driver. */ 948150849Sscottl/***************************************************************************/ 949150849Sscottl 950150849Sscottl#if (_KERNEL || KERNEL || __KERNEL__) 951150849Sscottl 952150849Sscottl#define SNDQ_MAXLEN 32 /* packets awaiting transmission */ 953150849Sscottl#define DESCS_PER_PKT 4 /* DMA descriptors per TX pkt */ 954150849Sscottl#define NUM_TX_DESCS (DESCS_PER_PKT * SNDQ_MAXLEN) 955150849Sscottl/* Increase DESCS_PER_PKT if status.cntrs.txdma increments. */ 956150849Sscottl 957150849Sscottl/* A Tulip DMA descriptor can point to two chunks of memory. 958150849Sscottl * Each chunk has a max length of 2047 bytes (ask the VMS guys...). 959150849Sscottl * 2047 isn't a multiple of a cache line size (32 bytes typically). 960150849Sscottl * So back off to 2048-32 = 2016 bytes per chunk (2 chunks per descr). 961150849Sscottl */ 962150849Sscottl#define MAX_CHUNK_LEN 2016 963150849Sscottl#define MAX_DESC_LEN (2 * MAX_CHUNK_LEN) 964150849Sscottl 965150849Sscottl/* Tulip DMA descriptor; THIS STRUCT MUST MATCH THE HARDWARE */ 966150849Sscottlstruct dma_desc 967150849Sscottl { 968150849Sscottl u_int32_t status; /* hardware->to->software */ 969150849Sscottl#if (BYTE_ORDER == LITTLE_ENDIAN) /* left-to-right packing by compiler */ 970150849Sscottl unsigned length1:11; /* buffer1 length */ 971150849Sscottl unsigned length2:11; /* buffer2 length */ 972150849Sscottl unsigned control:10; /* software->to->hardware */ 973150849Sscottl#else /* right-to-left packing by compiler */ 974150849Sscottl unsigned control:10; /* software->to->hardware */ 975150849Sscottl unsigned length2:11; /* buffer2 length */ 976150849Sscottl unsigned length1:11; /* buffer1 length */ 977150849Sscottl#endif 978150849Sscottl u_int32_t address1; /* buffer1 bus address */ 979150849Sscottl u_int32_t address2; /* buffer2 bus address */ 980150849Sscottl bus_dmamap_t map; /* bus dmamap for this descriptor */ 981150849Sscottl# define TLP_BUS_DSL_VAL (sizeof(bus_dmamap_t) & TLP_BUS_DSL) 982150849Sscottl } __attribute__ ((packed)); 983150849Sscottl 984150849Sscottl/* Tulip DMA descriptor status bits */ 985150849Sscottl#define TLP_DSTS_OWNER 0x80000000 986150849Sscottl#define TLP_DSTS_RX_DESC_ERR 0x00004000 987150849Sscottl#define TLP_DSTS_RX_FIRST_DESC 0x00000200 988150849Sscottl#define TLP_DSTS_RX_LAST_DESC 0x00000100 989150849Sscottl#define TLP_DSTS_RX_MII_ERR 0x00000008 990150849Sscottl#define TLP_DSTS_RX_DRIBBLE 0x00000004 991150849Sscottl#define TLP_DSTS_TX_UNDERRUN 0x00000002 992150849Sscottl#define TLP_DSTS_RX_OVERRUN 0x00000001 /* not documented in rev AF */ 993150849Sscottl#define TLP_DSTS_RX_BAD (TLP_DSTS_RX_MII_ERR | \ 994150849Sscottl TLP_DSTS_RX_DRIBBLE | \ 995150849Sscottl TLP_DSTS_RX_DESC_ERR | \ 996150849Sscottl TLP_DSTS_RX_OVERRUN) 997150849Sscottl 998150849Sscottl/* Tulip DMA descriptor control bits */ 999150849Sscottl#define TLP_DCTL_TX_INTERRUPT 0x0200 1000150849Sscottl#define TLP_DCTL_TX_LAST_SEG 0x0100 1001150849Sscottl#define TLP_DCTL_TX_FIRST_SEG 0x0080 1002150849Sscottl#define TLP_DCTL_TX_NO_CRC 0x0010 1003150849Sscottl#define TLP_DCTL_END_RING 0x0008 1004150849Sscottl#define TLP_DCTL_TX_NO_PAD 0x0002 1005150849Sscottl 1006150849Sscottl/* DMA descriptors are kept in a ring. 1007150849Sscottl * Ring is empty when (read == write). 1008150849Sscottl * Ring is full when (read == wrap(write+1)), 1009150849Sscottl * The ring also contains a tailq of data buffers. 1010150849Sscottl */ 1011150849Sscottlstruct desc_ring 1012150849Sscottl { 1013150849Sscottl struct dma_desc *read; /* next descriptor to be read */ 1014150849Sscottl struct dma_desc *write; /* next descriptor to be written */ 1015150849Sscottl struct dma_desc *first; /* first descriptor in ring */ 1016150849Sscottl struct dma_desc *last; /* last descriptor in ring */ 1017150849Sscottl struct dma_desc *temp; /* temporary write pointer for tx */ 1018150849Sscottl u_int32_t dma_addr; /* bus address for desc array */ 1019150849Sscottl int size_descs; /* bus_dmamap_sync needs this */ 1020150849Sscottl int num_descs; /* used to set rx quota */ 1021272094Sglebius#if BSD 1022150849Sscottl struct mbuf *head; /* tail-queue of mbufs */ 1023150849Sscottl struct mbuf *tail; 1024150849Sscottl bus_dma_tag_t tag; /* bus_dma tag for desc array */ 1025150849Sscottl bus_dmamap_t map; /* bus_dma map for desc array */ 1026150849Sscottl bus_dma_segment_t segs[2]; /* bus_dmamap_load() or bus_dmamem_alloc() */ 1027150849Sscottl int nsegs; /* bus_dmamap_load() or bus_dmamem_alloc() */ 1028150849Sscottl#endif 1029150849Sscottl }; 1030150849Sscottl 1031150849Sscottl/* break circular definition */ 1032150849Sscottltypedef struct softc softc_t; 1033150849Sscottl 1034150849Sscottl/* card-dependent methods */ 1035150849Sscottlstruct card 1036150849Sscottl { 1037150849Sscottl void (* config)(softc_t *); 1038150849Sscottl void (* ident)(softc_t *); 1039150849Sscottl int (* watchdog)(softc_t *); /* must not sleep */ 1040150849Sscottl int (* ioctl)(softc_t *, struct ioctl *); /* can sleep */ 1041150849Sscottl }; 1042150849Sscottl 1043150849Sscottl/* flag bits in sc->flags */ 1044150849Sscottl#define FLAG_IFNET 0x00000002 /* IFNET is attached */ 1045150849Sscottl#define FLAG_NETDEV 0x00000004 /* NETDEV is registered */ 1046150849Sscottl#define FLAG_NETGRAPH 0x00000008 /* NETGRAPH is attached */ 1047150849Sscottl 1048150849Sscottl/* Accessing Tulip CSRs: 1049150849Sscottl * There are two ways: IO instruction (default) and memory reference. 1050150849Sscottl * IO refs are used if IOREF_CSR is defined; otherwise memory refs are used. 1051150849Sscottl * MEMORY REFERENCES DO NOT WORK in BSD/OS: page faults happen. 1052150849Sscottl */ 1053150849Sscottl#define IOREF_CSR 1 /* access Tulip CSRs with IO cycles if 1 */ 1054150849Sscottl 1055278881Simp#if defined(DEVICE_POLLING) 1056150849Sscottl# define DEV_POLL 1 1057150849Sscottl#else 1058150849Sscottl# define DEV_POLL 0 1059150849Sscottl#endif 1060150849Sscottl 1061153110Sru#if defined(ALTQ) && ALTQ 1062150849Sscottl# define ALTQ_PRESENT 1 1063150849Sscottl#else 1064150849Sscottl# define ALTQ_PRESENT 0 1065150849Sscottl#endif 1066150849Sscottl 1067150849Sscottl/* This is the instance data, or "software context" for the device driver. */ 1068150849Sscottl/* NetBSD, OpenBSD and BSD/OS want struct device first in the softc. */ 1069150849Sscottl/* FreeBSD wants struct ifnet first in the softc. */ 1070150849Sscottlstruct softc 1071150849Sscottl { 1072150849Sscottl 1073150849Sscottl 1074150849Sscottl /* State for kernel-resident Line Protocols */ 1075150849Sscottl#if IFNET 1076150849Sscottl struct ifnet *ifp; 1077150849Sscottl struct ifmedia ifm; /* hooks for ifconfig(8) */ 1078150849Sscottl# if NSPPP 1079150849Sscottl struct sppp *sppp; 1080150849Sscottl# elif P2P 1081150849Sscottl struct p2pcom p2pcom; 1082150849Sscottl struct p2pcom *p2p; 1083150849Sscottl# endif 1084150849Sscottl#endif 1085150849Sscottl 1086150849Sscottl 1087150849Sscottl#if NETGRAPH 1088150849Sscottl node_p ng_node; /* pointer to our node struct */ 1089150849Sscottl hook_p ng_hook; /* non-zero means NETGRAPH owns device */ 1090150849Sscottl struct ifaltq ng_sndq; 1091150849Sscottl struct ifaltq ng_fastq; 1092150849Sscottl#endif 1093150849Sscottl 1094199538Sjhb struct callout callout; /* watchdog needs this */ 1095299048Sadrian device_t dev; /* base device pointer */ 1096150849Sscottl bus_space_tag_t csr_tag; /* bus_space needs this */ 1097150849Sscottl bus_space_handle_t csr_handle;/* bus_space_needs this */ 1098150849Sscottl void *irq_cookie; /* bus_teardown_intr needs this */ 1099150849Sscottl struct resource *irq_res; /* bus_release_resource needs this */ 1100150849Sscottl int irq_res_id; /* bus_release_resource needs this */ 1101150849Sscottl struct resource *csr_res; /* bus_release_resource needs this */ 1102150849Sscottl int csr_res_id; /* bus_release resource needs this */ 1103150849Sscottl int csr_res_type; /* bus_release resource needs this */ 1104150849Sscottl struct mbuf *tx_mbuf; /* hang mbuf here while building dma descs */ 1105153110Sru# ifdef DEVICE_POLLING 1106150849Sscottl int quota; /* used for incoming packet flow control */ 1107150849Sscottl# endif 1108150849Sscottl struct mtx top_mtx; /* lock card->watchdog vs core_ioctl */ 1109150849Sscottl struct mtx bottom_mtx; /* lock for buf queues & descriptor rings */ 1110150849Sscottl 1111150849Sscottl 1112150849Sscottl /* Top-half state used by all card types; lock with top_lock, */ 1113150849Sscottl const char *dev_desc; /* string describing type of board */ 1114150849Sscottl struct status status; /* driver status lmcconfig can read */ 1115150849Sscottl struct config config; /* driver config lmcconfig can read/write */ 1116150849Sscottl struct card *card; /* card methods: config, ioctl, watchdog */ 1117150849Sscottl u_int32_t gpio_dir; /* s/w copy of GPIO direction register */ 1118150849Sscottl u_int16_t led_state; /* last value written to mii16 */ 1119150849Sscottl u_int32_t flags; /* driver-global flags */ 1120150849Sscottl 1121150849Sscottl /* Top-half state used by card-specific watchdogs; lock with top_lock. */ 1122150849Sscottl u_int32_t last_mii16; /* SSI, HSSI: MII reg 16 one second ago */ 1123150849Sscottl u_int32_t last_stat16; /* T3: framer reg 16 one second ago */ 1124150849Sscottl u_int32_t last_alm1; /* T1E1: framer reg 47 one second ago */ 1125150849Sscottl u_int32_t last_FEAC; /* last FEAC msg code received */ 1126150849Sscottl u_int32_t loop_timer; /* seconds until loopback expires */ 1127150849Sscottl 1128150849Sscottl /* Bottom-half state used by the interrupt code; lock with bottom_lock. */ 1129150849Sscottl struct desc_ring txring; /* tx descriptor ring state */ 1130150849Sscottl struct desc_ring rxring; /* rx descriptor ring state */ 1131150849Sscottl }; /* end of softc */ 1132150849Sscottl 1133150849Sscottl/* Hide the minor differences between OS versions */ 1134150849Sscottl 1135150849Sscottl typedef void intr_return_t; 1136150849Sscottl# define READ_PCI_CFG(sc, addr) pci_read_config ((sc)->dev, addr, 4) 1137150849Sscottl# define WRITE_PCI_CFG(sc, addr, data) pci_write_config((sc)->dev, addr, data, 4) 1138150849Sscottl# define READ_CSR(csr) bus_space_read_4 (sc->csr_tag, sc->csr_handle, csr) 1139150849Sscottl# define WRITE_CSR(csr, val) bus_space_write_4(sc->csr_tag, sc->csr_handle, csr, val) 1140150849Sscottl# define NAME_UNIT device_get_nameunit(sc->dev) 1141150849Sscottl# define DRIVER_DEBUG ((sc->config.debug) || (sc->ifp->if_flags & IFF_DEBUG)) 1142278881Simp# define TOP_TRYLOCK mtx_trylock(&sc->top_mtx) 1143278881Simp# define TOP_UNLOCK mtx_unlock (&sc->top_mtx) 1144278881Simp# define BOTTOM_TRYLOCK mtx_trylock(&sc->bottom_mtx) 1145278881Simp# define BOTTOM_UNLOCK mtx_unlock (&sc->bottom_mtx) 1146278881Simp# define CHECK_CAP priv_check(curthread, PRIV_DRIVER) 1147150849Sscottl# define DISABLE_INTR /* nothing */ 1148150849Sscottl# define ENABLE_INTR /* nothing */ 1149150849Sscottl# define IRQ_NONE /* nothing */ 1150150849Sscottl# define IRQ_HANDLED /* nothing */ 1151150849Sscottl# define IFP2SC(ifp) (ifp)->if_softc 1152150849Sscottl# define COPY_BREAK MHLEN 1153150849Sscottl# define SLEEP(usecs) tsleep(sc, PCATCH | PZERO, DEVICE_NAME, 1+(usecs/tick)) 1154150849Sscottl# define DMA_SYNC(map, size, flags) bus_dmamap_sync(ring->tag, map, flags) 1155150849Sscottl# define DMA_LOAD(map, addr, size) bus_dmamap_load(ring->tag, map, addr, size, fbsd_dmamap_load, ring, 0) 1156150849Sscottl# if (NBPFILTER != 0) 1157278881Simp# define LMC_BPF_MTAP(mbuf) BPF_MTAP(sc->ifp, mbuf) 1158150849Sscottl# define LMC_BPF_ATTACH(dlt, len) bpfattach(sc->ifp, dlt, len) 1159150849Sscottl# define LMC_BPF_DETACH bpfdetach(sc->ifp) 1160150849Sscottl# endif 1161278881Simp# define IF_DROP(ifq) _IF_DROP(ifq) 1162278881Simp# define IF_QFULL(ifq) _IF_QFULL(ifq) 1163278881Simp# define IFF_RUNNING IFF_DRV_RUNNING 1164150849Sscottl 1165150849Sscottl 1166150849Sscottl#if (NBPFILTER == 0) 1167150849Sscottl# define LMC_BPF_MTAP(mbuf) /* nothing */ 1168150849Sscottl# define LMC_BPF_ATTACH(dlt, len) /* nothing */ 1169150849Sscottl# define LMC_BPF_DETACH /* nothing */ 1170150849Sscottl#endif 1171150849Sscottl 1172150849Sscottl#define HSSI_DESC "SBE/LMC HSSI Card" 1173150849Sscottl#define T3_DESC "SBE/LMC T3 Card" 1174150849Sscottl#define SSI_DESC "SBE/LMC SSI Card" 1175150849Sscottl#define T1E1_DESC "SBE/LMC T1E1 Card" 1176150849Sscottl 1177150849Sscottl/* procedure prototypes */ 1178150849Sscottl 1179150849Sscottlstatic void shift_srom_bits(softc_t *, u_int32_t, u_int32_t); 1180150849Sscottlstatic u_int16_t read_srom(softc_t *, u_int8_t); 1181150849Sscottlstatic void write_srom(softc_t *, u_int8_t, u_int16_t); 1182150849Sscottl 1183150849Sscottlstatic u_int8_t read_bios(softc_t *, u_int32_t); 1184150849Sscottlstatic void write_bios_phys(softc_t *, u_int32_t, u_int8_t); 1185150849Sscottlstatic void write_bios(softc_t *, u_int32_t, u_int8_t); 1186150849Sscottlstatic void erase_bios(softc_t *); 1187150849Sscottl 1188150849Sscottlstatic void shift_mii_bits(softc_t *, u_int32_t, u_int32_t); 1189150849Sscottlstatic u_int16_t read_mii(softc_t *, u_int8_t); 1190150849Sscottlstatic void write_mii(softc_t *, u_int8_t, u_int16_t); 1191150849Sscottl 1192150849Sscottlstatic void set_mii16_bits(softc_t *, u_int16_t); 1193150849Sscottlstatic void clr_mii16_bits(softc_t *, u_int16_t); 1194150849Sscottlstatic void set_mii17_bits(softc_t *, u_int16_t); 1195150849Sscottlstatic void clr_mii17_bits(softc_t *, u_int16_t); 1196150849Sscottl 1197150849Sscottlstatic void led_off(softc_t *, u_int16_t); 1198150849Sscottlstatic void led_on(softc_t *, u_int16_t); 1199150849Sscottlstatic void led_inv(softc_t *, u_int16_t); 1200150849Sscottl 1201150849Sscottlstatic void write_framer(softc_t *, u_int16_t, u_int8_t); 1202150849Sscottlstatic u_int8_t read_framer(softc_t *, u_int16_t); 1203150849Sscottl 1204150849Sscottlstatic void make_gpio_input(softc_t *, u_int32_t); 1205150849Sscottlstatic void make_gpio_output(softc_t *, u_int32_t); 1206150849Sscottlstatic u_int32_t read_gpio(softc_t *); 1207150849Sscottlstatic void set_gpio_bits(softc_t *, u_int32_t); 1208150849Sscottlstatic void clr_gpio_bits(softc_t *, u_int32_t); 1209150849Sscottl 1210150849Sscottlstatic void reset_xilinx(softc_t *); 1211150849Sscottlstatic void load_xilinx_from_rom(softc_t *); 1212150849Sscottlstatic int load_xilinx_from_file(softc_t *, char *, u_int32_t); 1213150849Sscottl 1214150849Sscottlstatic void shift_synth_bits(softc_t *, u_int32_t, u_int32_t); 1215150849Sscottlstatic void write_synth(softc_t *, struct synth *); 1216150849Sscottl 1217150849Sscottlstatic void write_dac(softc_t *, u_int16_t); 1218150849Sscottl 1219150849Sscottlstatic void hssi_config(softc_t *); 1220150849Sscottlstatic void hssi_ident(softc_t *); 1221150849Sscottlstatic int hssi_watchdog(softc_t *); 1222150849Sscottlstatic int hssi_ioctl(softc_t *, struct ioctl *); 1223150849Sscottl 1224150849Sscottlstatic void t3_config(softc_t *); 1225150849Sscottlstatic void t3_ident(softc_t *); 1226150849Sscottlstatic int t3_watchdog(softc_t *); 1227150849Sscottlstatic void t3_send_dbl_feac(softc_t *, int, int); 1228150849Sscottlstatic int t3_ioctl(softc_t *, struct ioctl *); 1229150849Sscottl 1230150849Sscottlstatic void ssi_config(softc_t *); 1231150849Sscottlstatic void ssi_ident(softc_t *); 1232150849Sscottlstatic int ssi_watchdog(softc_t *); 1233150849Sscottlstatic int ssi_ioctl(softc_t *, struct ioctl *); 1234150849Sscottl 1235150849Sscottlstatic void t1_config(softc_t *); 1236150849Sscottlstatic void t1_ident(softc_t *); 1237150849Sscottlstatic int t1_watchdog(softc_t *); 1238150849Sscottlstatic void t1_send_bop(softc_t *, int); 1239150849Sscottlstatic int t1_ioctl(softc_t *, struct ioctl *); 1240150849Sscottl 1241150849Sscottl#if IFNET 1242180304Srwatsonstatic void lmc_raw_input(struct ifnet *, struct mbuf *); 1243150849Sscottl#endif /* IFNET */ 1244150849Sscottl 1245150849Sscottl#if BSD 1246150849Sscottlstatic void mbuf_enqueue(struct desc_ring *, struct mbuf *); 1247150849Sscottlstatic struct mbuf* mbuf_dequeue(struct desc_ring *); 1248150849Sscottlstatic void fbsd_dmamap_load(void *, bus_dma_segment_t *, int, int); 1249150849Sscottlstatic int create_ring(softc_t *, struct desc_ring *, int); 1250150849Sscottlstatic void destroy_ring(softc_t *, struct desc_ring *); 1251150849Sscottlstatic int rxintr_cleanup(softc_t *); 1252150849Sscottlstatic int rxintr_setup(softc_t *); 1253150849Sscottlstatic int txintr_cleanup(softc_t *); 1254150849Sscottlstatic int txintr_setup_mbuf(softc_t *, struct mbuf *); 1255150849Sscottlstatic int txintr_setup(softc_t *); 1256150849Sscottl#endif /* BSD */ 1257150849Sscottl 1258150849Sscottl 1259150849Sscottlstatic void check_intr_status(softc_t *); 1260150849Sscottlstatic void core_interrupt(void *, int); 1261150849Sscottlstatic void user_interrupt(softc_t *, int); 1262150849Sscottl#if BSD 1263153110Sru# if (defined(__FreeBSD__) && defined(DEVICE_POLLING)) 1264193105Sattiliostatic int fbsd_poll(struct ifnet *, enum poll_cmd, int); 1265150849Sscottl# endif 1266150849Sscottlstatic intr_return_t bsd_interrupt(void *); 1267150849Sscottl#endif /* BSD */ 1268150849Sscottl 1269150849Sscottlstatic void set_status(softc_t *, int); 1270150849Sscottl#if P2P 1271150849Sscottlstatic int p2p_getmdm(struct p2pcom *, caddr_t); 1272150849Sscottlstatic int p2p_mdmctl(struct p2pcom *, int); 1273150849Sscottl#endif 1274150849Sscottl#if NSPPP 1275150849Sscottlstatic void sppp_tls(struct sppp *); 1276150849Sscottlstatic void sppp_tlf(struct sppp *); 1277150849Sscottl#endif 1278150849Sscottl 1279150849Sscottlstatic void config_proto(softc_t *, struct config *); 1280150849Sscottlstatic int core_ioctl(softc_t *, u_long, caddr_t); 1281150849Sscottlstatic void core_watchdog(softc_t *); 1282150849Sscottl 1283150849Sscottl#if IFNET 1284180304Srwatsonstatic int lmc_raw_ioctl(struct ifnet *, u_long, caddr_t); 1285180304Srwatsonstatic int lmc_ifnet_ioctl(struct ifnet *, u_long, caddr_t); 1286180304Srwatsonstatic void lmc_ifnet_start(struct ifnet *); 1287180304Srwatsonstatic int lmc_raw_output(struct ifnet *, struct mbuf *, 1288249925Sglebius const struct sockaddr *, struct route *); 1289150849Sscottlstatic void setup_ifnet(struct ifnet *); 1290180304Srwatsonstatic int lmc_ifnet_attach(softc_t *); 1291180304Srwatsonstatic void lmc_ifnet_detach(softc_t *); 1292150849Sscottl#endif /* IFNET */ 1293150849Sscottl 1294150849Sscottl#if NETGRAPH 1295150849Sscottlstatic int ng_constructor(node_p); 1296150849Sscottlstatic int ng_rcvmsg(node_p, item_p, hook_p); 1297150849Sscottlstatic int ng_shutdown(node_p); 1298150849Sscottlstatic int ng_newhook(node_p, hook_p, const char *); 1299150849Sscottlstatic int ng_connect(hook_p); 1300150849Sscottlstatic int ng_rcvdata(hook_p, item_p); 1301150849Sscottlstatic int ng_disconnect(hook_p); 1302150849Sscottl# if (IFNET == 0) 1303150849Sscottlstatic void ng_watchdog(void *); 1304150849Sscottl# endif 1305150849Sscottlstatic int ng_attach(softc_t *); 1306150849Sscottlstatic void ng_detach(softc_t *); 1307150849Sscottl#endif /* NETGRAPH */ 1308150849Sscottl 1309150849Sscottlstatic int startup_card(softc_t *); 1310150849Sscottlstatic void shutdown_card(void *); 1311150849Sscottlstatic int attach_card(softc_t *, const char *); 1312150849Sscottlstatic void detach_card(softc_t *); 1313150849Sscottl 1314150849Sscottlstatic int fbsd_probe(device_t); 1315150849Sscottlstatic int fbsd_detach(device_t); 1316188178Simpstatic int fbsd_shutdown(device_t); 1317150849Sscottlstatic int fbsd_attach(device_t); 1318150849Sscottl 1319150849Sscottl 1320150849Sscottl 1321150849Sscottl 1322150849Sscottl 1323150849Sscottl#endif /* KERNEL */ 1324150849Sscottl 1325150849Sscottl#endif /* IF_LMC_H */ 1326