Searched refs:config1 (Results 1 - 25 of 85) sorted by path

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/linux-master/drivers/net/ethernet/seeq/
H A Dether3.h158 unsigned int config1; member in struct:dev_priv::__anon446
/linux-master/arch/arm/mach-imx/
H A Dmmdc.c165 PMU_FORMAT_ATTR(axi_id, "config1:0-63");
349 val = event->attr.config1;
/linux-master/arch/arm64/kvm/
H A Dpmu-emul.c653 attr.config1 |= PERF_ATTR_CFG1_COUNTER_64BIT;
/linux-master/arch/mips/cavium-octeon/executive/
H A Dcvmx-pko.c297 union cvmx_pko_reg_queue_ptrs1 config1; local
298 config1.u64 = 0;
299 config1.s.qid7 = queue >> 7;
300 cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
333 union cvmx_pko_reg_queue_ptrs1 config1; local
425 config1.u64 = 0;
426 config1.s.idx3 = queue >> 3;
427 config1.s.qid7 = (base_queue + queue) >> 7;
529 cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
/linux-master/arch/mips/include/asm/
H A Dkvm_host.h659 __BUILD_KVM_RW_HW(config1, 32, MIPS_CP0_CONFIG, 1)
684 __BUILD_KVM_SET_SAVED(config1, 32, MIPS_CP0_CONFIG, 1)
H A Dmipsregs.h3087 __BUILD_SET_GC0(config1)
/linux-master/arch/mips/kernel/
H A Dcpu-probe.c461 unsigned int config1; local
463 config1 = read_c0_config1();
465 if (config1 & MIPS_CONF1_MD)
467 if (config1 & MIPS_CONF1_PC)
469 if (config1 & MIPS_CONF1_WR)
471 if (config1 & MIPS_CONF1_CA)
473 if (config1 & MIPS_CONF1_EP)
475 if (config1 & MIPS_CONF1_FP) {
480 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
485 return config1
838 unsigned int config1, config1_dyn; local
[all...]
/linux-master/arch/mips/mm/
H A Dc-octeon.c174 unsigned int config1; local
178 config1 = read_c0_config1();
182 c->icache.linesz = 2 << ((config1 >> 19) & 7);
183 c->icache.sets = 64 << ((config1 >> 22) & 7);
184 c->icache.ways = 1 + ((config1 >> 16) & 7);
202 c->icache.linesz = 2 << ((config1 >> 19) & 7);
H A Dc-r4k.c1000 unsigned long config1; local
1123 config1 = read_c0_config1();
1124 lsize = (config1 >> 19) & 7;
1129 c->icache.sets = 64 << ((config1 >> 22) & 7);
1130 c->icache.ways = 1 + ((config1 >> 16) & 7);
1136 lsize = (config1 >> 10) & 7;
1141 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1142 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1176 config1 = read_c0_config1();
1178 lsize = (config1 >> 1
[all...]
H A Dsc-mips.c186 unsigned int config1, config2; local
203 config1 = read_c0_config1();
204 if (!(config1 & MIPS_CONF_M))
/linux-master/arch/powerpc/include/asm/
H A Dmpc52xx.h72 u32 config1; /* SDRAM + 0x08 */ member in struct:mpc52xx_sdram
/linux-master/arch/powerpc/perf/
H A Dcore-book3s.c994 &cpuhw->avalues[i][0], event[i]->attr.config1))
1030 event[i]->attr.config1);
H A Dhv-24x7.c178 EVENT_DEFINE_RANGE_FORMAT(lpar, config1, 0, 15);
181 EVENT_DEFINE_RANGE(reserved2, config1, 16, 63);
1403 event->attr.config1,
H A Dhv-gpci.c43 EVENT_DEFINE_RANGE_FORMAT(secondary_index, config1, 0, 15);
45 EVENT_DEFINE_RANGE_FORMAT(counter_info_version, config1, 16, 23);
47 EVENT_DEFINE_RANGE_FORMAT(length, config1, 24, 31);
49 EVENT_DEFINE_RANGE_FORMAT(offset, config1, 32, 63);
H A Disa207-common.c121 * and provided via attr.config1 parameter. To program threshold in MMCRA,
654 val = (pevents[i]->attr.config1 >> p10_EVENT_THR_CMP_SHIFT) &
/linux-master/arch/powerpc/platforms/83xx/
H A Dsuspend.c62 u32 config1; member in struct:mpc83xx_pmc
123 u32 reg_cfg1 = in_be32(&pmc_regs->config1);
133 out_be32(&pmc_regs->config1, reg_cfg1);
185 out_be32(&pmc_regs->config1,
186 in_be32(&pmc_regs->config1) | PMCCR1_PME_EN);
206 out_be32(&pmc_regs->config1,
207 in_be32(&pmc_regs->config1) | PMCCR1_POWER_OFF);
214 out_be32(&pmc_regs->config1,
215 in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF);
229 out_be32(&pmc_regs->config1,
[all...]
/linux-master/arch/riscv/kvm/
H A Dvcpu_pmu.c479 .config1 = RISCV_PMU_CONFIG1_GUEST_EVENTS,
/linux-master/arch/x86/events/amd/
H A Diommu.c55 PMU_FORMAT_ATTR(devid_mask, "config1:0-15");
56 PMU_FORMAT_ATTR(domid_mask, "config1:16-31");
57 PMU_FORMAT_ATTR(pasid_mask, "config1:32-51");
227 hwc->conf1 = event->attr.config1;
/linux-master/arch/x86/events/
H A Dcore.c172 if (event->attr.config1 & ~er->valid_mask)
179 reg->config = event->attr.config1;
391 attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result];
/linux-master/arch/x86/events/intel/
H A Dcore.c4011 if (event->attr.config1 || event->attr.config2)
5000 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
5002 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
5004 PMU_FORMAT_ATTR(frontend, "config1:0-23");
5006 PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63");
H A Duncore.c199 (er->config1 == reg1->config && er->config2 == reg2->config)) {
201 er->config1 = reg1->config;
H A Duncore.h134 u64 config, config1, config2; member in struct:intel_uncore_extra_reg
H A Duncore_nhmex.c197 DEFINE_UNCORE_FORMAT_ATTR(match, match, "config1:0-63");
372 reg1->config = event->attr.config1;
457 reg1->config = event->attr.config1;
674 u64 config1 = reg1->config; local
687 __BITS_VALUE(config1, i, 32)))
726 config1 = nhmex_mbox_alter_er(event, idx[0], false);
776 * config1 to pass two MSRs' config.
781 if (event->attr.config1 & ~er->valid_mask)
798 reg1->config = event->attr.config1;
874 DEFINE_UNCORE_FORMAT_ATTR(dsp, dsp, "config1
986 u64 config1; local
[all...]
H A Duncore_snbep.c497 DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4");
498 DEFINE_UNCORE_FORMAT_ATTR(filter_tid2, filter_tid, "config1:0");
499 DEFINE_UNCORE_FORMAT_ATTR(filter_tid3, filter_tid, "config1:0-5");
500 DEFINE_UNCORE_FORMAT_ATTR(filter_tid4, filter_tid, "config1:0-8");
501 DEFINE_UNCORE_FORMAT_ATTR(filter_tid5, filter_tid, "config1:0-9");
502 DEFINE_UNCORE_FORMAT_ATTR(filter_cid, filter_cid, "config1:5");
503 DEFINE_UNCORE_FORMAT_ATTR(filter_link, filter_link, "config1:5-8");
504 DEFINE_UNCORE_FORMAT_ATTR(filter_link2, filter_link, "config1:6-8");
505 DEFINE_UNCORE_FORMAT_ATTR(filter_link3, filter_link, "config1:12");
506 DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1
1084 u64 mask, config1 = reg1->config; local
[all...]
/linux-master/drivers/dma/idxd/
H A Dperfmon.c40 * These attributes specify the bits in the config1 word that the perf
43 DEFINE_PERFMON_FORMAT_ATTR(filter_wq, "config1:0-31");
44 DEFINE_PERFMON_FORMAT_ATTR(filter_tc, "config1:32-39");
45 DEFINE_PERFMON_FORMAT_ATTR(filter_pgsz, "config1:40-43");
46 DEFINE_PERFMON_FORMAT_ATTR(filter_sz, "config1:44-51");
47 DEFINE_PERFMON_FORMAT_ATTR(filter_eng, "config1:52-59");
337 flt_cfg.val = event->attr.config1;

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