Searched refs:cfg2 (Results 1 - 25 of 31) sorted by path

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/linux-master/arch/sparc/include/asm/
H A Dsbi.h22 /* 0x0018 */ u32 cfg2; /* Slot2 config reg */ member in struct:sbi_regs
/linux-master/arch/mips/kernel/
H A Dcpu-probe.c1656 u32 cfg2 = read_cpucfg(LOONGSON_CFG2); local
1662 if (cfg2 & LOONGSON_CFG2_LEXT1)
1665 if (cfg2 & LOONGSON_CFG2_LEXT2)
1668 if (cfg2 & LOONGSON_CFG2_LSPW) {
/linux-master/drivers/gpu/drm/exynos/
H A Dexynos_drm_fimc.c419 u32 cfg1, cfg2; local
427 cfg2 = fimc_read(ctx, EXYNOS_CITRGFMT);
428 cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
438 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
455 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
464 fimc_write(ctx, cfg2, EXYNOS_CITRGFMT);
/linux-master/drivers/gpu/drm/msm/dp/
H A Ddp_catalog.c948 u32 cfg, cfg2, misc;
953 cfg2 = dp_read_link(catalog, MMSS_DP_SDP_CFG2);
959 cfg2 |= GENERIC0_SDPSIZE_VALID;
960 dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2);
978 u32 cfg, cfg2, misc;
983 cfg2 = dp_read_link(catalog, MMSS_DP_SDP_CFG2);
989 cfg2 &= ~GENERIC0_SDPSIZE_VALID;
990 dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2);
950 u32 cfg, cfg2, misc; local
980 u32 cfg, cfg2, misc; local
/linux-master/drivers/hwmon/
H A Dadt7462.c76 #define ADT7462_PIN26_MASK 0x0C /* cfg2 */
207 u8 cfg2; member in struct:adt7462_data
768 data->cfg2 = i2c_smbus_read_byte_data(client, ADT7462_REG_CFG2);
1056 return sprintf(buf, "%d\n", (data->cfg2 & ADT7462_FSPD_MASK ? 1 : 0));
1077 data->cfg2 = reg;
/linux-master/drivers/iio/adc/
H A Dimx7d_adc.c237 u32 cfg2; local
259 cfg2 = readl(info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel +
262 cfg2 |= imx7d_adc_average_num[info->adc_feature.avg_num];
268 writel(cfg2, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel +
/linux-master/drivers/infiniband/hw/erdma/
H A Derdma_hw.h234 /* create_cq cfg2 */
245 u32 cfg2; member in struct:erdma_cmdq_create_cq_req
259 /* regmr cfg2 */
271 u32 cfg2; member in struct:erdma_cmdq_reg_mr_req
H A Derdma_verbs.c161 req.cfg2 = FIELD_PREP(ERDMA_CMD_REGMR_PAGESIZE_MASK,
176 req.cfg2 |= FIELD_PREP(ERDMA_CMD_REGMR_MTT_PAGESIZE_MASK,
241 req.cfg2 = FIELD_PREP(ERDMA_CMD_CREATE_CQ_DB_CFG_MASK,
/linux-master/drivers/media/platform/atmel/
H A Datmel-isi.c146 u32 cfg2, psize; local
153 /* According to sensor's output format to set cfg2 */
154 cfg2 = isi->current_fmt->swap;
158 cfg2 |= ((isi->fmt.fmt.pix.width - 1) << ISI_CFG2_IM_HSIZE_OFFSET) &
161 cfg2 |= ((isi->fmt.fmt.pix.height - 1) << ISI_CFG2_IM_VSIZE_OFFSET)
163 isi_writel(isi, ISI_CFG2, cfg2);
/linux-master/drivers/mmc/host/
H A Drtsx_pci_sdmmc.c437 u8 cfg2 = 0; local
450 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
469 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
495 u8 cfg2; local
506 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
510 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
528 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
H A Drtsx_usb_sdmmc.c454 u8 cfg2, trans_mode; local
463 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
469 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
506 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
/linux-master/drivers/net/ethernet/agere/
H A Det131x.c870 u32 cfg2; local
876 cfg2 = readl(&mac->cfg2);
880 cfg2 &= ~ET_MAC_CFG2_IFMODE_MASK;
882 cfg2 |= ET_MAC_CFG2_IFMODE_1000;
885 cfg2 |= ET_MAC_CFG2_IFMODE_100;
901 cfg2 |= 0x7 << ET_MAC_CFG2_PREAMBLE_SHIFT;
902 cfg2 |= ET_MAC_CFG2_IFMODE_LEN_CHECK;
903 cfg2 |= ET_MAC_CFG2_IFMODE_PAD_CRC;
904 cfg2 |
[all...]
H A Det131x.h1048 u32 cfg2; /* 0x5004 */ member in struct:mac_regs
/linux-master/drivers/net/ethernet/atheros/
H A Dag71xx.c1043 u32 cfg1, cfg2; local
1047 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
1048 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
1049 cfg2 |= duplex ? MAC_CFG2_FDX : 0;
1059 cfg2 |= MAC_CFG2_IF_1000;
1063 cfg2 |= MAC_CFG2_IF_10_100;
1067 cfg2 |= MAC_CFG2_IF_10_100;
1073 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
/linux-master/drivers/net/ethernet/broadcom/
H A Dtg3.c15245 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0; local
15258 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15292 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15386 if (cfg2 & (1 << 17))
15391 if (cfg2 & (1 << 18))
15397 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
/linux-master/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_mactable.c138 u32 mach, macl, cfg2; local
141 cfg2 = spx5_rd(sparx5, LRN_MAC_ACCESS_CFG_2);
142 if (LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(cfg2)) {
152 *pcfg2 = cfg2;
162 u32 cfg2; local
179 ret = sparx5_mact_get(sparx5, mac, vid, &cfg2);
181 *pcfg2 = cfg2;
193 u32 cfg2; local
206 cfg2 = spx5_rd(sparx5, LRN_MAC_ACCESS_CFG_2);
207 if (LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(cfg2))
296 u32 cfg2; local
361 sparx5_mact_handle_entry(struct sparx5 *sparx5, unsigned char mac[ETH_ALEN], u16 vid, u32 cfg2) argument
427 u32 cfg2; local
[all...]
/linux-master/drivers/net/wireless/ath/ath11k/
H A Ddebugfs_htt_stats.c4673 cfg_params->cfg2 |= FIELD_PREP(GENMASK(7, 0), mac_addr[0]);
4674 cfg_params->cfg2 |= FIELD_PREP(GENMASK(15, 8), mac_addr[1]);
4675 cfg_params->cfg2 |= FIELD_PREP(GENMASK(23, 16), mac_addr[2]);
4676 cfg_params->cfg2 |= FIELD_PREP(GENMASK(31, 24), mac_addr[3]);
4699 cfg_params->cfg2 |= FIELD_PREP(GENMASK(7, 0), mac_addr[4]);
4700 cfg_params->cfg2 |= FIELD_PREP(GENMASK(15, 8), mac_addr[5]);
H A Ddebugfs_sta.c721 cfg_params.cfg2 |= FIELD_PREP(GENMASK(7, 0), sta->addr[0]);
722 cfg_params.cfg2 |= FIELD_PREP(GENMASK(15, 8), sta->addr[1]);
723 cfg_params.cfg2 |= FIELD_PREP(GENMASK(23, 16), sta->addr[2]);
724 cfg_params.cfg2 |= FIELD_PREP(GENMASK(31, 24), sta->addr[3]);
H A Ddp.h1570 u32 cfg2; member in struct:htt_ext_stats_cfg_params
H A Ddp_tx.c1162 cmd->cfg_param2 = cfg_params->cfg2;
/linux-master/drivers/net/wireless/ath/ath12k/
H A Ddp.h1793 u32 cfg2; member in struct:htt_ext_stats_cfg_params
H A Ddp_tx.c1026 cmd->cfg_param2 = cpu_to_le32(cfg_params->cfg2);
/linux-master/drivers/net/wireless/realtek/rtl8xxxu/
H A D8710b.c574 u32 cfg0, cfg2, vendor; local
647 cfg2 = rtl8710b_read_syson_reg(priv, REG_SYS_SYSTEM_CFG2_8710B);
648 priv->rom_rev = cfg2 & 0xf;
/linux-master/drivers/perf/
H A Dfsl_imx8_ddr_perf.c557 int cfg2 = event->attr.config2; local
589 cfg2 ^= READ_CHANNEL_REVERT;
590 cfg2 |= FIELD_PREP(READ_PORT_MASK, cfg2);
593 cfg2 ^= WRITE_CHANNEL_REVERT;
594 cfg2 |= FIELD_PREP(WRITE_PORT_MASK, cfg2);
597 writel(cfg2, pmu->base + COUNTER_MUX_CNTL + ((counter - 1) << 4));
H A Dfsl_imx9_ddr_perf.c364 static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2) argument
390 pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, cfg2);
469 int cfg2 = event->attr.config2; local
483 ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2);

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